CN110618828A

CN110618828A - Data updating method and device

Info

Publication number: CN110618828A
Application number: CN201910818309.4A
Authority: CN
Inventors: 王连香
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-08-30
Filing date: 2019-08-30
Publication date: 2019-12-27
Anticipated expiration: 2039-08-30
Also published as: CN110618828B

Abstract

The application provides a data updating method and a data updating device, wherein the method comprises the following steps: after receiving a firmware FW updating instruction sent by a BMC, a CPLD judges whether the FW information of a specified backboard needs to be updated according to identification information and FW information of the specified backboard carried in the specified FW updating instruction and current FW information of the specified backboard stored by the CPLD; and if the FW information of the specified backboard needs to be updated, writing the FW information carried in the FW updating instruction into the specified backboard, and updating the current FW information of the specified backboard stored in the CPLD into the FW information carried in the FW updating instruction. The technical scheme can reduce the using number of channels of the BMC chip I2C, and provides possibility for the BMC for other information management. Meanwhile, the use of an I2C Switch chip and an I2C driver chip is saved, and the hardware design cost is reduced.

Description

Data updating method and device

Technical Field

The present invention relates to the field of computers, and in particular, to a data updating method and apparatus.

Background

In the server system, a BMC (Baseboard Management Controller) is used as an external interface for server motherboard Management and is responsible for providing basic Management information to users and hardware design and debugging personnel. The method comprises the functions of collecting and displaying FW (Firmware) versions of main chips of a mainboard, versions of an operating system, on-site information of a hard disk, online refreshing of FW of a server backboard and the like. When the BMC performs FW refresh to a backplane EEPROM (Electrically erasable programmable read only memory), I2C (Inter-Integrated Circuit) protocol is used for communication.

In the prior art, during backboard-punching process, a foundry works records FW information of a backboard offline. After the backboard is returned, in the debugging process of a hardware research and development engineer, if the situation of backboard FW updating and verification is met, a BMC online burning mode is adopted for burning. Therefore, at the beginning of hardware design, the BMC is required to reserve an I2C communication interface for the backplane for FW refresh. However, because the BMC management information is more and the I2C channel resource is limited, the problem of insufficient use of the I2C interface resource in the BMC is likely to occur. To expand the I2C channel, the I2C Switch chip PCA9546 is often used for I2C channel expansion and the I2cr edge chip PCA9617 to enhance signal driving during hardware design. This will undoubtedly increase the board hardware design cost.

Disclosure of Invention

The technology to be solved by the application is to provide a data updating method and device, which can reduce the use burden of an I2C channel in the BMC and save the use resources of a BMC interface.

In order to solve the above technical problem, the present application provides a data updating method, including:

after receiving a firmware FW updating instruction sent by a baseboard management controller BMC, a Complex Programmable Logic Device (CPLD) judges whether the FW information of a specified backboard needs to be updated according to identification information and FW information of the specified backboard carried in the specified FW updating instruction and current FW information of the specified backboard stored by the CPLD;

and if the FW information of the specified backboard needs to be updated, writing the FW information carried in the FW updating instruction into the specified backboard, and updating the current FW information of the specified backboard stored in the CPLD into the FW information carried in the FW updating instruction.

Optionally, before the CPLD receives a firmware FW update instruction sent by the BMC, the method further includes:

and the BMC writes initial FW information corresponding to one or more backplates into the CPLD.

Optionally, after receiving a firmware FW update instruction sent by the baseboard management controller BMC, the determining, by the complex programmable logic device CPLD, whether to update the FW information of the specified backplane according to the specified backplane information and the FW information carried in the FW update instruction includes:

comparing the FW information carried in the FW update instruction with the current FW information of the specified backplane stored in the CPLD, and if the version of the FW information carried in the FW update instruction is inconsistent with the version of the current FW information corresponding to the specified backplane stored in the CPLD, the FW information of the specified backplane needs to be updated.

Optionally, after receiving the firmware FW update instruction sent by the baseboard management controller BMC, the complex programmable logic device CPLD determining whether to update the FW information of the specified backplane according to the specified backplane information and the FW information carried in the FW update instruction further includes:

if the version of the FW information carried in the FW update instruction is consistent with the version of the current FW information corresponding to the specified backboard stored in the CPLD, the FW information of the specified backboard does not need to be updated.

Optionally, the writing the FW information carried in the FW update instruction into the specified backplane includes:

and the CPLD writes the FW information carried in the FW updating instruction into the specified backboard through controlling a two-wire serial bus I2C.

The present embodiment also provides a data update apparatus, including: a memory and a processor;

the memory is used for storing a program for updating data;

the processor is used for reading and executing the program for updating data and executing the following operations:

Optionally, the processor is configured to read and execute the program for updating data, and further perform the following operations:

before the CPLD receives a firmware FW updating instruction sent by the BMC, the BMC writes initial FW information corresponding to one or more backplates into the CPLD.

The application includes: after receiving a firmware FW updating instruction sent by a baseboard management controller BMC, a Complex Programmable Logic Device (CPLD) judges whether the FW information of a specified backboard needs to be updated according to identification information and FW information of the specified backboard carried in the specified FW updating instruction and current FW information of the specified backboard stored by the CPLD; and if the FW information of the specified backboard needs to be updated, writing the FW information carried in the FW updating instruction into the specified backboard, and updating the current FW information of the specified backboard stored in the CPLD into the FW information carried in the FW updating instruction. The technical scheme can reduce the using number of channels of the BMC chip I2C, and provides possibility for the BMC for other information management. Meanwhile, the use of an I2C Switch chip and an I2C driver chip is saved, and the hardware design cost is reduced.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a flow chart of a data updating method according to a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a data updating apparatus according to a first embodiment of the present invention;

fig. 3 is a flowchart of a data updating method according to an example one of the present application.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Example one

As shown in fig. 1, the data updating method of the present embodiment includes:

step S101, after receiving a firmware FW updating instruction sent by a BMC, a CPLD judges whether the FW information of a specified backboard needs to be updated according to identification information and FW information of the specified backboard carried in the specified FW updating instruction and current FW information of the specified backboard stored by the CPLD;

step S102, if the FW information of the specified backplane needs to be updated, writing the FW information carried in the FW update instruction into the specified backplane, and updating the current FW information of the specified backplane stored in the CPLD to the FW information carried in the FW update instruction.

Optionally, after receiving the FW update instruction sent by the BMC, the CPLD determining whether to update the FW information of the specified backplane according to the specified backplane information and the FW information carried in the FW update instruction includes:

Optionally, the writing the FW information carried in the FW update instruction into the specified backplane may include:

The technical scheme can reduce the using number of channels of the BMC chip I2C, and provides possibility for the BMC for other information management. Meanwhile, the use of an I2C Switch chip and an I2C driver chip is saved, and the hardware design cost is reduced.

As shown in fig. 2, the present embodiment also provides a data updating apparatus, including: a memory 10 and a processor 11;

the memory 10 is used for storing programs for data updating;

the processor 11 is configured to read and execute the program for updating data, and perform the following operations:

Optionally, the processor 11 is configured to read and execute the program for updating data, and further perform the following operations:

Example 1

The data update method of the present application is further described below.

As shown in fig. 3, the data updating method of the first example includes:

step S201, the BMC writes initial FW information corresponding to one or more backplates into the CPLD;

in the example, the CPLD replaces the BMC to realize the update function of the backboard FW information, so that the number of used channels of the BMC chip I2C is reduced. The CPLD chip can be arranged in the server mainboard and the server backboard, and a plurality of CPLDs can be arranged on the server, so that the function of updating the backboard FW information by which the CPLDs replace the BMC can be preset.

Assuming that two CPLDs, namely CPLD1 and CPLD2, are provided on the server, if CPLD1 is set to replace BMC to realize the update function of the backplane FW information, the initial FW information of the backplane needs to be stored in CPLD1 in advance. In general, a plurality of backplanes may be provided on the server, and therefore, initial FW information corresponding to each backplane needs to be stored in the CPLD 1. Initial FW information corresponding to the partial backplane can be stored in CPLD1, so that CPLD1 only realizes the FW information updating function for the partial backplane.

In this example, the FW update instruction carries identification information and FW information specifying the backplane. The designated backplane, that is, the backplane requiring updating of the FW information, the identification information of the designated backplane may include address information, and the CPLD may know which backplane requiring updating of the FW information is according to the address information after receiving the FW update instruction.

Step S202, receiving an FW updating instruction sent by the BMC by the CPLD;

step S203, the CPLD judges whether to update the FW information of the specified backboard; if the FW information of the specified backplane needs to be updated, executing step S204; if the FW information of the specified backplane does not need to be updated, step S206 is executed;

in this example, after receiving an FW update instruction sent by a BMC, a CPLD compares FW information carried in the update instruction with current FW information of the specified backplane stored in the CPLD, and if the version of the FW information carried in the update instruction is inconsistent with the version of the FW information corresponding to the specified backplane stored in the CPLD, the FW information of the specified backplane needs to be updated; if the version of the FW information carried in the update instruction is consistent with the version of the FW information corresponding to the specified backplane stored in the CPLD, the FW information of the specified backplane does not need to be updated. That is, updating of the FW information is required only when the version of the FW information of the backplane is upgraded.

Step S204, writing the FW information carried in the FW updating instruction into the specified backboard;

in this example, the CPLD serves as a master device side control I2C, and the CPLD writes the FW information carried in the FW update instruction into the specified backplane through a control I2C.

In this example, the CPLD writes the backplane FW information carried in the update instruction into the backplane of the server by controlling a register of the CPLD.

Step S205, updating the current FW information of the specified backboard stored by the CPLD into the FW information carried in the FW updating instruction; the FW information of the specified backboard is updated;

after FW information of the specified backplane is updated, FW information of the specified backplane stored by the CPLD needs to be updated accordingly, so that when FW information of the specified backplane is updated again next time, the CPLD compares the version of the FW information of the specified backplane currently stored with the version of the FW information carried in the FW update instruction. That is, the initial FW information of the backplane, which is initially stored in the CPLD, is updated accordingly.

Step S206, the CPLD waits for the next time the BMC sends the FW update command, and if the FW update command is received, the process goes to step S202.

The following further describes the process of writing data on the server backplane by the CPLD in this example:

in this example, the CPLD is used as a master device side control I2C to communicate with one or more backplanes used as slave devices, respectively. The I2C Master can be used as an IP soft core of the CPLD, and mainly communicates with a Slave (Slave) through a WISHBONE bus (interconnection is completed by establishing a general interface between IP cores). The I2C Master includes a plurality of registers, such as: command Register (CR), transmit register (TXR), receive register (RXR), control register (CTR), status register, etc. (SR).

The I2C Master module controls the I2C bus through the operation of each register, thereby realizing the read-write operation of the Slave device.

The method for the communication between the I2C Master and the backboard comprises the following steps:

step 1, setting a clock frequency by an I2C Master;

step 2, writing an instruction in the CXR, wherein the instruction is 8' h80, and enabling the I2C Master to work normally;

step 3, writing an instruction in the TXR, wherein the instruction format is I2C bus address + write data bit (write bit);

step 4, writing an instruction in the CR, wherein the instruction format is a command byte of 8' h90, which indicates that it is necessary to Write data in the TXR into the I2C bus (the data is: I2C bus address + Write bit);

step 5, checking SR, and confirming whether the instruction in CR in step S2034 has been executed;

step 6, writing the address of the Slave in the TXR, namely the writing address of the updating data;

in this step, the FW update instruction carries identification information for specifying the backplane, and the identification information may include address information of the backplane.

Step 7, writing an instruction in the CR, wherein the instruction format is 8' h10, so that an I2C communication start signal can be started;

step 8, checking SR, and confirming whether the instruction in CR in step S2037 has been executed;

step 9, writing the latest version of FW information in the TXR;

in this step, the FW information of the latest version may be written into the specified backplane in a manner of writing 8-bit (bit) data each time.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A method for updating data, the method comprising:

2. The data updating method of claim 1, wherein before the complex programmable logic device CPLD receives a firmware FW update instruction sent by the baseboard management controller BMC, the method further comprises:

3. The data updating method of claim 2, wherein after receiving a firmware FW update instruction sent by a baseboard management controller BMC, the complex programmable logic device CPLD determining whether the FW information of the specified backplane needs to be updated according to specified backplane information and FW information carried in the FW update instruction comprises:

4. The data updating method of claim 3, wherein after receiving a firmware FW update instruction sent by a baseboard management controller BMC, the complex programmable logic device CPLD determining whether the FW information of the specified backplane needs to be updated according to specified backplane information and FW information carried in the FW update instruction further comprises:

5. The data updating method according to claim 3, wherein the writing the FW information carried in the FW update instruction to the specified backplane comprises:

6. A data update apparatus, the apparatus comprising: a memory and a processor; the method is characterized in that:

the memory is used for storing a program for updating data;

7. The data updating apparatus of claim 6, wherein the processor, configured to read and execute the program for data updating, further performs the following operations:

8. The data updating apparatus according to claim 7, wherein after receiving a firmware FW update command sent by the BMC, the complex programmable logic device CPLD determining whether to update the FW information of the specified backplane according to specified backplane information and FW information carried in the FW update command includes:

9. The data updating apparatus of claim 8, wherein after receiving a firmware FW update command sent by the BMC, the complex programmable logic device CPLD determining whether to update the FW information of the specified backplane according to specified backplane information and FW information carried in the FW update command further comprises:

10. The data updating apparatus according to claim 8, wherein the writing the FW information carried in the FW update instruction to the specified backplane comprises: