CN1106152A

CN1106152A - Apparatus for processing information

Info

Publication number: CN1106152A
Application number: CN 94101209
Authority: CN
Inventors: 奥野木丰
Original assignee: Sega Enterprises Ltd
Current assignee: Sega Corp
Priority date: 1994-01-29
Filing date: 1994-01-29
Publication date: 1995-08-02
Anticipated expiration: 2014-01-29
Also published as: CN1099081C

Abstract

The information processing unit comprises operation unit, storage unit attachable to said operation unit, circuit for sharing data processing task, unit forprocessing the data stored in storage unit. Said operation unit and storage unit share the decoding function of compressed coded data.

Description

Apparatus for processing information

The present invention relates to a kind of signal conditioning package, particularly have calculus treatment device, and can insert with this calculus treatment device and take off the external memory that is connected, and then be about having the signal conditioning package of the structure that can share data processing function.

Utilize calculus treatment device and can insert with this calculus treatment device and take off the signal conditioning package that external memory constituted that is connected, carry out the system of the formula that is stored in external memory, existing various motions by calculus treatment device.

As one of this kind information processing apparatus system example, the game device that for example uses a computer is arranged.The formation of this kind game device is, will in keep the external memory of the storage medium of ROM cartridge, ROM card, CD-ROM, disk (FD) etc., can insert the game device main body that keeps computing machine (CPU) in being connected in with taking off.

And, read the data that are stored in external memory, and calculation is handled in the game device main body, and appearance is shown in the display device of kinescope (CRT) or liquid crystal etc. within the formula of will playing, and plays.

In this, external memory is restricted to the memory capacity that is subjected to the storage medium qualification because of reasons such as the Package size of cartridge, specification, prices.Therefore, in order lot of data to be stored in the limited storage medium, adopt the data compression method of being stored after the digital codingization at present.

Therefore,, and, numeralization and compressed data decode should be handled, be reduced to original data for the CPU that can utilize agent set carries out formula calculation processing from the external memory sense data.

The method that this data decode is handled has: utilize the method for Cheng Zhihang, or the method for utilizing special-purpose decoding to carry out with semi-conductor chip.

When utilizing formula to carry out decoding processing, do not need special hardware.And the bigger advantage of degree of freedom for the numeralization method of packed data is arranged.Yet, have but that decoding speed is slow, the shortcoming of the processing of the CPU that takies agent set.

In addition, when utilizing the dedicated semiconductor chip of decoding usefulness to carry out decoding processing, decoding speed is fast, so it is less to take the shortcoming of CPU of agent set.When particularly decoding image data, because of handling complexity, and require high speed processing, so utilize the processing of special use to carry out more favourable with semi-conductor chip.

This occasion of prior art, the decoding processing semi-conductor chip of above-mentioned special use, because of not cheap, should sharing so take off outside the exchange data set for can inserting of plural number, and generally only place calculation to handle the apparatus main body of using.

In addition, ROM cartridge, ROM card, storage mediums such as CD-ROM, FD if duplicate the formula of storage data, are then made duplicate easily.Therefore, be replicated without approval, more need possess the process chip of maintaining secrecy and using in order to prevent formula.

Possess the prior art of this secret process chip of using, have: the spy opens clear 61-296, the spy opens the United States Patent (USP) 4,799,635,4,865,321,5,070,479 of clear 62-3331, correspondence, and is recorded in R34,161 technology.

Whether in this technology, the process chip of using except that maintaining secrecy is installed in the agent set, also is installed in external device (ED), consistent according to the result of the secret process chip of using of both sides, judges the true or false of the external memory that is connected.

Yet the process chip of this secret usefulness is also the same with the dedicated semiconductor chip that decoding is used, and all is that price is comparatively expensive, and has improved the price of external memory.

Therefore, the object of the present invention is to provide a kind of signal conditioning package, it has calculus treatment device, and can insert with this calculus treatment device and take off the external memory that is connected, and can reduce cost and have the stores processor function.

Another object of the present invention is to provide a kind of signal conditioning package, it has and can share the structure of the decodingization function of compression storage at calculus treatment device and external memory.

Another object of the present invention is to provide a kind of signal conditioning package, and it need not be provided with specific process chip, and can judge the true or false of external memory.

Another object of the present invention is to provide a kind of signal conditioning package, and it has the external memory of calculus treatment device and storage data; This calculus treatment device can be inserted to take off freely with external memory and be connected, and has more the data processing equipment that can handle the data that are stored in this external memory; This data processing equipment has: be located at the 1st treating apparatus of said external memory storage, and be located at the 2nd treating apparatus of aforementioned calculus treatment device, for the processing of aforementioned data, can share execution by the 1st treating apparatus and the 2nd treating apparatus.

Another object of the present invention be to provide a kind of can be corresponding to the external memory of above-mentioned purpose.

Another object of the present invention is to provide a kind of external memory, has: storage medium; And treating apparatus is stored at least a portion of processing capacity of the data of this storage medium, can be carried out by this treating apparatus, and can insert freely and take off in calculus treatment device, and this calculus treatment device has the result's that can be taken into the processing aforementioned data CPU.

Content of recording and narrating by the application's claim and following embodiment explanation for the present invention's further purpose, can be that this is clear.

Accompanying drawing aims at the present invention's explanation and prepares, and the present invention is not limited to drawing record person.

Fig. 1 is the calcspar of the present invention the 1st embodiment;

Fig. 2 is an example of the execution length coding of the embodiment of the invention;

Fig. 3 is an example of embodiment of the invention Huffman encoding;

Fig. 4 is the key diagrams of the execution data of the embodiment of the invention with the He Man decoding table;

Fig. 5 is the key diagram of the execution length of the embodiment of the invention with the Huffman encoding table;

Fig. 6 to Figure 14 is the circuit diagram of detailed formation of calcspar of representing to cut apart the 1st embodiment of Fig. 1 respectively;

Figure 15 is each configuration relation key diagram of Fig. 6 to Figure 14;

Figure 16 to Figure 19 is the action time figure of the 1st embodiment;

Figure 20 is the adjunct circuit figure that does not carry out decoding and promptly directly read the ROM data;

Figure 21 is the calcspar of the present invention the 2nd embodiment.

Fig. 1 is the calcspar of the present invention the 1st embodiment; Expression the present invention's the calculus treatment device 201 and the component part of external memory device 202, and annexation between the two.

Calculus treatment device 201 and external memory 202 are to utilize not shown special terminal to insert and take off freely to connect.

In calculus treatment device 201, on bus BS, except that CPU1, still connect various I/O and calculation function circuit.

Can be understood that by following explanation embodiments of the invention have the function of data processing, this data processing is the packed data of reading among the ROM2 that is stored in external memory 202, and decoding processing becomes original data, and delivers to CPU1.

Therefore, for the purpose of simplifying the description, in Fig. 1, only shown on the bus BS of calculus treatment device 201 sides, be connected at the structure of the demoder of calculus treatment device 201 sides.

Be located at the demoder of calculus treatment device 201 sides, divide, have: main body control portion 3 with the function square; Carry out length counter 4; And, carry out data register 5.

In addition, inserting and take off the external memory 202 that is connected in calculus treatment device 201 freely, is the cartridge of for example playing.

Be provided with the ROM2 that stores recreation formula data in this recreation cartridge, particularly, in the present invention's embodiment, store compressed data.

Therefore, the packed data of reading from ROM2 should be decoded into original data.This decoding is the demoder that utilizes aforementioned calculus treatment device 201 sides, and the demoder of external memory 202 sides is shared the execution function.

Therefore, in the present invention,, sharing and carrying out the function that particular data is handled in calculus treatment device 201 sides and external memory 202 sides.

By this, can overcome the shortcoming of the prior art of initial explanation.That is the occupying and the problem of the cost of external memory of CPU.

In the embodiment in figure 1, the demoder of external memory 202 sides includes: ROM address counter 6; Shift register 7; ROM read-out control part 8; Shift register control part 8; Shift register control part 9; And Huffman (Huffman) decoding table 10.

In this, in order to understand following explanation, one of the packed data example that just is stored in the ROM2 of embodiment is illustrated.

As embodiment, data in the packed data of ROM2 are, earlier binary numerical data are carried out length coding (Run Length Coding), will carry out then the length coded data in addition Huffman encoding obtain.

Fig. 2 is the key diagram that specifies this coding.That is as shown in the figure, be that the binary digital data of 56 bits is that example is studied, with former data.

This binary digital data is to be one group with per 4 bits, represents the size of 16 numerical value respectively.Therefore, Fig. 2 relies the binary digital data of 6 bits, as if being one group with per 4 bits, then represents with EEEEE999993311 by 16 scale codings.

After again this symbol being imposed the execution length coding, will carry out data and impose Huffman encoding.The feature of Huffman encoding is the occurrence frequency according to coding, and makes coding bit number difference.

Fig. 3 is one of this Huffman encoding example, and the raw data 0-F of 16 systems corresponds respectively to and carries out the Huffman encoding that data are used and execution length is used.

Example in the data E5953212 that imposes after carrying out length coding shown in Figure 2, is for example carried out data E and is the Huffman encoding corresponding to 11111110.Moreover execution length 4 is the Huffman encodings corresponding to 1010.

By relation in this way, the above-mentioned data E5953212 that carries out behind the length coding that imposes behind Huffman encoding, promptly becomes: 11111110|1010|11110|1010|11000|01|01|01

Therefore, can understand, the binary data of 56 bits originally can be compressed into the binary data of 32 bits.This compressed binary data storage is in the ROM2 of external memory shown in Figure 1 202.

Fig. 6 to Figure 14 is the physical circuit figure of the 1st embodiment structure shown in the contingency table diagrammatic sketch 1, and this embodiment is in order to should compressed storage data being read by ROM2, and is decoded into original binary data, and delivers to CPU1.

Figure 15 is the configuration relation key diagram of the Fig. 6 to Figure 14 after cutting apart.In Figure 15, the left side that utilizes the imaginary line incision is a part of being located at calculus treatment device 201; The right side is a part of being located at external memory 202.

And then Figure 16 to Figure 19 is the embodiment action time figure of Fig. 1 and Fig. 6 to Figure 14.

In the embodiment action time figure shown in Figure 16 to Figure 19 figure, Figure 16 and Figure 17 mainly are the action time figures that working storage is set the stage of reading corresponding to ROM2.

And then Figure 18 and Figure 19 be the action time figure that corresponds respectively to Figure 16 and Figure 17, and constantly proceed, and mainly is the action time figure in the stage of reading of decoded data.

Below, with reference to these action time figures, the circuit operation of key diagram 1 and Fig. 6 to Figure 14.

Get back to Fig. 1 explanation, through cpu address bus 11 cpu address signal CPUA is conducted to main body control portion 3 by CPU1.

Main body control portion 3, wherein a part is configured among the figure and shows.In Fig. 6, the 60th, have the NAND lock circuit of 8 input ends.With the cpu address signal CPUA(23 on the cpu address bus 11 ... 0) (annotate: the numeral signal bit number in (), in this example, the signal bit number of expression 23-0, in following explanation also together.), and/AS is conducted to this NAND lock circuit 60 with/DS signal (with reference to Figure 16).

Can detect the field of storage address 800000-83FFFF of ROM2 by access by this NAND lock circuit 60.NAND lock circuit 60 detect output, be sent to

NAND lock circuit

61,62,63 and 64 again.

When write/read output signal R/W is during at starting state, because of phase inverter 68 is arranged, thus corresponding to the state of 0 bit of cpu address signal CPUA, by NAND lock circuit 61,62 respectively output/LWR ,/the UWR signal.

/ LWR reaches/the UWR signal, imports ROM address counter 6(respectively with reference to Fig. 1).ROM address counter 6 is to be made of two up-down counters 121 and 123 ,/LWR and/the UWR signal transports to the input terminal (LON) (with reference to Figure 12) of counter 121 and 123 respectively.

In addition, via cpu data bus 12(with reference to Fig. 1), transport to the counter 121 and 123 that constitutes ROM address counter 6 with reading start address.

This reads start address, is that the address is upper and start address is the next to start with, and per 8 bits are sent, by/UWR and/LWR, sequentially make upper 8 bits be loaded to counter 123 and the next 8 bits are loaded to counter 121(with reference to Figure 16).

Therefore, by counter 121 and the 123 ROM address ROMA(15 that export as the counter initial value ... 0) to ROM address bus 13.

This ROM address ROMA(15 ... 0) input selector 122 again when non-starting state, is selected and is selected signal (/DIRECT), and deliver to ROM2(with reference to Figure 12).

In addition, ROM read-out control part 8(is with reference to Fig. 1), be by two sections D-FF(flip-flop) 90,91(is with reference to Fig. 9) and NOR lock circuit 120(with reference to Figure 12) constitute.

At two sections D-FF(flip-flop) 90,91 input/LWR and output-/SLDU is to shift register 7, should/SLDU is the load control signal (with reference to Figure 17) that only once goes up bit data at first.

The NOR lock circuit 120(of the part of formation ROM read-out control part 8 is with reference to Figure 12), also import in one input end/SLDU.

Again, at the other end of NOR lock circuit 120, input one/SLDU, should/SLDU, be signal (with reference to Figure 12, Figure 17) to bit data under the shift register 7 loads control.

Therefore, in each timing of two signals, by NOR lock circuit 120 outputs one address stairstep signal/INCA.ROM address counter 6 next stepping whenever, that is the address date on the ROM address bus 13 can every next stepping.

In this, as shown in figure 14, shift register 7 is by bit shift register 140 under the TTL logic, and top offset bit register 141 constitutes.

As previously mentioned, only when ROM address counter 6 is set start addresss, just bottom offset bit register 140 and top offset register are set the ROM data, these ROM data are basis/SLDU and transported to the data of ROM data bus 14 by ROM2.(with reference to Figure 17).

Only bottom offset bit register 140 set ROM data, and data successively by bottom offset bit register 140 move to top offset bit register 141 thereafter.

Shift register

140 and 141 displacement control be by, constitute aftermentioned shift register control part 9 a part NOR lock circuit 101 export it/SREQU(is with reference to Fig. 1, Figure 13), reach by NAND lock circuit 142 export it/SREQU(is with reference to Figure 14) carry out.

Shift register 7, be the output ROM data of top offset bit register 141 in specific words, be imported into Huffman decoding table 10(with reference to Fig. 1, Figure 10), and become address with respect to Huffman decoding table 10.

The output ROM data of shift register 7 are Huffman encodings, in this relation of these data and its decoding output are described.

In Fig. 3, as previously mentioned, carry out the length coded data, give Huffman encoding to carrying out data and carrying out length respectively.

Therefore, should Huffman encoding be imposed decoding table respectively at the execution data and the execution length of correspondence.Therefore, Huffman decoding table 10 has: carry out the Huffman decoding table 116 that data are used; And the Huffman decoding table 114(that execution length is used is with reference to Figure 11).

This Huffman decoding table 116,114 is made of a kind of memory circuit.Therefore, utilize various means, for example ROM makes its commonization, or utilizes RAM to make it become variable to each external memory.

Fig. 4 is a key diagram of carrying out the Huffman decoding table 116 that data use.Being the address from shift register 141 resulting 8 bit Huffman encoding HUF7-0, and 4 bit decoded datas (DATA3-0) of the address of output storage correspondence, the Huffman encoding length (code length-1) that reaches 3 bits (SLEN3-0).

In the same manner, Fig. 5 is a key diagram of carrying out the Huffman decoding table 114 that length uses.Being the address from shift register 141 resulting 8 bit Huffman encoding HUF7-0, and 4 bit decoded datas (DATA3-0) of the address of output storage correspondence, and the Huffman encoding length of 3 bits (coding length-1) is (CLEN3-0).

In Figure 11, by Huffman decoding table 116 and 114 outputs and respectively be respectively the execution data Huffman encoding length of 3 bits, and execution length Huffman encoding length, be input into multiplexer 113.

Similarly, respectively being respectively the decoded data used of the execution data of 4 bits and carrying out the decoded data that length uses and be imported into multiplexer 115 from Huffman decoding table 116 and 114.

At the SEL of

multiplexer

113 and 115 terminal.Input by T-FF100(with reference to Figure 10) RD/RL(of output is with reference to Figure 17, Figure 19).

Therefore, multiplexer 113 is according to the logic level of RD/RL, and the Huffman encoding length that Huffman decoding table 114 that length uses is exported is carried out in mutual output, or carries out the Huffman encoding length that data are exported with Huffman decoding table 116.

In the same manner, multiplexer 115 is according to the logic level of RD/RL, and the execution data that Huffman decoding table 114 that length uses is exported are carried out in mutual output, or carries out the Huffman decoding table 116 that data use and export the execution data.

So, by

use multiplexer

113 and 115, and utilize the bus of 4 bits to connect and to finish.Certainly, also can not use multiplexer, and utilize the structure of the bus output of 8 bits.

Huffman encoding length by multiplexer 113 output is imported into counter 111, and this counter 111 is to constitute shift register control part 9(with reference to Fig. 1) a part.Counter 111 only descends when input Huffman encoding length, and when reducing to 0, output/HLD(is with reference to Figure 17).

As previously mentioned ,/HLD becomes RD/RL via T-FF100, and the selection terminal SEL of

input multiplexer

113 and 115, and the output of switching controls Huffman encoding table 114 and 116 (with reference to Figure 10, Figure 11).

Via the NOR lock circuit 110 of Figure 11, just new Huffman encoding length/HLD can be input to the LDN terminal of counter 111.

Again ,/HLD signal input NOR lock circuit 101(is with reference to Figure 10), and become for B counter 130(with reference to Figure 13) displacement require signal/SREQL.

This displacement requires signal/SREQL, except that/HLD, when/INCA or/during RREQ input NOR lock circuit 101, all can produce (with reference to Figure 10).

/ INCA is the output (with reference to Figure 12) of NAND lock circuit 120.Again ,/RREQ is with reference to Fig. 8 by execution length counter 80(described later) introduce.

B counter 130, displacement require the starting of signal/SREQL during, counting descend (with reference to the BCOUNT of Figure 17 and Figure 19).

When the count value of B counter 130 is 0, exports SLDL, and use shift register 140(with reference to Figure 14 at bit data bus under the formation shift register 7), be taken into the ROM data of sending here by ROM data bus 14 again.

Get back to Fig. 1,, transport to and carry out length counter 4 by Huffman decoding table 10 output and through executive chairman's degrees of data of Huffman decoding; And carry out data and transport to execution data register 5.

Input to executive chairman's degrees of data of carrying out length counter 4,, subtract till the calculation to 0 in regular turn according to calculating instruction by subtracting of main body control portion 3 outputs.

In addition, input to the execution data of carrying out data register 5, before execution length counter 4 becomes 0, export cpu data bus 12 repeatedly to.By this, data and continuation number of times thereof can utilize CPU1 to control, can be decoded so carry out length coding.

Illustrate further to realizing the physical circuit of this function, the multiplexer 115 of Figure 11 is the parts that constitute Huffman decoding table 10, and mutual output is by the decoded data of aforementioned Huffman decoding table 114 and 116 outputs.

Carry out length counter 4 and be counter 80(by the TTL circuit with reference to Fig. 8), and NAND lock circuit 81 constitutes.

Decoded data by the output of Huffman decoding table 114, carry out the length data because be, so can import this counter 80, and be set, the execution length of transporting to counter 80 is with reference to Fig. 7 at NOR lock circuit 76(with the setting of data) output/RLLD (with reference to Figure 17, Figure 19) of carrying out when transporting to the LDN end of counter 80.

In addition, by the execution data of the decoded data of Huffman decoding table 116 output, transport to constitute carry out data register dualization D-FF84(with reference to Fig. 8).

The data of being set by dualization D-FF84, respectively by D-FF96,97(with reference to Fig. 9 figure) output /UCKH and/time of LCKL in, be set at each the next 4 bit, upper 4 bits (with reference to Fig. 8) by D-FF82,82.

Set by both sides' D-FF 82,83 if carry out data, promptly via cpu data bus input CPU1.

Counter 80 /UCKH and/during the non-starting state of LCKL,, and the executive chairman's number of degrees that set are subtracted calculations (RUN with reference to Figure 17, Figure 19 counts) by clock CLK by NAND lock circuit 81 inputs one/DECR.

Subtract and proceed, when setting value becomes 0, generation/RREQ signal, and carry out the data read requirement of next time.This data read requires to be imported into aforementioned NOR lock circuit 101(with reference to Figure 10), to counter 130 be shifted control (/AREQL).

Therefore, before the data read of carrying out next time requires, that is carry out subtracting of executive chairman's number of degrees that counter 80 is set be counted as be 0 before, identical execution data export cpu data bus 12 to by D-FF_82 and 83.

As mentioned above, in the present invention the 1st embodiment, will be stored among the ROM2 of external memory 202 by the packed data of carrying out length numeralization and Huffman encodingization.

And, the decoding processing function when reading the data that are stored in ROM2, can by: be located at the Huffman sign indicating number that the Huffman decoding table 10 of external memory 202 is produced; And, be located at the execution length counter 4 of calculus treatment device 201 and carry out the execution length decoder that data register 5 is produced, share function.

By this, can prevent: only have the processing capacity of decodingization in external memory 202, the cost of caused external memory 202 rises.

And then, even the packed data that is stored in ROM2 during by illegal duplicating, only has the data of duplicating also can not be reduced to original data, because of the still need map table of Huffman decoding table 10 of reduction.

Therefore, embodiments of the invention also can prevent that the formula data from being duplicated by illegal.

Moreover, about above-mentioned the 1st embodiment, though be to use ROM2 to be illustrated as the storage medium of external memory 202, the present invention is not limited to this, storage medium also can use: flash of light memory bank (Flash Memory) or have the RAM of reserve battery equipment.

Figure 20 is at the additional circuit diagram that has when appending function of the present invention's the 1st embodiment.That is, ROM2 except that store in advance encoded and the compression data, also can store not compressed data.

Therefore, Figure 20 directly reads the circuit of latter's data by CPU1.

Circuit shown in Figure 20 corresponding to storing the not field, address of the ROM2 of packed data, has NANHD lock circuit 201, and this NAND lock circuit 201 is the time of utilizing address strobe AS, detects the upper bit (A16-23) of address signal.

201 outputs of NAND lock circuit become/DIRECT, when consistent with the timing of the R/W that imports through phase inverter 203, through the output of NANHD lock circuit 202, make tri-state buffer circuit 204 attached gesture.

At this moment, the address signal CPU(15 of input NAND lock circuit 201 ... 0), also is input into selector switch 122() with reference to Figure 12.And selector switch 122 selects to switch address signal CPU(15 by/DIRECT ... 0), ROM2 can be started.

By this, tri-state buffer circuit 204 can be taken into ROM data (7 by ROM2 ... 0).

Secondly, through the cpu data bus 12 of Fig. 8, and unpressed ROM data without decoding device, can directly be imported CPU1.

Figure 21 is the calcspar that the present invention the 2nd embodiment constitutes.Particularly, the feature of this 2nd embodiment is the storage medium that has CD-ROM in external memory 202.

That is its structure is to have calculus treatment device main body 201, and the CD cartridge 202 of external memory.CD cartridge 202 has: CD-ROM217, and it is the medium in order to the encoded data described in storage as the 1st embodiment; And, demoder 216, it is equipped with in order to the decoding table of decode stored in the coded data of CD-ROM217.

Store encoded animation, voice data in CD-ROM217MPEG.Demoder 216 is connected with calculus treatment device main body 210 through CD cartridge connecting connector 214.

Be provided with CD driver 213 in calculus treatment device main body 201 in order to the data that read CD-ROM217.

Between CD driver 213 and the CD-ROM217, utilize laser 215 to connect.That is CD driver 213 is to utilize on the laser 215 scanning CD-ROM217, and reads the data of being stored.

Again, CD driver 213 is connected in CD recording controller 212 with the data that read, and this CD recording controller 212 is in order to carry out the error correction of CD-ROM specification.

CD recording controller 212 is connected in main body side demoder 211, and this main body side demoder 211 is equipped with the CD cartridge decoding control section corresponding to plural number.

Main body side demoder 211 connects with connector 214 through the CD cartridge, with the 216 one-tenth electrical connections of cartridge side demoder in the CD cartridge 202.

Main body side demoder 211 is more through bus 210, and the CPU1 all with the control calculus treatment device is connected.

Bus 210 also is connected with the various devices of calculus treatment device necessity, as: main storage means, I/O etc., because of not having direct connection, so in Figure 21, omit with the present invention.

Secondly, the decoding processing action of this embodiment device is described.

At first, CPU1 sends the commencing signal that reads the data on the CD-ROM217 to CD driver 213.CD driver 213 promptly reads the data on the CD-ROM217, and this number is delivered to CD recording controller 212.

212 pairs of data that obtain of CD recording controller see through the CD cartridge and connect with connector 214, with reference to the decoding table of cartridge side demoder 216, to decode.

The content of this decoding table, though have differently according to Methods for Coding, the decoding table 10 with the 1st embodiment of original explanation is identical basically.

Main body side demoder 211 is delivered to CPU1 through data bus 210 with decoded data after data decode is finished.

Therefore, identical with the 1st embodiment of Fig. 1, as if considering that to carrying out the decoding of length coding then basically, main body side demoder 211 is by carrying out length counter, reaching the execution data register and constitute.

It more than is the decoding processing action of the 2nd embodiment.

So, according to present embodiment, with the 1st embodiment in the same manner, carry out the decoding processing of data because of utilizing hardware, so do not occupy the processing of CPU, be able to high-speed decoding.

Again,,, can not duplicate, and can prevent that the illegal of software from duplicating if only be to duplicate CD-ROM217 by the cartridge side demoder 216 that should prepare difference to various cartridges.

Again, relevant demoder, will with the data independence that is recorded in CD-ROM217, and common part is located at main body side demoder 211; Different part then is located at cartridge side sign indicating number device 216 and map table etc. are with each CD-ROM, by this, can dwindle the size of the demoder that is equipped on each cartridge, and can reduce cost.

In above-mentioned the 2nd embodiment,, do not get rid of and to use: the data compression method of JPEG, Huffman encoding method, arithmetic coding method, general-purpose compiling method etc. though be to use MPEG in digital coding again.

And then, in the above-described embodiments, be equipped on though the function of demoder cut apart: calculus treatment device main body 201, and as the recreation cartridge or the CD cartridge 202 of external memory, but also want divisible demoder, only be equipped on: recreation cartridge or CD cartridge 202.

In this kind occasion,, can have the higher function of duplicating of preventing though the price of recreation cartridge or CD cartridge 202 can rise.

Again, in above-mentioned the 2nd embodiment, though should prepare the cartridge side demoder of difference with various CD cartridges, also can be common in the CD of plural number cartridge.

And then, in the above-described embodiments,, also can use LD-ROM, MO, FD etc. though storage medium is to use CD-ROM.

A kind of signal conditioning package is provided with calculus treatment device, and can insert with this calculus treatment device and take off the external memory that is connected, and has the data processing function that can reduce cost.

A kind of signal conditioning package further is provided, and one of its data processing example is by calculus treatment device; And external memory constitutes, and shares the decoding function of packed data.

Again, in the present invention's signal conditioning package, specific process chip need not be set, can judge the true and false of external memory.

Therefore,, can reduce the cost of signal conditioning package, and can prevent that illegal data from duplicating, and industry is had contribution greatly according to the present invention.

Moreover though according to the foregoing description explanation the present invention, the present invention produces and is not limited to this embodiment.Particularly, aspect data processing, though be the encoding compression data that are stored in external memory with decoding processing, be illustrated as embodiment, the present invention is not limited to the data processing of this decoding processing.

Modification in the scope of the present invention's technical conceive all should be contained in protection scope of the present invention.

Claims

1, a kind of signal conditioning package comprises:

The external memory (202) of calculus treatment device (201) and storage data, this calculus treatment device (201) are to insert to take off freely to be connected with external memory (202);

Data processing equipment can be handled the data that are stored in this external memory (202);

It is characterized in that:

This data processing equipment comprises: the 1st treating apparatus of being located at this external memory (202); Reach, be located at the 2nd treating apparatus of this calculus treatment device (201),

Share the processing of execution by the 1st treating apparatus and the 2nd treating apparatus to these data.

2, signal conditioning package as claimed in claim 1; It is characterized in that the data that are stored in this external memory (202) are to utilize coding and compression bit number.

3, signal conditioning package as claimed in claim 1; It is characterized in that the data that are stored in this external memory (202) are binary digit symbols, are subjected to the execution length coding at least.

4, signal conditioning package as claimed in claim 1; It is characterized in that the data that are stored in this external memory (202) are that the binary digit symbol is imposed the execution length coding, and then impose again that Huffman encoding forms.

5, signal conditioning package as claimed in claim 4; It is characterized in that the 1st treating apparatus is to carry out with respect to the Huffman decoding of this Huffman encoding to handle; The 2nd treating apparatus is the execution length decoding processing of carrying out with respect to this execution length coding.

6, signal conditioning package as claimed in claim 4; It is characterized in that the 1st treating apparatus has Huffman decoding table (10), and be the address, and output is carried out data and executive chairman's degrees of data with respect to the Huffman decoding of these data with the data of described storage;

The 2nd treating apparatus has: carry out length counter (4), and carry out data register (5); This carries out the length counting according to device (4), and input is by the Huffman decoding executive chairman degrees of data of this Huffman decoding table (10) output; And this executive chairman's degrees of data register (5), export this Huffman decoding and carry out data, and should carry out the length counting according to device (4) with this executive chairman's degrees of data subtrahend singly, till counting down to 0 when in, continue this Huffman decoding of output and carry out data.

7, signal conditioning package as claimed in claim 2 is characterized in that, this external memory (202) has storage medium, and this storage medium stores the compressed data by aforementioned coding at least.

8, signal conditioning package as claimed in claim 7 is characterized in that, this storage medium is the ROM(ROM (read-only memory)).

9, signal conditioning package as claimed in claim 2, it is characterized in that, this is stored in the data of external memory (202), more includes not impose coded data, and this does not impose the process object that coded data does not become the 1st treating apparatus and the 2nd treating apparatus.

10, a kind of external memory is characterized in that, comprising:

Storage medium (2); And,

Treating apparatus can be carried out at least a portion of the processing capacity of the data that are stored in this storage medium (2),

And can insert freely and take off in calculus treatment device (201), this calculus treatment device has the CPU(1 of the result that can be taken into these data).

11, external memory as claimed in claim 10 is characterized in that, the data that are stored in aforementioned storage medium (2) are data of encoded compression, and the aforementioned processing device has the function of execution corresponding at least a portion of the decoding processing of this coding.

12, external memory as claimed in claim 11 is characterized in that, the data that are stored in aforementioned storage medium (2) impose the execution length coding with the binary digit symbol and form.

13, external memory as claimed in claim 11; It is characterized in that the data that are stored in aforementioned storage medium (2) are that the binary digit symbol is imposed the execution length coding, and then impose again that Huffman encoding forms.

14, external memory as claimed in claim 13; It is characterized in that this treating apparatus has the Huffman decoding function of corresponding aforementioned Huffman encoding at least.

15, external memory as claimed in claim 14; It is characterized in that this treating apparatus has more Huffman decoding table (10), and be the address, and output is carried out data and executive chairman's degrees of data with respect to the Huffman decoding of these data with the data that are stored in aforementioned storage medium (2).

16, a kind of signal conditioning package has: calculus treatment device (201); And,

External memory (202) comprises the storage medium (2) of the data that storage is compressed by coding,

This calculus treatment device (201) with external memory (202), is inserted and is taken off connection freely,

It is characterized in that this calculus treatment device (201) has more:

CPU(1), with representing the geocoding in the field, address that this packed data is stored, export cpu address bus 12 to;

Main body control portion (3) detects by this CPU(1) geocoding sent here;

Carry out length counter (4); And

This external memory (202) has:

ROM address counter (6) when this main body control portion (3) detects this geocoding, is set the initial stage address coding site corresponding to the field, address of this packed data of storing this storage medium (2);

Shift register (7), this packed data that setting is read from the address location of this storage medium (2), and the address location of storage medium (2) is the geocoding that sets corresponding to this ROM address counter (6), and with the output that is shifted in regular turn of this packed data;

ROM read-out control part (8), next stepping control this ROM address counter (6) set at the beginning of phase geocoding position;

Shift register control part (9) is controlled the shift motion of this shift register (7); And,

Decoding table with the address that is output as of this shift register (7), is exported execution length and execution data corresponding to this address,

By the control of main body control portion (3), will be set in this execution length counter (4), and should carry out data by the execution length of this decoding table (10) output, be set in this execution data register (5);

When this execution length counter (4) was till whenever next subtracts the execution length to 0 that is set, this carried out storage register (5), and these execution data that are set are delivered to CPU(1).

17, signal conditioning package as claimed in claim 16 is characterized in that, this compression storage is to utilize 16 system symbols of each 2 bit expression of binary digit symbol, to impose the execution length coding, imposes that Huffman encoding forms again.

18, signal conditioning package as claimed in claim 17 is characterized in that, this decoding table (10) is the Huffman decoding table, and exportable Huffman encoding corresponding to aforementioned Huffman encoding is carried out data and executive chairman's degrees of data.

19, signal conditioning package as claimed in claim 18 is characterized in that, this Huffman decoding table has: carry out the Huffman decoding table (114) that length is used; And, carry out the Huffman decoding table (116) that data are used,

The Huffman encoding length that the exportable execution length of Huffman decoding table (114) that this execution length is used is used, and carry out the decoded data that length is used,

The Huffman encoding length that the exportable execution length of Huffman decoding table (116) that this execution length is used is used, and carry out the decoded data that length is used.

20, signal conditioning package as claimed in claim 19 is characterized in that, has more: the 1st multiplexer (113), and the 2nd multiplexer (115),

The 1st multiplexer (113) can be exported the Huffman encoding length that this execution length is used alternately, and carries out the Huffman encoding length that data are used;

The 2nd multiplexer (115) can be exported the decoded data that this execution length is used alternately, and carries out the decoded data that data are used.

21, a kind of signal conditioning package comprises:

Calculus treatment device (201) and external memory (202);

This calculus treatment device (201) is to insert to take off freely to be connected with reaching external memory (202); And then,

This external memory (202) has:

CD-ROM(217), store the data of mat encoding compression;

Cartridge side demoder (216) stores the decoding table corresponding to the coding of these data;

This calculus treatment device (201) has:

CD driver (213) is stored in this CD-ROM(217 in order to read) data;

CD controller (212) carries out the data that read the error correction of CD-ROM specification; And,

Agent set side demoder (211) imposes data after the error correction with this CD controller (212), with the decoding table of this cartridge side demoder (216) with reference to relatively, and decode.

22, signal conditioning package as claimed in claim 21; It is characterized in that this cartridge side demoder (216) and this agent set side demoder (211) utilize connector (214) to insert and take off freely to connect; And this CD-ROM(217) utilize laser to be connected with CD driver (215).