CN110611536A - Optical network unit, optical communication method, and computer-readable medium - Google Patents
Optical network unit, optical communication method, and computer-readable medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/697—Arrangements for reducing noise and distortion
- H04B10/6971—Arrangements for reducing noise and distortion using equalisation
Abstract
Embodiments of the present disclosure provide an ONU, an optical communication method, and a computer-readable medium. The ONU described herein comprises an adjuster configured to adjust, based on the equalized first digital signal, a second analog signal received from the optical line terminal after the first analog signal to obtain an adjusted second analog signal. The second analog signal is superimposed with the first analog signal, and the equalized first digital signal is generated based on the first analog signal. The ONU further comprises a digital signal decider configured to decide the adjusted second analog signal as a single-bit digital signal. The ONU further comprises an equalizer configured to equalize the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal. The ONU also includes a memory configured to store the equalized first digital signal and the equalized second digital signal.
Description
Technical Field
Embodiments of the present disclosure relate generally to communication technology and, more particularly, relate to an optical network unit, an optical communication method, and a computer readable medium.
Background
In the communication process, a transmitting end performs corresponding processing, such as modulation, encoding, and the like, on a signal before transmitting the signal, and transmits the processed signal to a receiving end via a communication channel. During processing at the transmitting end and signal transmission, the signal may be subject to various impairments, with noise and/or distortion. To be able to recover the payload data from the received signal, the receiving end typically employs an analog-to-digital converter (ADC) and a powerful Digital Signal Processor (DSP) to reduce these impairments.
To support a powerful DSP, the ADC becomes the necessary device to accurately quantize the signal before the DSP. However, for operators, employing ADCs in Optical Network Units (ONUs) would add significant cost.
Disclosure of Invention
Embodiments of the present disclosure provide an ONU, an optical communication method, and a computer-readable medium.
In a first aspect, an embodiment of the present disclosure provides an ONU. The ONU comprises an adjuster configured to adjust, based on the equalized first digital signal, a second analog signal received from the optical line terminal after the first analog signal to obtain an adjusted second analog signal. The second analog signal is superimposed with the first analog signal, and the equalized first digital signal is generated based on the first analog signal. The ONU further comprises a digital signal decider configured to decide the adjusted second analog signal as a single-bit digital signal. The ONU further comprises an equalizer configured to equalize the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal. The ONU also includes a memory configured to store the equalized first digital signal and the equalized second digital signal.
In some embodiments, the regulator comprises: an acquisition module configured to acquire the equalized first digital signal from the memory; a weighting module configured to weight the equalized first digital signal with a predetermined weight to generate a digital adjustment amount; a digital-to-analog converter configured to convert the digital adjustment amount into an analog adjustment amount; and an adder configured to add the analog adjustment amount to the second analog signal to obtain an adjusted second analog signal.
In some embodiments, the equalizer comprises a decision feedback equalizer.
In some embodiments, the digital signal determiner includes a binary clock data determining module.
In some embodiments, the digital signal decider comprises: a duobinary clock data decision module configured to decide the adjusted second analog signal as a duobinary signal; the equalizer is further configured to equalize the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and the ONU further comprises: a maximum likelihood sequence estimation module configured to convert the equalized duobinary signal into a binary signal.
In a second aspect, embodiments of the present disclosure provide an optical communication method. The method comprises adjusting a second analog signal received from the optical line terminal after the first analog signal based on the equalized first digital signal to obtain an adjusted second analog signal. The second analog signal is superimposed with the first analog signal, and the equalized first digital signal is generated based on the first analog signal. The method also includes deciding the adjusted second analog signal as a single-bit digital signal. The method also includes equalizing the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal. The method also includes storing the equalized second digital signal.
In some embodiments, adjusting the second analog signal comprises: obtaining an equalized first digital signal; weighting the equalized first digital signal with a predetermined weight to generate a digital adjustment amount; converting the digital adjustment amount into an analog adjustment amount; and adding the analog adjustment to the second analog signal to obtain an adjusted second analog signal.
In some embodiments, the method further comprises: generating a decision value based on the equalized first digital signal, the decision value indicating a payload from the optical line terminal; and storing the decision value.
In some embodiments, deciding the adjusted second analog signal as a single-bit digital signal comprises: the adjusted second analog signal is decided as a binary signal.
In some embodiments, deciding the adjusted second analog signal as a single-bit digital signal comprises: determining the adjusted second analog signal as a duobinary signal; equalizing the single-bit digital signal based on the equalized first digital signal comprises: equalizing the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and the method further comprises: the equalized duobinary signal is converted into a binary signal.
In a third aspect, embodiments of the present disclosure provide a computer readable medium having a computer program stored thereon. The computer program comprises instructions which, when executed by the processor, cause the processor to perform the method according to the second aspect.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.
Drawings
The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the disclosure.
Fig. 1 shows a schematic diagram of an optical network unit in a conventional scheme;
figure 2 illustrates a schematic diagram of an optical network unit, according to some embodiments of the present disclosure;
figure 3 shows a schematic diagram of an optical network unit according to other embodiments of the present disclosure;
figure 4 shows a flow diagram of a method implemented at an optical network unit according to an embodiment of the present disclosure;
5(a) to 5(d) show graphs comparing the performance of the solution according to an embodiment of the present disclosure with a conventional solution; and
fig. 6 illustrates a block diagram of an apparatus suitable for implementing certain embodiments of the present disclosure.
Detailed Description
Some example embodiments will be described below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
The term "passive optical network" or "PON" as used herein means that the Optical Distribution Network (ODN) it comprises consists of passive devices such as optical splitters and optical fibers, without the need for any active devices.
The term "optical line terminal" or "OLT" as used herein refers to a device in a PON that serves end users as a service providing node. The OLT may, for example, provide an electrical-to-optical conversion function to send data out through an optical fiber in the ODN.
The term "optical network unit" or "ONU" as used herein refers to a client node connected to an OLT by an optical fiber to receive user data from the OLT.
The term "equalization" as used herein refers to the suppression or elimination of impairments introduced by noise, distortion, etc. in the received signal at the receiving end in order to obtain the payload intended for transmission at the transmitting end.
The term "circuitry" as used herein refers to one or more of the following:
(a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry); and
(b) a combination of hardware circuitry and software, such as (if applicable): (i) a combination of analog and/or digital hardware circuitry and software/firmware, and (ii) any portion of a hardware processor and software (including a digital signal processor, software, and memory that work together to cause an apparatus, such as an OLT or other computing device, to perform various functions); and
(c) a hardware circuit and/or processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but may lack software when software is not required for operation.
The definition of circuit applies to all usage scenarios of this term in this application, including any claims. As another example, the term "circuitry" as used herein also covers an implementation of merely a hardware circuit or processor (or multiple processors), or a portion of a hardware circuit or processor, or software or firmware accompanying it. For example, the term "circuitry" would also cover a baseband integrated circuit or processor integrated circuit or a similar integrated circuit in an ONU or other computing device, if applicable to the particular claim element.
The terms "include" and variations thereof as used herein are inclusive and open-ended, i.e., "including but not limited to. The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". Relevant definitions for other terms will be given in the following description.
Fig. 1 shows a schematic diagram of an optical network unit 100 in a conventional scheme. As shown, an Optical Network Unit (ONU)100 includes an analog-to-digital converter (ADC)110 and a Digital Signal Processor (DSP) 120. An Optical Line Terminal (OLT) sends optical signals to the ONUs 100 at a transmission rate of 50Gb/s using 25GHz bandwidth optics. Accordingly, the ONU 100 receives a 50Gb/s optical signal from the OLT. In the ONU 100, the received optical signal is converted into an electrical signal 102 and then input to the ADC 110. The ADC110 is a high resolution, wideband ADC having a bandwidth of at least 25GHz, a sampling rate of at least 100GSa/s, and a resolution of at least 8 bits. The ADC110 is used to accurately quantize the electrical signal 102 into the digital signal 104. The DSP 120 has a large processing power and is capable of processing the digital signal 104 to compensate for the impairments experienced by the signal transmitted by the OLT during transmission, thereby generating an undistorted signal 106. However, high resolution ADCs with sampling rates above 50GSa/s are very expensive. Therefore, it would add significant cost to the operator to employ such ADCs in ONUs.
To at least partially address the above and other potential drawbacks and problems in existing solutions, embodiments of the present disclosure propose an ONU. In an ONU according to an embodiment of the present disclosure, a current reception signal is adjusted using an equalized historical reception signal to obtain an adjusted reception signal, the adjusted reception signal is decided as a single-bit digital signal using a low-cost digital signal decider, and the single-bit digital signal is equalized based on the equalized historical signal to obtain a distortion-free reception signal. The ONU according to the embodiment of the disclosure does not adopt the expensive ADC with high resolution, thereby reducing the cost of the ONU. Hereinafter, several examples of an ONU according to embodiments of the present disclosure will be described with reference to fig. 2 to 3.
Fig. 2 shows a schematic diagram of an ONU 200 according to an embodiment of the present disclosure. The ONU 200 includes an adjuster 210, a digital signal decider 220, an equalizer 230, and a memory 240. It should be understood that the ONU 200 may further comprise additional modules not shown and/or may omit the modules shown. The scope of the disclosed embodiments is not limited in this respect. For example, before the adjuster 210, the ONU 200 may further include an optical-to-electrical converter for converting an optical signal received from the OLT into an electrical signal. As another example, after equalizer 230, ONU 200 may further comprise a Forward Error Correction (FEC) module for performing forward error correction on the equalized signal.
The adjuster 210 is configured to adjust, based on the equalized first digital signal 201, a second analog signal 203 received from the OLT after the first analog signal to obtain an adjusted second analog signal 205. The second analog signal 205 is superimposed with the first analog signal, and the equalized first digital signal 201 is generated based on the first analog signal. Since the first analog signal is received before the second analog signal 203, for ease of discussion, the first analog signal is also referred to as a historical received signal, the second analog signal 203 is also referred to as a current received signal, the equalized first digital signal 201 is also referred to as an equalized historical received signal, and the equalized second digital signal 209 is also referred to as an equalized current received signal.
The digital signal decider 220 is configured to decide the adjusted second analog signal 205 as a single-bit digital signal 207. In some embodiments, the digital signal decider 220 includes a binary clock data decision module, also referred to as a non-return-to-zero (NRZ) CDR module. In such embodiments, the digital signal decider 220 may decide the adjusted second analog signal 205 as a binary signal, e.g., 0 or 1.
In other embodiments, the digital signal decider 220 includes an electrical duobinary clock data decision (EDB CDR) module. In such an embodiment, the digital signal decider 220 may decide the adjusted second analog signal 205 as a duobinary signal, such as 0, 1, or-1. In such an embodiment, the equalizer 230 is further configured to equalize the duobinary signal based on the equalized first digital signal 201 to obtain an equalized duobinary signal. Furthermore, the ONU 200 may further comprise a Maximum Likelihood Sequence Estimation (MLSE) module configured to convert the equalized duobinary signal into a binary signal.
The equalizer 230 is configured to equalize the single-bit digital signal 207 based on the equalized first digital signal 201 to generate an equalized second digital signal 209.
In some implementations, a first learning model (also referred to as an equalization model) may be constructed based on Artificial Intelligence (AI) techniques and a parameter set of the equalization model is determined using a known single-bit digital signal (i.e., the output value of the digital signal decider 220), the equalized history signal, and the equalized current signal to indicate an association between the three. After sufficient learning, the obtained model has reduced computational complexity requirements, and thus equalizer 230 may be implemented by a lower cost processing device, such as a DSP.
In some embodiments, equalizer 230 may include a Decision Feedback Equalizer (DFE). Since the output of the digital signal decider 220 is a digital signal, the output of the digital signal decider 220 can be stored, so that a large amount of information is available for the decision feedback equalizer. The decision feedback equalizer may be configured to generate a historical decision value based on the equalized first digital signal, the historical decision value being indicative of a historical payload from the OLT. The historical decision values may be stored in the memory 240. Equalizer 230 may thus make a decision on the currently received signal based on the historical decision values.
The memory 240 is configured to store the equalized first digital signal 201 and the equalized second digital signal 209. In some embodiments, an analog signal received from the OLT is input into the regulator 210 at the beginning of each clock cycle (e.g., 20ps for a 50Gb/s PON), and at the end of each clock cycle, the equalizer 230 outputs an equalized digital signal and stores the equalized digital signal in the memory 240.
In an embodiment of the present disclosure, a current received signal is adjusted using an equalized historical received signal to obtain an adjusted received signal. Therefore, under the condition that a small difference exists between the current received signal and a subsequently received signal, the equalized historical received signal is utilized to adjust the current received signal and the subsequently received signal to have a large difference, and different decision values are obtained at the output of the digital signal judger. Furthermore, since the history received signal is superimposed on the current received signal and the equalized history received signal is a history signal without distortion after removing interference, the current received signal can be equalized by removing the equalized history received signal from the current received signal, thereby obtaining a current signal without distortion. In the ONU according to the embodiment of the present disclosure, the damage that the signal undergoes during transmission is also compensated and the cost of the ONU is reduced without using an expensive high-resolution ADC.
Figure 3 shows a schematic diagram of an ONU 300 according to some other embodiments of the present disclosure. The ONU 300 may be seen as an example implementation of the ONU 200 described above. In this example, the adjuster 210 includes an acquisition module 310, a weighting module 320, a digital-to-analog converter (DAC)330, and an adder 340.
The acquisition module 310 is configured to acquire the equalized first digital signal 201 from the memory 240.
The weighting module 320 is configured to weight the equalized first digital signal 201 with a predetermined weight to generate the digital adjustment amount 301. In some implementations, a second learning model (also referred to as a weighting model) can be constructed based on AI techniques, and a parameter set (i.e., weights) of the weighting model is determined using the known equalized first digital signal and the digital adjustment. After sufficient learning, the obtained model has reduced computational complexity requirements, so the weighting module 320 can be implemented by a less costly processing device, such as a DSP.
The DAC 330 is configured to convert the digital adjustment amount 301 into an analog adjustment amount 303. The adder 340 is configured to add the analog adjustment 303 to the second analog signal 203 to obtain an adjusted second analog signal 205.
It will be appreciated that since the memory 240 has the equalized first digital signal 201 and the equalized second digital signal 209 stored therein, if it is desired to adjust a third analog signal received after the second analog signal, the third analog signal may be adjusted and equalized based on the equalized first digital signal 201 and the equalized second digital signal 209.
For example, the equalized first digital signal 201 and the equalized second digital signal 209 may be weighted via the weighting module 320, respectively, to obtain a weighted first signal and a weighted second signal, and further to calculate a sum of the weighted first signal and the weighted second signal. The sum is converted to an analog adjustment using DAC 330. The analog adjustment amount is added to the third analog signal using adder 340 to obtain an adjusted third analog signal. The adjusted third analog signal is decided as a single-bit digital signal using the digital signal decider 220. The single-bit digital signal is equalized with equalizer 230 based on equalized first digital signal 201 and equalized second digital signal 209 to generate an equalized third digital signal.
The ONU according to the embodiment of the present disclosure is described above with reference to fig. 2 and 3, and the optical communication method 400 will be described below with reference to fig. 4.
Fig. 4 shows a flow diagram of an optical communication method 400 according to an embodiment of the present disclosure. In some embodiments, method 400 may be implemented by ONU 200 in fig. 2 or ONU 300 in fig. 3. For ease of discussion, the method 400 will be described below with reference to fig. 2. It is to be understood that method 400 may also include additional acts not shown and/or may omit acts shown. The scope of the disclosed embodiments is not limited in this respect.
At 410, the ONU 200 adjusts the second analog signal 203 received from the OLT after the first analog signal based on the equalized first digital signal 201 to obtain an adjusted second analog signal 205. The first analog signal is superimposed on the second analog signal 203. The equalized first digital signal 201 is generated based on the first analog signal.
At 420, the ONU 200 decides the adjusted second analog signal 205 as the single-bit digital signal 207. At 430, the ONU 200 equalizes the single-bit digital signal 207 based on the equalized first digital signal 201 to generate an equalized second digital signal 209. At 440, the ONU 200 stores the equalized second digital signal 209.
In some embodiments, adjusting the second analog signal 203 comprises: obtaining an equalized first digital signal 201; weighting the equalized first digital signal 201 with a predetermined weight to generate a digital adjustment amount; converting the digital adjustment amount into an analog adjustment amount; and adding the analog adjustment to the second analog signal to obtain an adjusted second analog signal.
In some embodiments, the method 400 further comprises: generating a decision value based on the equalized first digital signal, the decision value indicating a payload from the optical line terminal; and storing the decision value.
In some embodiments, deciding the adjusted second analog signal as a single-bit digital signal comprises: the adjusted second analog signal is decided as a binary signal.
In some embodiments, deciding the adjusted second analog signal as a single-bit digital signal comprises: determining the adjusted second analog signal as a duobinary signal; equalizing the single-bit digital signal based on the equalized first digital signal comprises: equalizing the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and the method 400 further comprises: the equalized duobinary signal is converted into a binary signal.
It should be understood that the various features described above with reference to fig. 2 and 3 are equally applicable to the method 400, and thus, a detailed description thereof is omitted herein.
Hereinafter, performance comparison of an equalization scheme according to an embodiment of the present disclosure with a conventional equalization scheme is described with reference to fig. 5(a) to 5 (d). The equalization scheme according to the present disclosure can compensate for the impairments experienced by the signal during transmission and has a lower cost. To verify this effect, the equalizer 230 and the adjuster 210 in fig. 3 are implemented by running a Recurrent Neural Network (RNN) algorithm in the DSP. The key parameters are shown in table 1.
TABLE 1
Fig. 5(a) and 5(b) show 0/1 level distribution functions (pdf) and Bit Error Rates (BER) for an equalization scheme according to an embodiment of the disclosure. Fig. 5(c) and 5(d) show 0/1 level distribution function (pdf) and Bit Error Rate (BER) according to the conventional equalization scheme. As can be seen from fig. 5(b), the BER of the equalization scheme of the embodiment of the present disclosure is on the order of 1E-3. As can be seen from fig. 5(d), the BER of the conventional equalization scheme is of the order of 1E-4.
In some embodiments, a device capable of performing the method 400 (e.g., the ONU 200) may comprise respective means for performing the steps of the method 400. These components may be implemented in any suitable manner. For example, it may be implemented by a circuit or a software module.
In some embodiments, the apparatus comprises means for adjusting a second analog signal received from the optical line terminal after the first analog signal based on the equalized first digital signal to obtain an adjusted second analog signal, the second analog signal having the first analog signal superimposed thereon, the equalized first digital signal being generated based on the first analog signal; means for determining the adjusted second analog signal as a single-bit digital signal; means for equalizing the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal; and means for storing the equalized second digital signal.
In some embodiments, the means for adjusting the second analog signal comprises: means for obtaining an equalized first digital signal; means for weighting the equalized first digital signal with a predetermined weight to generate a digital adjustment amount; means for converting the digital adjustment amount into an analog adjustment amount; and means for adding the analog adjustment to the second analog signal to obtain an adjusted second analog signal.
In some embodiments, the apparatus further comprises: means for generating a decision value based on the equalized first digital signal, the decision value indicating a payload from the optical line terminal; and means for storing the decision value.
In some embodiments, the means for deciding the adjusted second analog signal as a single-bit digital signal comprises: means for deciding the adjusted second analog signal as a binary signal.
In some embodiments, the means for deciding the adjusted second analog signal as a single-bit digital signal comprises: means for determining the adjusted second analog signal as a duobinary signal; the means for equalizing the single-bit digital signal based on the equalized first digital signal comprises: means for equalizing the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and the apparatus further comprises: means for converting the equalized duobinary signal to a binary signal.
Fig. 6 illustrates a block diagram of an apparatus 600 suitable for implementing embodiments of the present disclosure. The apparatus 600 may be used to implement an ONU capable of implementing the operations and functions described herein, such as the ONU described with reference to fig. 2-5.
As shown in fig. 6, the apparatus 600 includes a processor 610. The processor 610 controls the operation and functions of the device 600. For example, in some embodiments, the processor 610 may perform various operations by way of instructions 630 stored in a memory 620 coupled thereto. The memory 620 may be of any suitable type suitable to the local technical environment and may be implemented using any suitable data storage technology, including but not limited to semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems. Although only one memory unit is shown in FIG. 6, there may be multiple physically distinct memory units in device 600.
The processor 610 may be of any suitable type suitable to the local technical environment, and may include, but is not limited to, one or more of general purpose computers, special purpose computers, microcontrollers, digital signal controllers (DSPs), and controller-based multi-core controller architectures. The apparatus 600 may also include a plurality of processors 610. The apparatus 600 may implement the reception and transmission of information by means of optical fibers or cables, etc.
The processor 610, by executing the instructions, causes the apparatus 600 to perform the relevant operations and features of the ONU described above with reference to fig. 2-5. All of the features described above with reference to fig. 2-5 apply to the apparatus 600 and are not described in detail herein.
In general, the various example embodiments of this disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of embodiments of the disclosure have been illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
By way of example, embodiments of the disclosure may be described in the context of machine-executable instructions, such as those included in program modules, being executed in a device on a target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or divided between program modules as described. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.
Computer program code for implementing the methods of the present disclosure may be written in one or more programming languages. These computer program codes may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the computer or other programmable data processing apparatus, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
In the context of the present disclosure, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus or processor to perform various processes and operations described above. Examples of a carrier include a signal, computer readable medium, and the like.
Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.
The computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.
Additionally, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking or parallel processing may be beneficial. Likewise, while the above discussion contains certain specific implementation details, this should not be construed as limiting the scope of any invention or claims, but rather as describing particular embodiments that may be directed to particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (12)
1. An optical network unit comprising:
an adjuster configured to adjust, based on an equalized first digital signal, a second analog signal received from an optical line terminal after a first analog signal, in which the first analog signal is superimposed, to obtain an adjusted second analog signal, the equalized first digital signal being generated based on the first analog signal;
a digital signal decider configured to decide the adjusted second analog signal as a single-bit digital signal;
an equalizer configured to equalize the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal; and
a memory configured to store the equalized first digital signal and the equalized second digital signal.
2. The optical network unit of claim 1, wherein the adjuster comprises:
an acquisition module configured to acquire the equalized first digital signal from the memory;
a weighting module configured to weight the equalized first digital signal with a predetermined weight to generate a digital adjustment;
a digital-to-analog converter configured to convert the digital adjustment amount to an analog adjustment amount; and
an adder configured to add the analog adjustment amount to the second analog signal to obtain the adjusted second analog signal.
3. The optical network unit of claim 1, wherein the equalizer comprises a decision feedback equalizer.
4. The optical network unit of claim 1, wherein the digital signal determiner comprises a binary clock data determining module.
5. The optical network unit of claim 1, wherein:
the digital signal decision device includes: a duobinary clock data decision module configured to decide the adjusted second analog signal as a duobinary signal;
the equalizer is further configured to equalize the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and is
The optical network unit further comprises: a maximum likelihood sequence estimation module configured to convert the equalized duobinary signal into a binary signal.
6. An optical communication method, comprising:
adjusting a second analog signal received from the optical line terminal after the first analog signal based on the equalized first digital signal to obtain an adjusted second analog signal, the second analog signal having the first analog signal superimposed thereon, the equalized first digital signal being generated based on the first analog signal;
determining the adjusted second analog signal as a single-bit digital signal;
equalizing the single-bit digital signal based on the equalized first digital signal to generate an equalized second digital signal; and
storing the equalized second digital signal.
7. The method of claim 6, wherein adjusting the second analog signal comprises:
obtaining the equalized first digital signal;
weighting the equalized first digital signal with a predetermined weight to generate a digital adjustment;
converting the digital adjustment amount into an analog adjustment amount; and
adding the analog adjustment to the second analog signal to obtain the adjusted second analog signal.
8. The method of claim 6, further comprising:
generating a decision value based on the equalized first digital signal, the decision value indicating a payload from the optical line terminal; and
and storing the decision value.
9. The method of claim 6, wherein deciding the adjusted second analog signal as the single-bit digital signal comprises:
the adjusted second analog signal is decided as a binary signal.
10. The method of claim 6, wherein:
deciding the adjusted second analog signal as the single-bit digital signal comprises: determining the adjusted second analog signal as a duobinary signal;
equalizing the single-bit digital signal based on the equalized first digital signal comprises: equalizing the duobinary signal based on the equalized first digital signal to obtain an equalized duobinary signal; and is
The method further comprises: converting the equalized duobinary signal to a binary signal.
11. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform the method of any of claims 1-5.
12. A computer-readable medium, on which a computer program is stored, the computer program comprising instructions which, when executed by a processor, cause the processor to carry out the method according to any one of claims 1 to 5.
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