CN110597665A - Power-down protection device - Google Patents
Power-down protection device Download PDFInfo
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- CN110597665A CN110597665A CN201910884993.6A CN201910884993A CN110597665A CN 110597665 A CN110597665 A CN 110597665A CN 201910884993 A CN201910884993 A CN 201910884993A CN 110597665 A CN110597665 A CN 110597665A
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- 238000001514 detection method Methods 0.000 claims abstract description 58
- 230000005856 abnormality Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 26
- 230000009977 dual effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 6
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000005389 magnetism Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1433—Saving, restoring, recovering or retrying at system level during software upgrading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1448—Management of the data involved in backup or backup restore
- G06F11/1451—Management of the data involved in backup or backup restore by selection of backup contents
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Abstract
The invention discloses a power failure protection device, which comprises a power failure detection module, a flag bit circuit and a control module; the control module is used for upgrading and updating the software data; software backup data corresponding to the software data are stored in the backup storage area; the power failure detection module is used for detecting the power supply state of the power supply; generating a first state signal when the power supply abnormality of the power supply is detected; the flag bit circuit is used for setting the flag bit circuit to be in an action state when receiving a first state signal transmitted by the power failure detection module and generating an action flag bit signal; when the control module is normally powered on through the power supply and is in an initialization stage, the control module is also used for controlling the zone bit circuit to be in a reset state and overwriting the software backup data into the storage area of the software data if receiving an action zone bit signal transmitted by the zone bit circuit. The invention can improve the reliability of power failure protection and ensure that the equipment can normally start software after power supply is recovered.
Description
Technical Field
The invention relates to the technical field of power failure protection, in particular to a power failure protection device.
Background
When a user sets software of a device for updating, for example, when the software of a router is updated, the device may be abnormally powered down due to sudden insufficient power supply, poor connection of power supply wires, or misoperation of the user, which may result in unexpected interruption of software updating. Because the software data is erased and rewritten during software updating, the data can be lost after the updating is interrupted unexpectedly, and further the software starting abnormality of the equipment is caused.
At present, the scheme of performing power failure protection on software update usually adopts a pure software means to perform data protection when power failure occurs, for example, to perform software update cancellation and restore original data.
However, because a power failure event often occurs suddenly and a process from power failure to complete failure of a power supply is short, an uncontrollable factor exists when data protection is performed in the power failure by a pure software means and there is a possibility that sufficient time is not available for data protection, so that the existing power failure protection scheme has poor reliability.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a power failure protection device, which can improve the reliability of power failure protection and ensure that the device can normally start software after power supply is restored.
In order to solve the technical problem, an embodiment of the present invention provides a power-down protection device, which includes a power-down detection module, a flag bit circuit and a control module, wherein the control module and the power-down detection module are both connected to a power supply, the power-down detection module is connected to the flag bit circuit, and the control module is connected to the flag bit circuit; wherein,
the control module is used for upgrading and updating software data; software backup data corresponding to the software data are stored in a preset backup storage area;
when the control module updates the software data, the power failure detection module is used for detecting the power supply state of the power supply; when the power supply abnormality of the power supply is detected, a first state signal is generated;
the zone bit circuit is used for setting the zone bit circuit to be in an action state when receiving the first state signal transmitted by the power failure detection module and generating an action zone bit signal;
when the control module is normally powered on through the power supply and is in an initialization stage, the control module is further configured to control the flag bit circuit to be in a reset state and write the software backup data into the storage area of the software data in a covering manner if the control module receives the action flag bit signal transmitted by the flag bit circuit.
Further, the power failure detection module is further configured to generate a second state signal when detecting that the power supply of the power supply is normal;
the zone bit circuit is also used for setting the zone bit circuit to be in a reset state when receiving the second state signal transmitted by the power failure detection module and generating a reset zone bit signal;
when the control module is just updating the software data, the control module is further configured to continue updating the software data if the reset flag bit signal transmitted by the flag bit circuit is received.
Further, the zone bit circuit comprises a magnetic latching relay and a first power supply;
the first end of the magnetic latching relay is connected with the output end of the power failure detection module, the second end of the magnetic latching relay is connected with the control end of the control module, the third end of the magnetic latching relay is connected with the first power supply, and the fourth end of the magnetic latching relay is grounded;
and the zone bit signal output end of the magnetic latching relay is connected with the zone bit signal detection end of the control module.
Further, the magnetic latching relay is a single-coil magnetic latching relay, and the single-coil magnetic latching relay comprises a first coil and a first switching device; wherein,
the first end of the first coil is the first end of the magnetic latching relay, and the second end of the first coil is the second end of the magnetic latching relay;
the fixed end of the first switching switch device is a zone bit signal output end of the magnetic latching relay, the first switching end of the first switching switch device is a third end of the magnetic latching relay, and the second switching end of the first switching switch device is a fourth end of the magnetic latching relay.
Furthermore, the magnetic latching relay is a double-coil magnetic latching relay, and the double-coil magnetic latching relay comprises an action coil, a reset coil and a second change-over switch device; wherein,
the first end of the action coil is the first end of the magnetic latching relay, the first end of the reset coil is the second end of the magnetic latching relay, and the second end of the action coil and the second end of the reset coil are both grounded;
the fixed end of the second switching switch device is a zone bit signal output end of the magnetic latching relay, the first switching end of the second switching switch device is a third end of the magnetic latching relay, and the second switching end of the second switching switch device is a fourth end of the magnetic latching relay.
Further, the flag bit circuit further comprises a first resistor and a second resistor; wherein,
the first end of the first resistor is connected with the third end of the magnetic latching relay, and the second end of the first resistor is connected with the first power supply;
and the first end of the second resistor is connected with the fourth end of the magnetic latching relay, and the second end of the second resistor is grounded.
Furthermore, the power failure detection module comprises a first triode, a second triode, a first diode, a first capacitor, a second capacitor, a third resistor, a fourth resistor and a fifth resistor; wherein,
the first end of the first triode is connected with the first end of the third resistor, the second end of the first triode is connected with the first end of the first capacitor, and the third end of the first triode is grounded; the second end of the third resistor is used for connecting the power supply, and the second end of the first capacitor is grounded;
a first end of the first diode is connected with a first end of the first capacitor, and a second end of the first diode is used for connecting the power supply;
the first end of the second triode is connected with the first end of the fourth resistor, the second end of the second triode is connected with the first end of the fifth resistor, and the third end of the second triode is grounded;
a second end of the fourth resistor is connected with a third end of the first triode, and a second end of the fifth resistor is used for connecting a second power supply;
the first end of the second capacitor is connected with the second end of the fifth resistor, and the second end of the second capacitor is grounded;
and the second end of the second triode is the output end of the power failure detection module.
Further, the power failure detection module comprises a second diode, a sixth resistor and a seventh resistor; wherein,
the first end of the second diode is connected with the first end of the third resistor, and the second end of the second diode is grounded;
a first end of the sixth resistor is connected with a first end of the first triode, and a second end of the sixth resistor is connected with a first end of the third resistor;
and the first end of the seventh resistor is connected with the third end of the first triode, and the second end of the seventh resistor is grounded.
Further, the first triode is a first PNP type triode, and the second triode is a second PNP type triode; wherein,
the base electrode of the first PNP type triode is the first end of the first triode, the emitter electrode of the first PNP type triode is the second end of the first triode, and the collector electrode of the first PNP type triode is the third end of the first triode;
the base electrode of the second PNP type triode is the first end of the second triode, the emitting electrode of the second PNP type triode is the second end of the second triode, and the collector electrode of the second PNP type triode is the third end of the second triode.
Furthermore, the first end of the first diode is the cathode of the first diode, and the second end of the first diode is the anode of the first diode.
According to the power failure detection device, the power supply state of the power supply is detected through the power failure detection module, the flag bit circuit is set to be in the action state and maintained when the power supply of the power supply is abnormal, so that the action flag bit signal is continuously generated, and the control module can be guaranteed to know a power failure event and rewrite software backup data to perform power failure protection when being powered on again. Because the flag bit circuit is set through the state of the flag bit circuit, the action flag bit signal is continuous and stable, the control module executes the power-down protection action in the initialization stage when restarting, the software backup data is written into the corresponding storage area, the control module can be triggered to perform the power-down protection without time limitation, the power-down protection is not required to be performed in the short time period from the power failure to the power failure when the power-down occurs, the reliability of the power-down protection is improved, and the equipment can normally start the software after power supply is restored.
Drawings
Fig. 1 is a schematic structural diagram of a first preferred embodiment of a power down protection apparatus provided in the present invention;
fig. 2 is a schematic structural diagram of a second preferred embodiment of a power down protection apparatus provided in the present invention;
fig. 3 is a schematic structural diagram of a third preferred embodiment of a power down protection device provided by the present invention;
fig. 4 is a schematic structural diagram of a fourth preferred embodiment of a power down protection device provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a power failure protection device, please refer to fig. 1, fig. 1 is a schematic structural diagram of a first preferred embodiment of the power failure protection device provided by the invention; specifically, the device comprises a power failure detection module 1, a flag bit circuit 2 and a control module 3, wherein the control module 3 and the power failure detection module 1 are both connected with a power supply 4, the power failure detection module 1 is connected with the flag bit circuit 2, and the control module 3 is connected with the flag bit circuit 2; wherein,
the control module 3 is used for updating software data; software backup data corresponding to the software data are stored in a preset backup storage area;
when the control module 3 updates the software data, the power failure detection module 1 is used for detecting the power supply state of the power supply 4; when the power supply abnormality of the power supply source 4 is detected, a first state signal is generated;
the flag bit circuit 2 is configured to set itself in an action state and generate an action flag bit signal when receiving the first state signal transmitted by the power failure detection module 1;
when the control module 3 is normally powered on through the power supply 4 and is in an initialization stage, the control module is further configured to control the flag bit circuit 2 to be in a reset state and write the software backup data into the storage area of the software data in an overwriting manner if the control module receives the action flag bit signal transmitted by the flag bit circuit 2.
The software data refers to data of a current version of software that is being used before updating, and is located in a storage area where software is read and written, and the software backup data may be data of the same version and content as the software data, or data of the version when the system is factory set.
It should be noted that the flag bit circuit has a reset state and an action state, and when the flag bit circuit is in the action state, because the state is not changed, the action flag bit signal transmitted to the control module is continuous, and the action flag bit signal does not disappear if a signal generated on pure software is transmitted to the control module, but the action flag bit signal in the action state is continuously transmitted through the circuit, and the action flag bit signal disappears only when the state of the flag bit circuit is changed into the reset state, which is an important technical means for ensuring that the control module can know whether power down occurs during updating and cannot trigger the control module to perform power down protection due to time limitation. The flag bit circuit is set to be in a reset state by default, is set to be in an action state when the power supply of the power supply is abnormal, and is set to be in the reset state after being controlled by the control module.
Specifically, according to the power failure detection device provided by the invention, the control module can respond to an update instruction of a user or automatic update of background setting, and update software data; in the process of upgrading and updating software, a power failure detection module continuously detects the power supply state of a power supply, and when the power supply abnormality of the power supply is detected, a first state signal is generated and transmitted to a flag bit circuit; after receiving the first state signal transmitted by the power failure detection module, the zone bit circuit sets the zone bit circuit to be in an action state so as to continuously output an action zone bit signal to the control module through the circuit; when the power supply of the power supply source is abnormal and the power failure occurs, the power failure detection device is powered on again, the control module is normally powered on through the power supply source and enters an initialization stage after the power supply and the startup, if the control module receives an action zone bit signal, the control module can know that the power failure event occurs during the software updating period after the last system or equipment is started, the control module controls the zone bit circuit to be restored to a reset state, and the software backup data is extracted and written into a storage area where the software data is located during the updating in the initialization stage, so that the system or the equipment can normally start corresponding software functions.
It should be noted that, if the data set by the user is not stored in the software backup data, the software backup data can be used normally through the configuration of the user after being written into the storage area where the software data is located during updating. The power failure detection device provided by the invention can be arranged in any suitable equipment, such as gateway equipment such as a router. The corresponding function of the power failure detection module can be realized by software, hardware or software and hardware, preferably, in order to make the corresponding function of the power failure detection module more reliable, the power failure detection module is preferably realized by hardware.
According to the power failure detection device provided by the invention, the power supply state of the power supply is detected through the power failure detection module, and the flag bit circuit is used for setting the power supply state as the action state and maintaining the action state when the power supply of the power supply is abnormal so as to continuously generate the action flag bit signal, so that the control module can be ensured to acquire a power failure event and rewrite software backup data to carry out power failure protection when being electrified again. Because the zone bit circuit is set through the self state, the action zone bit signal is continuous and stable, and the control module executes the power-down protection action in the initialization stage when restarting, the software backup data is written into the corresponding storage area, the control module can be triggered to carry out the power-down protection without being limited by time, the power-down protection is not required to be carried out in the short time period from the power failure when the power-down happens, the reliability of the power-down protection is improved, and the equipment can be normally started after the power supply is restored.
Preferably, the power failure detection module 1 is further configured to generate a second state signal when it is detected that the power supply of the power supply 4 is normal;
the zone bit circuit 2 is further configured to set itself in a reset state and generate a reset zone bit signal when receiving the second state signal transmitted by the power failure detection module 1;
when the control module is just updating the software data, the control module is further configured to continue updating the software data if the reset flag bit signal transmitted by the flag bit circuit is received.
Specifically, when the control module starts the device or the system, if a reset flag bit signal transmitted by the flag bit circuit is received, the control module can know to continue a normal starting process; when the control module finishes starting and updates software data, the zone bit circuit is in a default reset state, the power failure detection module detects that the power supply of the power supply is normal, a second state signal is transmitted to the zone bit circuit, the zone bit circuit continuously keeps setting itself in the reset state according to the second state signal, and the reset zone bit signal is transmitted to the control module; if the control module is upgrading and updating the software data, the control module receives the reset flag bit signal to know that the software data updating process is continued.
When a power failure event occurs in the updating process, the power failure detection module detects that the power supply of the power supply is abnormal, a first state signal is generated, the zone bit circuit sets the zone bit circuit to be in an action state according to the received first state signal, the action zone bit signal is continuously output, and the control module stops the updating process of the software data due to the abnormal power supply. After the power failure fault is eliminated, the control module is electrified again, the system or the equipment is started again, the control module enters an initialization stage first to initialize the system or the equipment, at the moment, if an action zone bit signal of the zone bit circuit is received, the control module knows that the previous updating process is interrupted, the control module writes the software backup data into a storage area where the previous software data are located, and controls the zone bit circuit to be restored to a reset state. After the software backup data is written, the software can be normally started according to the newly written software backup data, and the software upgrading and updating process can be carried out again. And the flag bit circuit is recovered to a reset state, and continues to receive the first state signal or the second state signal transmitted by the power failure detection module.
It should be noted that, after the control module is normally powered on by the power supply, the control module is continuously started again, and the control flag bit circuit is restored to the reset state, so that the above process is performed in a corresponding cycle when software data needs to be updated.
Preferably, referring to fig. 2, fig. 2 is a schematic structural diagram of a second preferred embodiment of a power down protection device provided in the present invention; specifically, the flag bit circuit 2 includes a magnetic latching relay 201 and a first power supply 202;
a first end of the magnetic latching relay 201 is connected with an output end of the power failure detection module 1, a second end of the magnetic latching relay 201 is connected with a control end of the control module 3, a third end of the magnetic latching relay 201 is connected with the first power supply 202, and a fourth end of the magnetic latching relay 201 is grounded;
and the flag bit signal output end of the magnetic latching relay 201 is connected with the flag bit signal detection end of the control module 3.
Specifically, the invention can realize the maintenance process of the reset state and the action state of the zone bit circuit through the magnetic latching relay, and can realize the output of an action zone bit signal or a reset zone bit signal at the zone bit output end through the first power supply and the grounding voltage.
Preferably, referring to fig. 3, fig. 3 is a schematic structural diagram of a power down protection apparatus according to a third preferred embodiment of the present invention; specifically, the magnetic latching relay 201 is a single-coil magnetic latching relay, which includes a first coil K1 and a first switching device SW 1; wherein,
a first end of the first coil K1 is a first end of the magnetic latching relay 201, and a second end of the first coil K1 is a second end of the magnetic latching relay 201;
the fixed terminal of the first switching device SW1 is the flag signal output terminal of the magnetic latching relay 201, the first switching terminal of the first switching device SW1 is the third terminal of the magnetic latching relay 201, and the second switching terminal of the first switching device SW1 is the fourth terminal of the magnetic latching relay 201.
Specifically, the magnetic latching relay is a single-coil magnetic latching relay, the state of the flag circuit is set through the voltage at two ends of a first coil K1, and when the magnetic latching relay is set to be in an action state, a first switching switch device is switched to be communicated with a first power supply, and a high level is output to the control module through a flag signal output end; when the reset state is set, the first switching switch device is switched to be communicated with the ground wire, and the ground level is output to the control module through the flag bit signal output end.
Preferably, referring to fig. 4, fig. 4 is a schematic structural diagram of a fourth preferred embodiment of a power down protection device provided in the present invention; specifically, the magnetic latching relay 201 is a double-coil magnetic latching relay, and the double-coil magnetic latching relay includes an operating coil K2, a reset coil K3, and a second switching device SW 2; wherein,
a first end of the operating coil K2 is a first end of the magnetic latching relay 201, a first end of the reset coil K3 is a second end of the magnetic latching relay 201, and a second end of the operating coil K2 and a second end of the reset coil K3 are both grounded;
the fixed terminal of the second switching device SW2 is the flag signal output terminal of the magnetic latching relay 201, the first switching terminal of the second switching device SW2 is the third terminal of the magnetic latching relay 201, and the second switching terminal of the second switching device SW2 is the fourth terminal of the magnetic latching relay 201.
Specifically, the magnetic latching relay is a double-coil magnetic latching relay, the state of the zone bit circuit is set by controlling the voltage of the first end of the second coil K2 and the first end of the third coil K3, and when the zone bit circuit is set to be in an action state, the second switching switch device is switched to be communicated with the first power supply, and a high level is output to the control module through a zone bit signal output end; when the reset state is set, the second change-over switch device is switched to be communicated with the ground wire, and the ground level is output to the control module through the zone bit signal output end.
Preferably, as shown in fig. 3 to 4, the flag circuit 2 further includes a first resistor R1 and a second resistor R2; wherein,
a first end of the first resistor R1 is connected to the third end of the magnetic latching relay 201, and a second end of the first resistor R1 is connected to the first power VCC 1;
a first end of the second resistor R2 is connected to the fourth end of the magnetic latching relay 201, and a second end of the second resistor R2 is grounded.
Specifically, corresponding voltage division is performed through the first resistor and the second resistor, and a signal of corresponding voltage is provided for the control module.
Preferably, as shown in fig. 3 to 4, the power down detection module 1 includes a first transistor Q1, a second transistor Q2, a first diode D1, a first capacitor C1, a second capacitor C2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; wherein,
a first terminal of the first transistor Q1 is connected to a first terminal of the third resistor R3, a second terminal of the first transistor Q1 is connected to a first terminal of the first capacitor C1, and a third terminal of the first transistor Q1 is grounded; the second end of the third resistor R3 is used for connecting the power supply VCC, and the second end of the first capacitor C1 is grounded;
a first end of the first diode D1 is connected with a first end of the first capacitor C1, and a second end of the first diode D1 is used for connecting the power supply VCC;
a first terminal of the second transistor Q2 is connected to a first terminal of the fourth resistor R4, a second terminal of the second transistor Q2 is connected to a first terminal of the fifth resistor R5, and a third terminal of the second transistor Q2 is grounded;
a second end of the fourth resistor R4 is connected to a third end of the first transistor Q1, and a second end of the fifth resistor R5 is connected to a second power source VCC 2;
a first end of the second capacitor C2 is connected with a second end of the fifth resistor R5, and a second end of the second capacitor C2 is grounded;
the second end of the second triode Q2 is the output end of the power down detection module 1.
Specifically, when the power supply VCC is normally powered, a high voltage is input, the first capacitor is charged, the first triode is cut off, the second triode is conducted, the second capacitor is charged through the second power supply, at the moment, the second end of the second triode is used as the output end of the power failure detection module to output a low level to the flag bit circuit, and at the moment, the magnetic latching relay maintains a reset state; when power supply VCC supplies power when unusual, no high level input, and first electric capacity and second electric capacity discharge this moment, provide voltage to first triode and second triode in a certain time, first triode switches on this moment, and the second triode ends, and the second power provides the high level to the second end of second triode after fifth resistance partial pressure, falls electric detection module's output and exports the high level to the flag bit circuit promptly, and magnetism keeps the relay switch to set up to the action state this moment.
It should be noted that the first diode D1 is used to isolate the first capacitor C1 from the power supply, so as to prevent the power supply from affecting the discharge of the first capacitor to the first triode during power failure; the third resistor R3, the fourth resistor R4 and the fifth resistor R5 have the functions of providing bias voltage for the first triode and the second triode and limiting current. It should be noted that the first triode and the second triode may be NPN type or PNP type, as long as the ends of the triodes are connected to implement the functions of the present invention according to the characteristics of the triodes of various types, and the types of the components in fig. 3 to 4 are only schematic and do not limit the types of the components used in the present invention.
Preferably, as shown in fig. 3 to 4, the power down detection module 1 includes a second diode D2, a sixth resistor R6 and a seventh resistor R7; wherein,
a first end of the second diode D2 is connected with a first end of the third resistor R3, and a second end of the second diode D2 is grounded;
a first end of the sixth resistor R6 is connected to a first end of the first transistor Q1, and a second end of the sixth resistor R6 is connected to a first end of the third resistor R3;
a first terminal of the seventh resistor R7 is connected to the third terminal of the first transistor Q1, and a second terminal of the seventh resistor R7 is grounded.
Specifically, the second diode is used as a voltage stabilizing diode to provide a detection threshold value of the power failure detection module, wherein the detection threshold value is the sum of the nominal voltage stabilizing value of the second diode and 0.7V. The sixth resistor and the seventh resistor also provide bias voltage and current limiting function for the circuit.
Preferably, the first transistor Q1 is a first PNP transistor, and the second transistor Q2 is a second PNP transistor; wherein,
the base electrode of the first PNP type triode is the first end of the first triode, the emitter electrode of the first PNP type triode is the second end of the first triode, and the collector electrode of the first PNP type triode is the third end of the first triode;
the base electrode of the second PNP type triode is the first end of the second triode, the emitting electrode of the second PNP type triode is the second end of the second triode, and the collector electrode of the second PNP type triode is the third end of the second triode.
Specifically, when the first triode and the second triode are PNP triodes, the first end to the third end of the first triode are respectively a base, an emitter and a collector, and the first end to the third end of the second triode are respectively a base, an emitter and a collector, so as to realize the corresponding functions of the power failure detection module.
Preferably, a first terminal of the first diode D1 is a cathode of the first diode D1, and a second terminal of the first diode D1 is an anode of the first diode D1.
Specifically, when the first end and the second end of the first diode are the cathode and the anode respectively, the first capacitor and the power supply can be isolated.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A power failure protection device is characterized by comprising a power failure detection module, a flag bit circuit and a control module, wherein the control module and the power failure detection module are connected with a power supply, the power failure detection module is connected with the flag bit circuit, and the control module is connected with the flag bit circuit; wherein,
the control module is used for upgrading and updating software data; software backup data corresponding to the software data are stored in a preset backup storage area;
when the control module updates the software data, the power failure detection module is used for detecting the power supply state of the power supply; when the power supply abnormality of the power supply is detected, a first state signal is generated;
the zone bit circuit is used for setting the zone bit circuit to be in an action state when receiving the first state signal transmitted by the power failure detection module and generating an action zone bit signal;
when the control module is normally powered on through the power supply and is in an initialization stage, the control module is further configured to control the flag bit circuit to be in a reset state and write the software backup data into the storage area of the software data in a covering manner if the control module receives the action flag bit signal transmitted by the flag bit circuit.
2. The power fail safe apparatus of claim 1, wherein the power fail detect module is further configured to generate a second status signal when detecting that the power supply of the power supply is normal;
the zone bit circuit is also used for setting the zone bit circuit to be in a reset state when receiving the second state signal transmitted by the power failure detection module and generating a reset zone bit signal;
when the control module is just updating the software data, the control module is further configured to continue updating the software data if the reset flag bit signal transmitted by the flag bit circuit is received.
3. The power fail safe apparatus of claim 1, wherein the flag circuit comprises a magnetic latching relay and a first power supply;
the first end of the magnetic latching relay is connected with the output end of the power failure detection module, the second end of the magnetic latching relay is connected with the control end of the control module, the third end of the magnetic latching relay is connected with the first power supply, and the fourth end of the magnetic latching relay is grounded;
and the zone bit signal output end of the magnetic latching relay is connected with the zone bit signal detection end of the control module.
4. The power fail safe apparatus of claim 3, wherein the magnetic latching relay is a single coil magnetic latching relay comprising a first coil and a first switching device; wherein,
the first end of the first coil is the first end of the magnetic latching relay, and the second end of the first coil is the second end of the magnetic latching relay;
the fixed end of the first switching switch device is a zone bit signal output end of the magnetic latching relay, the first switching end of the first switching switch device is a third end of the magnetic latching relay, and the second switching end of the first switching switch device is a fourth end of the magnetic latching relay.
5. The power fail safe apparatus of claim 3, wherein the magnetic latching relay is a dual coil magnetic latching relay comprising an action coil, a reset coil and a second switching device; wherein,
the first end of the action coil is the first end of the magnetic latching relay, the first end of the reset coil is the second end of the magnetic latching relay, and the second end of the action coil and the second end of the reset coil are both grounded;
the fixed end of the second switching switch device is a zone bit signal output end of the magnetic latching relay, the first switching end of the second switching switch device is a third end of the magnetic latching relay, and the second switching end of the second switching switch device is a fourth end of the magnetic latching relay.
6. The power fail safe apparatus of any of claims 3 to 5, wherein the flag bit circuit further comprises a first resistor and a second resistor; wherein,
the first end of the first resistor is connected with the third end of the magnetic latching relay, and the second end of the first resistor is connected with the first power supply;
and the first end of the second resistor is connected with the fourth end of the magnetic latching relay, and the second end of the second resistor is grounded.
7. The power fail safe apparatus of claim 3, wherein the power fail detect module comprises a first transistor, a second transistor, a first diode, a first capacitor, a second capacitor, a third resistor, a fourth resistor, and a fifth resistor; wherein,
the first end of the first triode is connected with the first end of the third resistor, the second end of the first triode is connected with the first end of the first capacitor, and the third end of the first triode is grounded; the second end of the third resistor is used for connecting the power supply, and the second end of the first capacitor is grounded;
a first end of the first diode is connected with a first end of the first capacitor, and a second end of the first diode is used for connecting the power supply;
the first end of the second triode is connected with the first end of the fourth resistor, the second end of the second triode is connected with the first end of the fifth resistor, and the third end of the second triode is grounded;
a second end of the fourth resistor is connected with a third end of the first triode, and a second end of the fifth resistor is used for connecting a second power supply;
the first end of the second capacitor is connected with the second end of the fifth resistor, and the second end of the second capacitor is grounded;
and the second end of the second triode is the output end of the power failure detection module.
8. The power fail protection device of claim 7, wherein the power fail detection module comprises a second diode, a sixth resistor, and a seventh resistor; wherein,
the first end of the second diode is connected with the first end of the third resistor, and the second end of the second diode is grounded;
a first end of the sixth resistor is connected with a first end of the first triode, and a second end of the sixth resistor is connected with a first end of the third resistor;
and the first end of the seventh resistor is connected with the third end of the first triode, and the second end of the seventh resistor is grounded.
9. The power fail safe apparatus of claim 7, wherein the first transistor is a first PNP transistor and the second transistor is a second PNP transistor; wherein,
the base electrode of the first PNP type triode is the first end of the first triode, the emitter electrode of the first PNP type triode is the second end of the first triode, and the collector electrode of the first PNP type triode is the third end of the first triode;
the base electrode of the second PNP type triode is the first end of the second triode, the emitting electrode of the second PNP type triode is the second end of the second triode, and the collector electrode of the second PNP type triode is the third end of the second triode.
10. The power fail safe apparatus of claim 7, wherein the first terminal of the first diode is a cathode of the first diode and the second terminal of the first diode is an anode of the first diode.
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Application publication date: 20191220 |