CN110597555B - Nonvolatile memory computing chip and operation control method thereof - Google Patents
Nonvolatile memory computing chip and operation control method thereof Download PDFInfo
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Abstract
The invention provides a nonvolatile memory computing chip and an operation control method thereof, wherein the nonvolatile memory computing chip comprises: the cache module is used for caching data; the nonvolatile memory computing module is connected with the cache module and is used for executing operation on the data sent by the cache module; the post-processing module is connected with the nonvolatile memory computing module and is used for post-processing the operation result of the nonvolatile memory computing module; wherein the non-volatile memory computing module comprises: the nonvolatile memory comprises a nonvolatile memory cell array, a row and column decoder connected with the nonvolatile memory cell array, and a read-write circuit connected with the nonvolatile memory cell array. The nonvolatile memory computing chip is matched with the operation control method, the product accumulation operation and the binary neural network operation are realized based on the storage and computation integration technology, data do not need to be transmitted between the memory and the processor, and power consumption and time delay are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit application, in particular to a nonvolatile memory computing chip and an operation control method thereof.
Background
With the proposal of deep learning theory and the improvement of numerical computation equipment, the deep learning neural network technology is rapidly developed and is widely applied to the fields of computer vision, natural language processing and the like. At present, the neural network generally adopts floating point calculation, and requires a larger storage space and a longer operation time.
Binary Neural Network (BNN) is a Neural Network obtained by binarizing a weight value and each activation function value (eigenvalue) in a weight matrix of a floating-point Neural Network at the same time, that is, the Binary Neural Network is: the weight value and the activation function value are binarized to 1 or-1. Through binarization operation, the parameters of the model occupy smaller storage space (the memory consumption is reduced to 1/32 times in theory from floating point 32 bits to 1 bit), and bit operation is used for replacing multiply-add operation in the network, so that the operation time and power consumption are greatly reduced. Therefore, the binary neural network can solve the problems of overlarge model, overhigh calculation density and the like existing when the current floating-point neural network model is applied to an embedded or mobile scene (such as a mobile phone terminal, wearable equipment, an automatic driving automobile and the like), effectively reduces the occupation of storage space, reduces the operation time, and becomes a popular research direction for deep learning in recent years due to the potential advantages of high model compression ratio and high calculation speed.
However, although the binary neural network and the floating point neural network change phases, which can reduce the storage space occupation and reduce the operation time, the binary neural network still needs to transmit data between the memory and the processor, and frequent data movement still causes higher power consumption and time delay.
Disclosure of Invention
The invention provides a nonvolatile memory computing chip and an operation control method thereof, aiming at the problems in the prior art, and the nonvolatile memory computing chip and the operation control method thereof can at least partially solve the problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a non-volatile memory computing chip is provided, including:
the cache module is used for caching data;
the nonvolatile memory computing module is connected with the cache module and is used for executing operation on the data sent by the cache module;
the post-processing module is connected with the nonvolatile memory computing module and is used for post-processing the operation result of the nonvolatile memory computing module;
wherein the non-volatile memory computing module comprises: the nonvolatile memory comprises a nonvolatile memory cell array, a row and column decoder connected with the nonvolatile memory cell array, and a read-write circuit connected with the nonvolatile memory cell array.
Further, the cache module comprises: a first buffer unit and a second buffer unit,
the first cache unit is connected to the front end of the nonvolatile memory computing module and used for receiving and caching input data and characteristic diagram data;
the second cache unit is connected with the nonvolatile memory computing module and used for caching the weight data.
Further, the row-column decoder includes: a row decoder and a column decoder, the nonvolatile memory cell array comprising: a plurality of nonvolatile memory cells arranged in an array;
each row of nonvolatile memory units is connected with a row decoder through a bit line, each row of nonvolatile memory units is connected with the row decoder through a word line, and the bit line and the source line of each row of nonvolatile memory units are connected with the read-write circuit.
Further, the nonvolatile memory cell includes: a nonvolatile memory device and a three-terminal switching element connected in series;
one end of the nonvolatile memory device is connected with the bit line, the other end of the nonvolatile memory device is connected with the first end of the three-terminal switching element, the second end of the three-terminal switching element is connected with the word line, and the third end of the three-terminal switching element is connected with the source line.
Further, the row-column decoder includes: a row decoder and a column decoder, the nonvolatile memory cell array comprising: a plurality of nonvolatile memory cells arranged in an array;
each column of nonvolatile memory cells is connected with a column decoder through a bit line, each row of nonvolatile memory cells is connected with the row decoder through a source line, and the bit line and the source line of each row of nonvolatile memory cells are connected with the read-write circuit.
Further, the nonvolatile memory cell includes: a nonvolatile memory device and a two-terminal switching element connected in series;
one end of a serial branch formed by the nonvolatile memory device and the two-end switching element is connected with the bit line, and the other end of the serial branch is connected with the source line.
Further, still include: and the amplifier is connected with each bit line and used for comparing the total analog current/voltage on each bit line with the reference information and outputting the operation result of the nonvolatile memory calculation module.
Further, still include: and the counter is connected with the read-write circuit, and the output of the counter is used as the operation result of the nonvolatile memory calculation module.
Further, the nonvolatile memory unit is a resistance change memory unit, a phase change memory unit, a ferroelectric memory unit and a spin memory unit.
In a second aspect, a control method for implementing a multiply-accumulate operation based on a non-volatile memory calculation is provided, including:
storing a first binary operation signal into a row of non-volatile memory cells, each non-volatile memory cell storing a bit of the first binary operation signal;
loading a second binary operation signal to the row of nonvolatile memory cells, wherein corresponding bits of the first binary operation signal and the second binary operation signal when performing product accumulation operation are applied to the same nonvolatile memory cell;
loading an exclusive nor operation instruction to the row of nonvolatile memory cells to enable the row of nonvolatile memory cells to respond to the exclusive nor operation instruction to execute exclusive nor operation of corresponding bits of the first binary operation signal and the second binary operation signal, and storing an operation result in the corresponding nonvolatile memory cells;
and reading the data in each nonvolatile memory cell in the row of nonvolatile memory cells and accumulating to obtain the product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.
In a third aspect, a control method for implementing a binary neural network operation based on a nonvolatile memory calculation is provided, including:
storing at least one binary weight signal in at least one row of non-volatile memory cells, each non-volatile memory cell storing one bit of the binary weight signal;
loading the characteristic signal to the row of nonvolatile memory cells, and applying corresponding bits of the binary weight signal and the characteristic signal when the binary weight signal and the characteristic signal execute product accumulation operation to the same nonvolatile memory cells;
loading an exclusive nor operation instruction to the row of nonvolatile memory cells, so that the row of nonvolatile memory cells execute exclusive nor operation of the binary weight signal and the corresponding bit of the characteristic signal in response to the exclusive nor operation instruction, and storing an operation result in the corresponding nonvolatile memory cells;
and reading the data in each nonvolatile memory cell in the row of nonvolatile memory cells and accumulating to obtain the product accumulation operation result of the binary weight signal and each bit of the characteristic signal.
Further, still include:
and buffering the result of the product accumulation operation as a characteristic signal of the next layer.
Further, still include:
and post-processing the product accumulation operation result to obtain a binary neural network operation result.
The embodiment of the invention provides a nonvolatile memory computing chip and an operation control method thereof, wherein the nonvolatile memory computing chip comprises: the cache module is used for caching data; the nonvolatile memory computing module is connected with the cache module and is used for executing operation on the data sent by the cache module; the post-processing module is connected with the nonvolatile memory computing module and is used for post-processing the operation result of the nonvolatile memory computing module; wherein the non-volatile memory computing module comprises: the nonvolatile memory comprises a nonvolatile memory cell array, a row and column decoder connected with the nonvolatile memory cell array, and a read-write circuit connected with the nonvolatile memory cell array. The nonvolatile memory computing chip is matched with the operation control method, the product accumulation operation and the binary neural network operation are realized based on the storage and computation integration technology, data do not need to be transmitted between the memory and the processor, and power consumption and time delay are reduced.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. In the drawings:
FIG. 1 is a block diagram of a non-volatile memory computing chip according to an embodiment of the present invention;
FIG. 2 illustrates the structure of the non-volatile memory computing module 20 of FIG. 1;
FIG. 3 is a block diagram of a non-volatile memory computing chip according to an embodiment of the present invention;
FIG. 4 shows one configuration of the non-volatile memory cell of FIG. 2;
FIG. 5 shows a structure based on the nonvolatile memory cell array shown in FIG. 4;
FIG. 6a shows another structure of the non-volatile memory cell of FIG. 2;
FIG. 6b shows a third structure of the non-volatile memory cell of FIG. 2;
FIG. 7 shows another structure based on the array of non-volatile memory cells shown in FIG. 6 b;
8 a-8 c illustrate the operation logic of three non-volatile memory cells provided by embodiments of the present invention;
FIG. 9 illustrates a truth table for implementing an exclusive OR or XOR operation using the logic illustrated in FIGS. 8 a-8 c;
FIG. 10a shows a circuit configuration for implementing an exclusive OR or an exclusive OR operation using the nonvolatile memory cell array of FIG. 5;
FIG. 10b illustrates another circuit configuration for implementing an exclusive OR or XOR operation using the array of nonvolatile memory cells of FIG. 5;
FIG. 11a illustrates a circuit configuration for implementing an exclusive OR or an exclusive OR operation using the nonvolatile memory cell array of FIG. 7;
FIG. 11b illustrates another circuit configuration for performing an exclusive OR or XOR operation using the array of nonvolatile memory cells of FIG. 7;
FIG. 12 shows a specific structure of the post-processing module 30 in FIG. 1;
FIG. 13 is a first flowchart illustrating a method for controlling a multiply-accumulate operation based on non-volatile memory operations according to an embodiment of the present invention;
FIG. 14 is a flowchart illustrating a second method for controlling a multiply-accumulate operation based on non-volatile memory operations according to an embodiment of the present invention;
fig. 15 is a flowchart illustrating a control method for implementing a binary neural network operation based on a nonvolatile memory calculation according to an embodiment of the present invention.
Figure 16 illustrates a neural network operational architecture.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for anyone skilled in the art to understand the technical content of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art from the disclosure, the claims and the drawings of the present specification. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the invention in any way.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
At present, although the binary neural network and the floating-point neural network change phases, which can reduce the storage space occupation and reduce the operation time, the binary neural network still needs to transmit data between a memory and a processor, and frequent data movement still causes higher power consumption and time delay.
In order to at least partially solve the above technical problems in the prior art, embodiments of the present invention provide a nonvolatile memory computing chip, which can integrate the stored data into a same chip, and implement a product accumulation operation and a binary neural network operation based on a storage and computation integration technique, so as to directly use a memory to perform the computation, reduce data transmission between the memory and a processor, and reduce power consumption and time delay.
Fig. 1 is a first block diagram of a non-volatile memory computing chip according to an embodiment of the present invention. As shown in fig. 1, the nonvolatile memory computing chip includes: a cache module 10, a non-volatile memory computing module 20 and a post-processing module 30.
The cache module 10 is configured to receive input data and cache the data, and may also be configured to output the data, where the cached data may be the input data, or may also be an intermediate operation result of the nonvolatile memory calculation module 20 or a calculation result output by the post-processing module, and the like, for example: input data, weight data, feature map data, and the like.
In particular, the cache module 10 may be implemented using SRAM or MRAM.
The nonvolatile memory computing module 20 is connected to the cache module, and is configured to perform operations on the data sent by the cache module.
The nonvolatile memory computation module 20 may store data, or may implement and logic operation, or logic operation, xor logic operation, and or logic operation, multiply-add-accumulate (MAC), and the like based on nonvolatile characteristics.
A Post-processing Engine (Post-processing Engine)30 is connected to the non-volatile memory computing module, and is configured to perform Post-processing on an operation result of the non-volatile memory computing module.
Specifically, the post-processing may include: pooling (Pooling), Batch Normalization (Batch Normalization), shifting, biasing, averaging, taking the maximum and minimum values, activating functions, and the like.
The nonvolatile memory computing module 20 includes: the nonvolatile memory device comprises a nonvolatile memory cell array 21, a row and column decoder 23 connected with the nonvolatile memory cell array, a read-write circuit 22 connected with the nonvolatile memory cell array, and a MAC peripheral circuit 24 (such as a counter, an amplifier and the like) connected with the nonvolatile memory cell array 21, as shown in FIG. 2.
Specifically, the nonvolatile memory cell array 21 may be RRAM, PCRAM, MRAM, or the like.
It should be noted that, in the nonvolatile memory computing chip provided in the embodiment of the present invention, the cache module is adopted to receive or cache data, and the nonvolatile memory computing module 20 is controlled to enable the nonvolatile memory computing module 20 to perform a logic operation on data to be computed, and after an operation result is processed by the post-processing module 30, the operation result is sent to the cache module for output or continuously participates in a next round of operation, so that operation processes such as product accumulation operation or binary neural network operation can be implemented based on a memory and computation integration technology, data does not need to be transmitted between the memory and the processor, and power consumption and time delay are reduced.
In an alternative embodiment, referring to fig. 3, the cache module 10 may include: a first buffer unit 11 and a second buffer unit 12.
The first cache unit 11 is connected to the front end of the nonvolatile memory computing module 20, and is configured to receive and cache input data and feature map data; the second cache unit 12 is connected to the nonvolatile memory computing module and is configured to cache the weight data.
The two cache units are arranged to cache different data respectively, so that the data cache reading speed can be increased, and the flexibility of the nonvolatile memory computing chip is improved.
In an optional embodiment, the cache module 20 may further be connected to a nonvolatile off-chip memory (which may be a conventional Flash, a hard disk, or a novel nonvolatile memory RRAM, MRAM, PCRAM), so as to improve the capacity and access speed of the off-chip memory, and prevent the problem that the cache data seriously overflows to affect the operation during large-scale operation.
In an alternative embodiment, the row column decoder comprises: a row decoder and a column decoder, the non-volatile memory cell array comprising: a plurality of nonvolatile memory cells arranged in an array; each row of nonvolatile memory units is connected with the row decoder through a bit line BL, each row of nonvolatile memory units is connected with the row decoder through a word line WL, and the bit line BL and the source line SL of each row of nonvolatile memory units are connected with the read-write circuit.
In a further embodiment, the non-volatile memory cell comprises: a nonvolatile memory device R and a three-terminal switching element T1 (1T 1R structure for short) connected in series, see fig. 4;
one end of the nonvolatile memory device R is connected to the bit line BL, the other end is connected to the first end of the three-terminal switching element T1, the second end of the three-terminal switching element T1 is connected to the word line WL, the third end of the three-terminal switching element T1 is connected to the source line SL, and the structure of the nonvolatile memory cell array formed by the arrangement of the nonvolatile memory cell array is shown in fig. 5.
The switching element can be implemented by a PMOS transistor or an NMOS transistor, the first terminal can be a drain of the MOS transistor, the second terminal can be a gate of the MOS transistor, and the third terminal can be a source of the MOS transistor.
Of course, the first terminal of the transistor provided in the embodiment of the present invention may be a source, and the third terminal is a drain.
In another alternative embodiment, the row-column decoder includes: a row decoder and a column decoder, the nonvolatile memory cell array including: a plurality of nonvolatile memory cells arranged in an array;
each column of nonvolatile memory cells is connected with a column decoder through a bit line, each row of nonvolatile memory cells is connected with the row decoder through a source line, and the bit line and the source line of each row of nonvolatile memory cells are connected with the read-write circuit.
In a further embodiment, the non-volatile memory cell comprises: a series connection of a non-volatile memory device R and a two-terminal switching element T2 or T3 (also called 1T1R configuration), see fig. 6a and 6 b;
one end of a series branch formed by the nonvolatile memory device and the two-terminal switching element is connected to the bit line BL, and the other end thereof is connected to the source line SL. The structure of a nonvolatile memory cell array (cross point array for short) formed by the nonvolatile memory cell array arrangement is shown in fig. 7.
In the 1T1R cell structure, the state of the nonvolatile memory device (usually two states, a low resistance state representing logic 0 and a high resistance state representing logic 1, or vice versa) depends on the voltage difference between the bit line BL and the source line SL (note: high voltage represents 1 and low voltage represents 0), when the voltage difference between the bit line BL and the source line SL exceeds a certain threshold, the state of the nonvolatile memory device is inverted (no matter what state is currently the state), and when the voltage between the bit line BL and the source line SL does not exceed the threshold, the state of the nonvolatile memory device is maintained in the initial state, such as a unidirectional RRAM device, an electric field modulation MRAM device, and the like. Based on this principle, the inventor has found through a great deal of research and analysis that the exclusive nor operation XNOR can be realized by using the above-mentioned 1T1R structure. As shown in fig. 8a, 8b, and 8C, when the voltage on BL is the input operand a, the voltage on SL is the input operand C, and the data currently stored in the nonvolatile memory device is the operand Bi, a truth table can be obtained, and referring to fig. 9, it can be seen that when C is 0, Bi and a perform an exclusive or (XOR) operation, but when C is 1, Bi and a perform an exclusive or (XNOR) operation.
Through extensive research by the inventors, the process of MAC operation on two vectors is equivalent to the accumulation of exclusive nor operations (XNOR) on each element of two items, for example, sequences a ═ 0101 and B ═ 1011, a × B ═ a1 × B1+ a2 × B2+ a3 × B3+ a4 × B4 ═ a1 ≥ B1+ a2 ≥ B2+ a3 ≥ B3+ a4 ≥ B4 ═ 1. Wherein a sign of XNOR is ═ XOR, and XNOR ═ XOR (exclusive or operation behavior) is inverted.
Based on the above principle, for the nonvolatile memory cell arrays shown in fig. 5 and 7, by adding peripheral circuits, an XNOR operation of two vectors can be realized.
Fig. 10a shows a circuit configuration for implementing an exclusive or exclusive or operation using the nonvolatile memory cell array shown in fig. 5. As shown in fig. 10a, each bit line is connected to an amplifier (corresponding to a read/write unit of the read/write circuit), an output terminal of each amplifier is connected to a counter, the counter counts data representing 1 in the read data, and the counted result is an operation result of the nonvolatile memory calculation module.
The operation data B may be { B ═ B1,b2,…,bMStoring the data (for neural network operation, B is equivalent to weight data of a certain layer, for convolutional neural network operation, B is equivalent to convolutional kernel data) in a certain row of nonvolatile memory cells (realized by matching a read-write circuit with a row-column decoder and controlling the voltage difference between a bit line and a source line), and storing the representation A ═ a1,a2,…,aMLoading the same or operation instruction {1,1, …,1} on the source line of the nonvolatile memory cell, when all the bit lines are high, under the action of A, executing XNOR operation in each cell, corresponding to each row, executing XNOR operation of A and B, finally, by gating different WL, reading the state of each row of cell 1 and accumulating through the counter, namely realizing MAC operation.
It will be understood by those skilled in the art that the MAC operation may also be implemented by loading an XOR operation {0,0, …,0} on the source line of the non-volatile memory cell, performing an XOR operation in each cell under a, performing an XOR operation of a and B for each row, and finally, by gating a different WL, reading the state of each row of cells 0 and accumulating through a counter.
FIG. 10b illustrates another circuit configuration for implementing an exclusive OR or XOR operation using the array of nonvolatile memory cells of FIG. 5; as shown in fig. 10b, an amplifier is connected to each bit line for comparing the total analog current/voltage on each bit line with the reference information and outputting the operation result of the non-volatile memory computing module.
The operation data B may be { B ═ B1,b2,…,bMStoring the data (for neural network operation, B is equivalent to weight data of a certain layer, for convolutional neural network operation, B is equivalent to convolutional kernel data) in a certain row of nonvolatile memory cells (realized by matching a read-write circuit with a row-column decoder and controlling the voltage difference between a bit line and a source line), and storing the representation A ═ a1,a2,…,aMLoading a signal of the row of nonvolatile memory cells on a bit line, loading an exclusive nor operation instruction {1,1, …,1} on a source line of the nonvolatile memory cells, when all the bit lines are high, performing an XNOR operation in each cell under the action of a, performing XNOR operations of a and B corresponding to each row, comparing the total analog current/voltage of all the cells with a reference signal through an amplifier in a manner of reading the total analog current/voltage of all the cells, and taking the comparison result as a MAC operation result.
Fig. 11a shows a circuit configuration for implementing an exclusive or exclusive or operation using the nonvolatile memory cell array shown in fig. 7. Fig. 11b shows another circuit configuration for implementing an exclusive or exclusive or operation using the nonvolatile memory cell array shown in fig. 7. The operation principle and circuit description refer to fig. 10a and 10b, which are not repeated herein.
Fig. 12 shows a specific structure of the post-processing module 30 in fig. 1. Referring to fig. 12, the post-processing module 30 includes a plurality of PE channels, each implementing a post-processing function configured by different budgets, and the PE channel 1 includes: nonlinear function + pooling + batch normalization + activation function. Different PE channels are assembled and realized by different operations according to a required sequence.
It should be noted that the post-processing module is a common technique in the art and is not described herein again.
It is to be noted that the nonvolatile memory cell used in the embodiment of the present invention is preferably a resistance change memory cell, a phase change memory cell, a ferroelectric memory cell, a spin memory cell, or the like.
The nonvolatile memory computing chip can also comprise a controller for controlling the state and the time sequence of the whole chip.
FIG. 13 is a first flowchart illustrating a method for controlling a multiply-accumulate operation based on non-volatile memory operations according to an embodiment of the present invention; as shown in fig. 13, the control method for implementing the multiply-accumulate operation based on the non-volatile memory computing may be used to control the non-volatile memory computing chip to implement the multiply-accumulate operation.
The control method for realizing the multiply-accumulate operation based on the nonvolatile memory calculation can comprise the following steps:
step S100: the first binary operation signal is stored in a row of non-volatile memory cells.
Wherein each non-volatile memory cell stores one bit of the first binary operation signal.
Specifically, the voltage difference on the bit line and the source line of the nonvolatile memory unit is controlled to write each binary bit into one nonvolatile memory unit through the cooperation of the row and column decoder and the read-write circuit.
It is worth pointing out that the first binary operation signal represents the first binary operation data.
Step S200: the second binary operation signal is loaded to the row of non-volatile memory cells.
Corresponding bits of the first binary operation signal and the second binary operation signal when the product accumulation operation is executed are applied to the same nonvolatile memory unit;
specifically, the bit lines of the corresponding memory cells of the nonvolatile memory cells in the row are configured according to the second binary operation signal through the cooperation of the row-column decoder and the read-write circuit.
It is worth mentioning that the second binary operation signal represents the second binary operation data.
Step S300: and loading an exclusive OR operation instruction to the row of nonvolatile memory units so that the row of nonvolatile memory units respond to the exclusive OR operation instruction to execute exclusive OR operation of corresponding bits of the first binary operation signal and the second binary operation signal, and storing an operation result in the corresponding nonvolatile memory units.
The exclusive-nor operation instruction can be set to be all 1 or all 0, and the exclusive-or operation instruction is configured according to the circuit condition, and is opposite to the exclusive-nor operation instruction.
Specifically, the row of nonvolatile memory cells are configured according to the exclusive nor operation instruction through the cooperation of the row and column decoder and the read-write circuit.
Step S400: and reading the data in each nonvolatile memory cell in the row of nonvolatile memory cells and accumulating to obtain the product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.
Specifically, the data in each nonvolatile memory cell in the row of nonvolatile memory cells may be read through the cooperation of the row-column decoder and the read-write circuit, and the MAC operation may be implemented by counting a certain specific state of each read nonvolatile memory cell in the row through the counter, and referring to fig. 10a and 11a, first, the data in each nonvolatile memory cell in the row of nonvolatile memory cells is read; then, counting data representing 1 in the read data; and finally, taking the counting result as a product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.
Or, by reading the total analog current/voltage of all the cells, comparing the total analog current/voltage of all the cells with the reference signal through the amplifier, and taking the comparison result as the MAC operation result, referring to fig. 10b and 11b, first, reading the total analog current/voltage of all the nonvolatile memory cells in the row of nonvolatile memory cells; then, comparing the total analog current/voltage with a first reference signal; and finally, taking the comparison result as a product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.
According to the technical scheme, the control method can be adopted to control the calculation based on the nonvolatile memory to realize the product accumulation operation, data do not need to be transmitted between the memory and the processor, and the power consumption and the time delay are reduced.
FIG. 14 is a flowchart illustrating a second method for controlling a multiply-accumulate operation based on non-volatile memory operations according to an embodiment of the present invention; as shown in fig. 14, the control method for implementing the multiply-accumulate operation based on the non-volatile memory computing may be used to control the non-volatile memory computing chip to implement the multiply-accumulate operation.
The control method for implementing the multiply-accumulate operation based on the non-volatile memory calculation shown in fig. 14 is the same as the control method shown in fig. 13, except that the exclusive-or operation instruction is loaded to the row of the non-volatile memory cells in step S300', and the data representing 0 in the read data is counted when the operation result is read by using the principle that the exclusive-or operation is the inverse of the exclusive-or operation; and finally, taking the counting result as a product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal.
Or, by reading the total analog current/voltage of all the units, comparing the total analog current/voltage of all the units with the reference signal through the amplifier, and taking the comparison result as the MAC operation result, the adopted reference signal is different from the reference signal adopted when performing the exclusive nor operation, and other principles are the same as those when adopting the exclusive nor operation, and are not described herein again.
Fig. 15 is a flowchart illustrating a control method for implementing a binary neural network operation based on a nonvolatile memory calculation according to an embodiment of the present invention. As shown in fig. 15, the control method for implementing the binary neural network operation based on the nonvolatile memory computing may include the following steps:
step S1000: storing at least one binary weight signal (corresponding to Bi) in at least one row of non-volatile memory cells;
it is worth mentioning that, referring to fig. 16, the neural network operation includes a plurality of layers, each layer being configured to perform a MAC operation on input data and weight data, and to take the operation result as an input of the next layer.
Wherein one bit of the binary weight signal is stored in each non-volatile memory cell.
Specifically, the voltage difference on the bit line and the source line of the nonvolatile memory unit is controlled to write each binary bit into one nonvolatile memory unit through the cooperation of the row and column decoder and the read-write circuit.
In addition, for the convolutional neural network, one layer may correspond to a plurality of convolutional kernels, and at this time, data corresponding to each convolutional kernel is taken as one weight data, and the weight data corresponding to the convolutional kernels are written into the plurality of rows of nonvolatile memory cells, so that operations corresponding to the convolutional kernels can be simultaneously realized.
Step S2000: a characteristic signal (corresponding to a) is loaded into the row of non-volatile memory cells.
Corresponding bits when the binary weight signal and the characteristic signal execute the product accumulation operation are applied to the same nonvolatile memory cell;
specifically, the bit lines of the corresponding memory cells of the nonvolatile memory cells in the row are configured according to the characteristic signals through the cooperation of the row and column decoders and the read-write circuits.
Step S3000: loading an exclusive OR operation instruction to the row of nonvolatile memory cells, so that the row of nonvolatile memory cells execute exclusive OR operation of the binary weight signal and the corresponding bit of the characteristic signal in response to the exclusive OR operation instruction, and storing an operation result in the corresponding nonvolatile memory cells;
the exclusive-nor operation instruction can be set to be all 1 or all 0, and the exclusive-or operation instruction is configured according to the circuit condition, and is opposite to the exclusive-nor operation instruction.
Specifically, the row of nonvolatile memory cells are configured according to the exclusive nor operation instruction through the cooperation of the row and column decoder and the read-write circuit.
Step S4000: and reading the data in each nonvolatile memory cell in the row of nonvolatile memory cells and accumulating to obtain the product accumulation operation result of the binary weight signal and each bit of the characteristic signal.
Specifically, the data in each nonvolatile memory cell in the row of nonvolatile memory cells may be read through the cooperation of the row-column decoder and the read-write circuit, and the MAC operation may be implemented by counting a certain state of each nonvolatile memory cell in the row through a counter, and referring to fig. 10a and 11a, first, the data in each nonvolatile memory cell in the row of nonvolatile memory cells is read; then, counting data representing 1 in the read data; and finally, taking the counting result as a product accumulation operation result of each bit of the weight signal and the characteristic signal.
Or, by reading the total analog current/voltage of all the cells, comparing the total analog current/voltage of all the cells with the reference signal through the amplifier, and taking the comparison result as the MAC operation result, referring to fig. 10b and 11b, first, reading the total analog current/voltage of all the nonvolatile memory cells in the row of nonvolatile memory cells; then, comparing the total analog current/voltage with a first reference signal; and finally, taking the comparison result as a product accumulation operation result of each bit of the weight signal and the characteristic signal.
It is to be noted that, assuming that the weight data itself is stored in the nonvolatile memory cell array, it is first necessary to store the weight data BiRead out to the cache module (because in the operation process, the operation result Bi+1Stored in the current cell, meaning the initial weight data BiWill be corrupted and therefore it will be necessary to put B into operation when performing MAC operationsiCopying to a cache module, and writing back after execution is finished);
in addition, if the weight data is stored in the off-chip memory, the weight data is first imported into the nonvolatile memory cell array.
According to the technical scheme, the control method can be adopted to control the nonvolatile memory-based calculation to realize the neural network operation, particularly the convolutional neural network operation, the effect is better and obvious, data do not need to be transmitted between the memory and the processor, and the power consumption and the time delay are reduced.
In an optional embodiment, the control method for implementing the binary neural network operation based on the nonvolatile memory computing may further include:
and caching the product accumulation operation result as a characteristic signal of the next layer.
Specifically, the result of the multiply-accumulate operation is buffered in a buffer module for subsequent use.
In an optional embodiment, the control method for implementing the binary neural network operation based on the nonvolatile memory computing may further include:
and post-processing the product accumulation operation result to obtain a binary neural network operation result.
Specifically, the post-processing may include: pooling (Pooling), Batch Normalization (Batch Normalization), shifting, biasing, averaging, taking the maximum and minimum values, activating functions, and the like.
It can be understood by those skilled in the art that, for the control method for implementing the binary neural network operation based on the nonvolatile memory calculation, an exclusive-or operation instruction may be used instead of the exclusive-or operation instruction, because the results of the exclusive-or operation and the exclusive-or operation are mutually returned, if the number of 1 s in the storage unit is counted when the exclusive-or operation is used, the number of 0 s in the storage unit is counted when the exclusive-or operation is used, and the principle is the same as that of the method described above, and is not described herein again.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but may be embodied or carried out by various modifications, equivalents and changes without departing from the spirit and scope of the invention.
Claims (13)
1. A non-volatile memory computing chip, comprising:
the cache module is used for caching data;
the nonvolatile memory computing module is connected with the cache module and is used for executing operation on the data sent by the cache module;
the post-processing module is connected with the nonvolatile memory computing module and is used for post-processing the operation result of the nonvolatile memory computing module;
wherein the non-volatile memory computing module comprises: the nonvolatile memory comprises a nonvolatile memory cell array, a row and column decoder connected with the nonvolatile memory cell array, and a read-write circuit connected with the nonvolatile memory cell array;
each bit line of the nonvolatile memory computing module is connected with an amplifier, the output end of each amplifier is connected with a counter, the counter counts data which represents 1 in the read data, and the counting result is used as the operation result of the nonvolatile memory computing module; or
And comparing the total analog current/voltage on each bit line with reference information, and outputting the operation result of the nonvolatile memory calculation module.
2. The non-volatile in-memory computing chip of claim 1, wherein the cache module comprises: a first buffer unit and a second buffer unit,
the first cache unit is connected to the front end of the nonvolatile memory computing module and used for receiving and caching input data and characteristic diagram data;
the second cache unit is connected with the nonvolatile memory computing module and used for caching the weight data.
3. The non-volatile in-memory computing chip of claim 1, wherein the row-column decoder comprises: a row decoder and a column decoder, the non-volatile memory cell array comprising: a plurality of nonvolatile memory cells arranged in an array;
each row of nonvolatile memory units is connected with a row decoder through a bit line, each row of nonvolatile memory units is connected with the row decoder through a word line, and the bit line and the source line of each row of nonvolatile memory units are connected with the read-write circuit.
4. The non-volatile in-memory computing chip of claim 3, wherein the non-volatile storage unit comprises: a nonvolatile memory device and a three-terminal switching element connected in series;
one end of the nonvolatile memory device is connected with the bit line, the other end of the nonvolatile memory device is connected with the first end of the three-terminal switching element, the second end of the three-terminal switching element is connected with the word line, and the third end of the three-terminal switching element is connected with the source line.
5. The non-volatile in-memory computing chip of claim 1, wherein the row-column decoder comprises: a row decoder and a column decoder, the non-volatile memory cell array comprising: a plurality of nonvolatile memory cells arranged in an array;
each column of nonvolatile memory cells is connected with a column decoder through a bit line, each row of nonvolatile memory cells is connected with the row decoder through a source line, and the bit line and the source line of each row of nonvolatile memory cells are connected with the read-write circuit.
6. The non-volatile in-memory computing chip of claim 5, wherein the non-volatile storage unit comprises: a nonvolatile memory device and a two-terminal switching element connected in series;
one end of a series branch formed by the nonvolatile memory device and the two-terminal switching element is connected to the bit line, and the other end is connected to the source line.
7. The non-volatile in-memory computing chip of any of claims 3 or 5, further comprising: and the amplifier is connected with each bit line and used for comparing the total analog current/voltage on each bit line with the reference information and outputting the operation result of the nonvolatile memory calculation module.
8. The non-volatile in-memory computing chip of any of claims 3 or 5, further comprising: and the counter is connected with the read-write circuit, and the output of the counter is used as the operation result of the nonvolatile memory calculation module.
9. The non-volatile memory computing chip of any one of claims 4 or 6, wherein the non-volatile memory unit is a resistive memory unit, a phase change memory unit, a ferroelectric memory unit, a spin memory unit.
10. A control method for realizing product accumulation operation based on nonvolatile memory calculation is characterized by comprising the following steps:
storing a first binary operation signal in a row of non-volatile memory cells, each non-volatile memory cell storing a bit of the first binary operation signal;
loading a second binary operation signal to the row of nonvolatile memory cells, wherein corresponding bits of the first binary operation signal and the second binary operation signal when performing product accumulation operation are applied to the same nonvolatile memory cell;
loading an exclusive-nor operation instruction to the row of nonvolatile memory cells, so that the row of nonvolatile memory cells execute exclusive-nor operation of corresponding bits of the first binary operation signal and the second binary operation signal in response to the exclusive-nor operation instruction, and storing an operation result in the corresponding nonvolatile memory cells;
reading and accumulating data in each nonvolatile memory cell in the row of nonvolatile memory cells to obtain a product accumulation operation result of each bit of the first binary operation signal and the second binary operation signal;
wherein the non-volatile memory unit is located in a non-volatile memory computing module; each bit line of the nonvolatile memory computing module is connected with an amplifier, the output end of each amplifier is connected with a counter, the counter counts data which represents 1 in the read data, and the counting result is used as the operation result of the nonvolatile memory computing module; or
And comparing the total analog current/voltage on each bit line with reference information, and outputting the operation result of the nonvolatile memory calculation module.
11. A control method for realizing binary neural network operation based on nonvolatile memory calculation is characterized by comprising the following steps:
storing at least one binary weight signal in at least one row of non-volatile memory cells, each non-volatile memory cell storing one bit of the binary weight signal;
loading the characteristic signal to the row of nonvolatile memory cells, and applying corresponding bits of the binary weight signal and the characteristic signal when the binary weight signal and the characteristic signal execute product accumulation operation to the same nonvolatile memory cells;
loading an exclusive OR operation instruction to the row of nonvolatile memory cells, so that the row of nonvolatile memory cells execute exclusive OR operation of the binary weight signal and the corresponding bit of the characteristic signal in response to the exclusive OR operation instruction, and storing an operation result in the corresponding nonvolatile memory cells;
reading and accumulating data in each nonvolatile memory cell in the row of nonvolatile memory cells to obtain a product accumulation operation result of each bit of the binary weight signal and the characteristic signal;
wherein the non-volatile memory unit is located in a non-volatile memory computing module; each bit line of the nonvolatile memory computing module is connected with an amplifier, the output end of each amplifier is connected with a counter, the counter counts data which represents 1 in the read data, and the counting result is used as the operation result of the nonvolatile memory computing module; or
And comparing the total analog current/voltage on each bit line with reference information, and outputting the operation result of the nonvolatile memory calculation module.
12. The control method for implementing a binary neural network operation based on non-volatile memory computing according to claim 11, further comprising:
and caching the product accumulation operation result as a characteristic signal of the next layer.
13. The control method for implementing a binary neural network operation based on non-volatile memory computing according to claim 11, further comprising:
and post-processing the product accumulation operation result to obtain a binary neural network operation result.
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