CN110581178A - diode surge voltage suppressor chip and manufacturing method thereof - Google Patents
diode surge voltage suppressor chip and manufacturing method thereof Download PDFInfo
- Publication number
- CN110581178A CN110581178A CN201810594567.4A CN201810594567A CN110581178A CN 110581178 A CN110581178 A CN 110581178A CN 201810594567 A CN201810594567 A CN 201810594567A CN 110581178 A CN110581178 A CN 110581178A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- electrode
- type
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000000206 photolithography Methods 0.000 claims description 16
- 230000001678 irradiating effect Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000000295 complement effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 230000002441 reversible effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
the invention relates to a surge voltage suppressor, in particular to a diode surge voltage suppressor chip and a manufacturing method thereof. The chip is of an NPN structure, N-type impurities are diffused and distributed on the front surface and the back surface of the P-type substrate, electrode metal covers electrode areas of the N-type impurities, oxide layers cover other areas of the N-type impurities, and the thickness of the chip is 170-240 mu m. The diode surge voltage suppressor chip is bipolar or unipolar, and the bipolar positive and negative electrode areas are covered with negative electrode metal; the electrode area of the front side of the single polarity is covered with negative electrode metal, and the whole back side of the single polarity is the electrode area and is covered with positive electrode metal. The diode surge voltage suppressor chip of the invention uses a P-type primary silicon wafer with better current gain control to be thinned to a certain thickness. The original silicon wafer is subjected to double-sided diffusion N-type doping, the depth of a PN junction is controlled through complementary diffusion so as to further control the negative resistance characteristic of the chip, and when the chip meets surge voltage, the power borne by the element is reduced due to the characteristic that breakdown voltage carries negative resistance, so that the chip is more resistant to high current.
Description
Technical Field
the present invention relates to a surge voltage Suppressor (TVS), and more particularly, to a diode surge voltage Suppressor chip and a method for manufacturing the same.
background
surge suppressors are important components for circuit protection, especially for circuits formed by MOSFET (metal oxide semiconductor field effect transistor) transistors. The gate of the MOSFET is broken down to lose the insulation effect and the circuit fails because of the surge voltage (transient voltage) that is easily generated by the power supply voltage and signal voltage outside the circuit due to lightning or other reasons, or the high-voltage static electricity carried by the human body, tools, etc. Therefore, the input end of the integrated circuit needs to be provided with a surge voltage suppressor, so that the transient surge can be short-circuited from the bypass of the surge voltage suppressor when the transient surge is larger than a certain range, and the signal transmission is not influenced.
there are many conventional surge voltage protection devices, such as capacitors, which temporarily charge a capacitor with a surge voltage, such as a short-circuit ground; if the reverse bias of the diode is used, the diode is conducted when the breakdown voltage is reached, and the surge exceeding a certain voltage value is conducted to the ground; further, for example, a MOSFET is used to connect the gate to the source and then to the input terminal and to ground the drain, thereby effectively suppressing the surge.
as shown in fig. 1, a conventional diode surge suppressor 102 is mainly made of an N-type or P-type silicon substrate (P-type in this example) 104, and its doping concentration depends on the surge voltage to be protected, and is selected to be equal to the reverse breakdown voltage of the PN junction under a specific protection surge voltage, and is high when the protection voltage is low, and is low when the protection voltage is low. Then, a layer of N-type doping is diffused to form a PN junction 106, a protective oxide layer 108 is formed, an alloy is plated to form a positive electrode 110, and the positive electrode is cut into single chips and then packaged on a protected circuit.
the diode surge voltage suppressor utilizes the clamping voltage thereof to protect a back-end equipment system, but the chip with the structure has the following defects: when the surge voltage passes through the element, the clamping voltage of the element is higher, and the power borne by the element is larger, as shown in fig. 2, a P region in an NPN structure of the surge suppressor is longer, and after the surge suppressor is turned on, the current passes through the longer P-type region; the current gain effect of the NPN structure is not obvious, so that the clamping voltage is high, the PN junction is overheated, the clamping voltage does not have a negative resistance characteristic, so that the power borne by the element under the impact current is large, and the excessive power easily causes the suppressor chip to be burned out prematurely, so that the circuit is not protected.
disclosure of Invention
In view of the above disadvantages, the diode surge voltage suppressor chip and the manufacturing method thereof of the present invention can eliminate the above disadvantages, so that the surge voltage suppressor can bear a larger surge current and will not be burnt out in advance.
The technical scheme of the invention is as follows:
a diode surge voltage suppressor chip is of an NPN structure, N-type impurities are diffused and distributed on the front surface and the back surface of a P-type substrate, electrode metal covers electrode areas of the N-type impurities, oxide layers cover other areas of the N-type impurities, and the thickness of the chip is 170-240 mu m.
the diode surge voltage suppressor chip is bipolar, and the electrode areas of the front surface and the back surface are covered with negative electrode metal.
The diode surge voltage suppressor chip is unipolar, the electrode area of the front side is covered with negative electrode metal, and the whole reverse side is the electrode area and is covered with positive electrode metal.
the doping concentration of the P-type substrate is determined by the voltage value of the surge voltage, and the doping concentration is low when the voltage value is high and the doping concentration is high when the voltage value is low.
the chip is used for circuit protection formed by the metal oxide semiconductor field effect transistor.
a manufacturing method of a bipolar diode surge voltage suppressor chip comprises the following steps:
Step 1: taking a silicon wafer as a substrate, wherein the substrate is of a P type;
Step 2: thinning the substrate to a thickness of 150-200 μm;
and step 3: thermally growing an oxide layer on the front surface and the back surface of the substrate respectively;
And 4, step 4: irradiating the surface of the substrate with first light, and exposing by lithography to obtain a diffusion region and a scribe line pattern;
and 5: etching the oxide layer in the pattern area formed in the step 4 to form a diffusion area and a cutting path;
Step 6: doping a layer of N-type impurities in the diffusion region and the cutting channel formed in the step 5 to form an N-type doping layer;
And 7: continuously driving in the N-type impurity to form a PN junction of the N-type impurity and the P-type substrate;
And 8: removing the oxide layer on the substrate;
And step 9: thermally growing an oxide layer on the front surface and the back surface of the substrate respectively;
Step 10: irradiating the substrate surface with a second mask, and exposing by photolithography to obtain an electrode region pattern;
step 11: etching the oxide layer of the pattern area formed in the step 10 to form an electrode area;
step 12: plating negative electrode metal on the electrode areas of the front surface and the back surface of the substrate;
Step 13: irradiating the substrate surface with a third mask to form an electrode pattern by photolithography;
Step 14: and cutting the substrate into single chips along the cutting lines.
a manufacturing method of a unipolar diode surge voltage suppressor chip comprises the following steps:
step 1: taking a silicon wafer as a substrate, wherein the substrate is of a P type;
Step 2: thinning the substrate to a thickness of 150-200 μm;
And step 3: thermally growing an oxide layer on the front surface and the back surface of the substrate respectively;
And 4, step 4: irradiating the surface of the substrate with first light, and exposing by lithography to obtain a diffusion region and a scribe line pattern;
And 5: etching the oxide layer in the pattern area formed in the step 4 to form a diffusion area and a cutting path;
Step 6: doping a layer of N-type impurities in the diffusion region and the cutting channel formed in the step 5 to form an N-type doping layer;
and 7: continuously driving in the N-type impurity to form a PN junction of the N-type impurity and the P-type substrate;
and 8: removing the oxide layer on the substrate;
and step 9: thermally growing an oxide layer on the front surface and the back surface of the substrate respectively;
Step 10: irradiating the substrate surface with a second mask, and exposing by photolithography to obtain an electrode region pattern;
step 11: etching the oxide layer of the pattern area formed in the step 10 to form an electrode area;
step 12: plating negative electrode metal on the electrode area on the front side of the substrate, and plating positive electrode metal on the electrode area on the back side of the substrate;
step 13: irradiating the substrate surface with a third mask to form an electrode pattern by photolithography;
step 14: and cutting the substrate into single chips along the cutting lines.
the invention provides a bipolar diode surge voltage suppressor and a manufacturing method thereof.A thinning machine is used for grinding an original P-type silicon wafer to a specific thickness, a layer of N-type doping is diffused on the front side and the back side of the original silicon wafer for driving in, so that a chip NPN structure generates current gain under reverse bias, and the voltage of an element has the electrical characteristic of negative resistance so as to enhance the capacity of resisting impact current.
the invention also provides a unipolar diode surge voltage suppressor and a manufacturing method thereof, wherein an original P-type silicon wafer is ground to a specific thickness by using a thinning machine, a layer of N-type doping is diffused on the front side and the back side of the original silicon wafer and is driven in, so that a chip NPN structure generates current gain under reverse bias, and after a PN junction on the back side of the chip is short-circuited, the voltage of an element has the electrical characteristic of negative resistance so as to enhance the capacity of resisting impulse current.
Drawings
FIG. 1 is a cross-sectional view of a prior art diode surge suppressor chip;
FIG. 2 is a state diagram of a prior art diode surge suppressor chip in conduction with current;
FIG. 3 is a cross-sectional view of a bipolar diode surge suppressor chip in accordance with the present invention;
FIG. 4 is a cross-sectional view of a chip of the unipolar diode surge suppressor of the present invention;
FIG. 5 is a diagram of the state of the process for manufacturing the single and dual-polarity diode surge suppressor chip of the present invention shown in FIG. 1;
FIG. 6 is a diagram of the manufacturing process of the single-diode and dual-diode surge voltage suppressor chip of the present invention in a state of FIG. 2;
FIG. 7 is a diagram of the manufacturing process of the single-diode and dual-diode surge suppressor chip of the present invention in FIG. 3;
FIG. 8 is a diagram of the manufacturing process of the single-diode and dual-diode surge voltage suppressor chip of the present invention in FIG. 4;
FIG. 9 is a diagram of the state of the process for manufacturing the single and dual-polarity diode surge suppressor chip of the present invention shown in FIG. 5;
FIG. 10 is a state diagram of a process for manufacturing a BJT chip according to the present invention;
FIG. 11 is a state diagram of a process for manufacturing a BJT chip of the present invention;
FIG. 12 is a state diagram of a process for manufacturing a unipolar diode surge suppressor chip according to the present invention;
FIG. 13 is a state diagram of a process for manufacturing a unipolar diode surge suppressor chip of the present invention shown in FIG. 7;
FIG. 14 is a diagram showing the state of the BJT chip of the present invention when current is conducted.
Detailed Description
the conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.
referring to fig. 3 and 4, the diode surge voltage suppressor chip of the present invention has an NPN structure, N-type impurities 308 are diffused and distributed on the front and back sides of the P-type substrate 302, the doping concentration of the P-type substrate 302 is determined by the voltage value of the surge voltage, and if the voltage value is high, the doping concentration is low, and if the voltage value is low, the doping concentration is high. The electrode area 316 of the N-type impurity 308 is covered with electrode metal, the other areas are covered with the oxide layer 314, and the thickness of the chip is 170-240 μm. Fig. 3 shows a bipolar diode surge suppressor chip, in which the electrode regions 316 on the front and back sides are covered with a negative electrode metal 318; fig. 4 shows a unipolar diode surge suppressor chip, in which the electrode area 316 on the front side is covered with a negative electrode metal 318, and the electrode area 316 on the back side is entirely covered with a positive electrode metal 320.
the diode surge voltage suppressor chip of the invention controls the current gain of the NPN structure, so that the electrical property of the surge voltage suppressor voltage has the electrical property of negative resistance, and the P-type silicon wafer with better current gain control is used for thinning to a certain thickness. The original silicon wafer is subjected to double-sided diffusion N-type doping, the depth of a PN junction is controlled through complementary diffusion so as to further control the negative resistance characteristic of the chip, and when the chip meets surge voltage, the power borne by the element is reduced due to the characteristic that breakdown voltage carries negative resistance, so that the chip is more resistant to high current. Because the circuit formed by the MOSFET is more susceptible to surge voltage and high-voltage electrostatic attack to fail, the diode surge voltage suppressor chip can provide good protection for the circuit formed by the MOSFET.
referring to fig. 5 to 11, the method for manufacturing the bipolar diode surge suppressor chip of the present invention includes the following steps:
as shown in fig. 5, a silicon wafer is used as a substrate 302, and the substrate 302 is P-type; thinning the substrate 302 to a thickness of 150-200 μm using a thinning machine; placing the substrate 302 in an oxidation furnace to thermally grow an oxide layer 304 on the front surface and the back surface respectively;
as shown in fig. 6, the surface of the substrate 302 is irradiated with a mask having a pattern of diffusion regions and scribe lines, and the pattern of diffusion regions and scribe lines is obtained by photolithography exposure; etching the oxide layer in the pattern region to form a diffusion region 305 and a scribe line 306;
referring to fig. 7, the substrate 302 is placed in a diffusion furnace or ion implanter, and an N-type impurity 308 is doped in the diffusion region 305 and the scribe line 306 to form an N-type doped layer 310;
referring to FIG. 8, the substrate 302 is placed in a diffusion furnace, and the N-type impurity 308 is driven in to form a PN junction 312 between the N-type impurity 308 and the P-type substrate 302;
as shown in fig. 9, the oxide layer 304 on the substrate 302 is removed;
Referring to FIG. 10, the substrate 302 is placed in an oxidation furnace, an oxide layer 314 is thermally grown on each of the front and back surfaces, the surface of the substrate 302 is irradiated with an electrode pattern mask, and an electrode region pattern is obtained by photolithography exposure; etching the oxide layer in the patterned region to form an electrode region 316; wherein the electrode regions 316 on the front and back sides are both located above the diffusion region 305;
As shown in fig. 11, the electrode areas 316 on the front and back sides of the substrate 302 are plated with a negative electrode metal 318; irradiating the surface of the substrate 302 with an electrode pattern mask to form an electrode pattern by photolithography; the substrate 302 is diced into individual chips along dicing streets 306.
referring to fig. 5 to 9 and 12 to 13, the method for manufacturing the unipolar diode surge suppressor chip of the present invention includes the steps of:
As shown in fig. 5, a silicon wafer is used as a substrate 302, and the substrate 302 is P-type; thinning the substrate 302 to a thickness of 150-200 μm using a thinning machine; placing the substrate 302 in an oxidation furnace to thermally grow an oxide layer 304 on the front surface and the back surface respectively;
As shown in fig. 6, the surface of the substrate 302 is irradiated with a mask having a pattern of diffusion regions and scribe lines, and the pattern of diffusion regions and scribe lines is obtained by photolithography exposure; etching the oxide layer in the pattern region to form a diffusion region 305 and a scribe line 306;
referring to fig. 7, the substrate 302 is placed in a diffusion furnace or ion implanter, and an N-type impurity 308 is doped in the diffusion region 305 and the scribe line 306 to form an N-type doped layer 310;
referring to FIG. 8, the substrate 302 is placed in a diffusion furnace, and the N-type impurity 308 is driven in to form a PN junction 312 between the N-type impurity 308 and the P-type substrate 302;
As shown in fig. 9, the oxide layer 304 on the substrate 302 is removed;
Referring to FIG. 12, the substrate 302 is placed in an oxidation furnace, an oxide layer 314 is thermally grown on each of the front and back surfaces, the surface of the substrate 302 is irradiated with an electrode pattern mask, and an electrode region pattern is obtained by photolithography exposure; etching the oxide layer in the patterned region to form an electrode region 316; wherein the front electrode areas 316 are all located above the diffusion areas 305, and the back electrode areas 316 cover the entire back surface;
as shown in fig. 13, the electrode area 316 on the front side of the substrate 302 is plated with a negative electrode metal 318, and the electrode area 316 on the back side is plated with a positive electrode metal 320; irradiating the surface of the substrate 302 with an electrode pattern mask to form an electrode pattern by photolithography; the substrate 302 is diced into individual chips along dicing streets 306.
referring to fig. 14, the current distribution of the bipolar diode surge voltage suppressor of the present invention is schematically illustrated, in the manufacturing method of the present invention, since the substrate 302 is thinned, the P layer in the NPN structure is shortened by the deep diffusion layer 312, and the current I gain of the surge suppressor after being turned on is increased, the breakdown voltage of the surge suppressor has a negative resistance characteristic, the PN junction generates a lower clamping voltage when receiving a surge current, and the device inherently bears a lower power and can withstand a higher surge current. For example, the surge voltage suppressor manufactured by the conventional technology with the same PN junction can withstand 100 amperes, and the surge current of the surge voltage suppressor manufactured by the invention can be increased by 1 time to 200 amperes, so that the surge voltage suppressor is not easy to be burnt.
the above disclosure is only an example of the present invention, but the present invention is not limited thereto, and any variations that can be made by those skilled in the art should fall within the scope of the present invention.
Claims (7)
1. A diode surge voltage suppressor chip is of an NPN structure, N-type impurities (308) are diffused and distributed on the front surface and the back surface of a P-type substrate (302), electrode areas (316) of the N-type impurities (308) are covered with electrode metal, and other areas are covered with an oxide layer (314), and the diode surge voltage suppressor chip is characterized in that the thickness of the chip is 170-240 mu m.
2. the diode surge suppressor chip according to claim 1, wherein the diode surge suppressor chip is bipolar, and the electrode regions (316) on the front and back sides are covered with a negative electrode metal (318).
3. The diode surge suppressor chip according to claim 1, characterized in that the diode surge suppressor chip is unipolar, and the electrode area (316) of the front side is covered with a negative electrode metal (318), and the electrode area (316) of the back side is entirely covered with a positive electrode metal (320).
4. the diode surge suppressor chip of claim 2 or 3, wherein the doping concentration of the P-type substrate (302) is determined by the voltage value of the surge voltage, and the doping concentration is low when the voltage value is high and the doping concentration is high when the voltage value is low.
5. the diode surge suppressor chip according to claim 2 or 3, wherein said chip is used for circuit protection of metal oxide semiconductor field effect transistors.
6. a method for manufacturing a bipolar diode surge suppressor chip according to claim 2, comprising the steps of:
step 1: taking a silicon wafer as a substrate (302), wherein the substrate (302) is of a P type;
step 2: thinning the substrate (302) to a thickness of 150-200 μm;
and step 3: thermally growing an oxide layer (304) on each of the front and back surfaces of the substrate (302);
And 4, step 4: irradiating the surface of the substrate (302) with a first light, and obtaining a diffusion region and scribe line pattern by photolithography exposure;
and 5: etching the oxide layer in the patterned area formed in step 4 to form a diffusion area (305) and a scribe line (306);
step 6: doping a layer of N-type impurity (308) in the diffusion region (305) and the cutting channel (306) formed in the step 5 to form an N-type doped layer (310);
and 7: continuing to drive in the N-type impurity 308 to form a PN junction 312 between the N-type impurity 308 and the P-type substrate 302;
And 8: removing an oxide layer (304) on a substrate (302);
and step 9: thermally growing an oxide layer (314) on each of the front and back surfaces of the substrate (302);
step 10: irradiating the surface of the substrate (302) with a second mask to obtain a pattern of electrode areas by means of photolithography exposure;
Step 11: etching the oxide layer of the pattern region formed in the step 10 to form an electrode region (316);
Step 12: plating negative electrode metal (318) on the electrode areas (316) on the front surface and the back surface of the substrate (302);
step 13: irradiating the surface of the substrate (302) with a third mask to form an electrode pattern by photolithography;
step 14: the substrate (302) is diced into individual chips along dicing streets (306).
7. a method of manufacturing a unipolar diode surge suppressor chip according to claim 3, characterized by comprising the steps of:
Step 1: taking a silicon wafer as a substrate (302), wherein the substrate (302) is of a P type;
Step 2: thinning the substrate (302) to a thickness of 150-200 μm;
and step 3: thermally growing an oxide layer (304) on each of the front and back surfaces of the substrate (302);
And 4, step 4: irradiating the surface of the substrate (302) with a first light, and obtaining a diffusion region and scribe line pattern by photolithography exposure;
and 5: etching the oxide layer in the patterned area formed in step 4 to form a diffusion area (305) and a scribe line (306);
step 6: doping a layer of N-type impurity (308) in the diffusion region (305) and the cutting channel (306) formed in the step 5 to form an N-type doped layer (310);
and 7: continuing to drive in the N-type impurity 308 to form a PN junction 312 between the N-type impurity 308 and the P-type substrate 302;
and 8: removing an oxide layer (304) on a substrate (302);
and step 9: thermally growing an oxide layer (314) on each of the front and back surfaces of the substrate (302);
Step 10: irradiating the surface of the substrate (302) with a second mask to obtain a pattern of electrode areas by means of photolithography exposure;
step 11: etching the oxide layer of the pattern region formed in the step 10 to form an electrode region (316);
step 12: plating a negative electrode metal (318) on the electrode area (316) on the front surface of the substrate (302), and plating a positive electrode metal (320) on the electrode area (316) on the back surface;
step 13: irradiating the surface of the substrate (302) with a third mask to form an electrode pattern by photolithography;
step 14: the substrate (302) is diced into individual chips along dicing streets (306).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810594567.4A CN110581178A (en) | 2018-06-11 | 2018-06-11 | diode surge voltage suppressor chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810594567.4A CN110581178A (en) | 2018-06-11 | 2018-06-11 | diode surge voltage suppressor chip and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110581178A true CN110581178A (en) | 2019-12-17 |
Family
ID=68809604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810594567.4A Pending CN110581178A (en) | 2018-06-11 | 2018-06-11 | diode surge voltage suppressor chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110581178A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5245412A (en) * | 1992-02-18 | 1993-09-14 | Square D Company | Low capacitance silicon transient suppressor with monolithic structure |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
| CN201699018U (en) * | 2010-06-22 | 2011-01-05 | 南通明芯微电子有限公司 | High-power planar junction unilateral TVS diode chip |
| CN103050545A (en) * | 2011-10-14 | 2013-04-17 | 上海韦尔半导体股份有限公司 | TVS (Transient Voltage Suppressor) diode and manufacturing method thereof |
| US20160293592A1 (en) * | 2015-03-31 | 2016-10-06 | Vishay General Semiconductor Llc | Thin bi-directional transient voltage suppressor (tvs) or zener diode |
| CN206742243U (en) * | 2017-05-16 | 2017-12-12 | 上海长园维安微电子有限公司 | A kind of two-way TVS device with anti-paralleled diode |
-
2018
- 2018-06-11 CN CN201810594567.4A patent/CN110581178A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5245412A (en) * | 1992-02-18 | 1993-09-14 | Square D Company | Low capacitance silicon transient suppressor with monolithic structure |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
| CN201699018U (en) * | 2010-06-22 | 2011-01-05 | 南通明芯微电子有限公司 | High-power planar junction unilateral TVS diode chip |
| CN103050545A (en) * | 2011-10-14 | 2013-04-17 | 上海韦尔半导体股份有限公司 | TVS (Transient Voltage Suppressor) diode and manufacturing method thereof |
| US20160293592A1 (en) * | 2015-03-31 | 2016-10-06 | Vishay General Semiconductor Llc | Thin bi-directional transient voltage suppressor (tvs) or zener diode |
| CN206742243U (en) * | 2017-05-16 | 2017-12-12 | 上海长园维安微电子有限公司 | A kind of two-way TVS device with anti-paralleled diode |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220165725A1 (en) | High Voltage ESD Protection Apparatus | |
| US8648419B2 (en) | ESD protection device and method | |
| US5477078A (en) | Integrated circuit (IC) with a two-terminal diode device to protect metal-oxide-metal capacitors from ESD damage | |
| US7715159B2 (en) | ESD protection circuit | |
| CN110364523B (en) | ESD protection device, semiconductor device including the same, and method of manufacturing the same | |
| US9620496B2 (en) | Stacked protection devices with overshoot protection and related fabrication methods | |
| US9330961B2 (en) | Stacked protection devices and related fabrication methods | |
| US9019667B2 (en) | Protection device and related fabrication methods | |
| JP2012104834A (en) | High voltage bipolar-based esd protection structure | |
| US9502890B2 (en) | Protection device and related fabrication methods | |
| US10411004B2 (en) | Semiconductor device suitable for electrostatic discharge (ESD) protection | |
| US10483257B2 (en) | Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection | |
| US9287255B2 (en) | ESD protection device and related fabrication methods | |
| JPH10256393A (en) | Semiconductor device | |
| EP2827373B1 (en) | Protection device and related fabrication methods | |
| US9129806B2 (en) | Protection device and related fabrication methods | |
| CN110581178A (en) | diode surge voltage suppressor chip and manufacturing method thereof | |
| JP6594296B2 (en) | Zener diode with polysilicon layer with improved reverse surge capability and reduced leakage current | |
| US10643989B2 (en) | Electrostatic discharge protection apparatus having at least one junction and method for operating the same | |
| US9478531B2 (en) | Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device | |
| KR20200027902A (en) | Structure and method for sic based protection device | |
| JP2014038922A (en) | Semiconductor device | |
| US11837600B2 (en) | Electrostatic discharge protection apparatus and its operating method | |
| CN117133770A (en) | Electrostatic discharge protection structure, forming method and working method thereof | |
| CN117917780A (en) | Unidirectional high-voltage punch-through TVS diode and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191217 |
|
| RJ01 | Rejection of invention patent application after publication |