CN110572012A - Grid driving circuit and switching power supply circuit - Google Patents
Grid driving circuit and switching power supply circuit Download PDFInfo
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- CN110572012A CN110572012A CN201910813700.5A CN201910813700A CN110572012A CN 110572012 A CN110572012 A CN 110572012A CN 201910813700 A CN201910813700 A CN 201910813700A CN 110572012 A CN110572012 A CN 110572012A
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- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000000740 bleeding effect Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to the technical field of integrated circuits, and particularly discloses a gate drive circuit, which comprises: the power tube switch-on circuit comprises a power tube switch-off circuit and at least one light-load marking circuit, wherein the input ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with a main control chip, the output ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with the grid drive end of a power switch tube, and each light-load marking circuit is connected with the power switch-off circuit; and each light-load marking circuit generates a second turn-off signal of the power tube when the current working state of the switching power supply circuit is light load, and the second turn-off signal of the power tube and the first turn-off signal of the power tube can jointly control the power switching tube to be turned off. The invention also discloses a switching power supply circuit. The grid driving circuit provided by the invention achieves the purpose of giving consideration to full-load EMI and light-load standby power consumption.
Description
Technical Field
the invention relates to the technical field of integrated circuits, in particular to a gate driving circuit and a switching power supply circuit comprising the same.
Background
In the switching power supply system, the generation of the power switching tube control signal is realized by properly converting the driving logic signal through the gate driving module, and finally driving the power tube to be switched on and off. When the primary side control isolation type flyback converter works, energy is transferred between the primary coil and the secondary coil; the secondary coil transmits output information to the auxiliary winding, and the input and the output are isolated by using a transformer. A general switching power supply control system has two processes of starting and stopping of a power tube. When the power tube is started, the primary side inductor forms a path to the ground, the input end supplies energy to the transformer, the primary side inductor stores energy, the secondary side diode is cut off, and the load output energy is supplied by the energy stored in the output capacitor; when the power tube is turned off, the transformer releases energy, and the secondary inductor releases energy.
it has been analyzed that the effect of the drop delay on the full load condition is much less in the prior art switching power supply system than under light load. In modern PWM control engineering application, the EMI effect is often tested under the full load condition; and under the no-load condition, measuring the standby power consumption. Under the full-load condition, the time delay influence is small, in order to improve EMI caused by driving, the common method in the industry is to artificially control EMI, so that the driving voltage signal is slowly reduced, and when the time delay is provided, the EMI effect is also improved while the driving voltage signal is slowly reduced. However, when the delay time is artificially increased, the standby power consumption may be increased while improving the EMI. This is due in part to the additional energy generated by the time delay being transferred through the transformer to the secondary side, which has an effect on the output energy. Moreover, the energy is inherent in the system and is not controlled by a feedback loop, and the change caused by the improvement of the control loop is avoided, so that the standby power consumption is greatly increased. From the stand-by power consumption point of view, in order to reduce the stand-by power consumption, we must shorten the turn-off delay as much as possible. Therefore, how to achieve both EMI under a full load condition and reduce standby power consumption under no load becomes a technical problem to be solved urgently by those skilled in the art.
disclosure of Invention
the invention provides a gate driving circuit and a switching power supply circuit comprising the same, and solves the problem that full-load EMI and no-load standby power consumption cannot be considered simultaneously in the related technology.
As an aspect of the present invention, there is provided a gate driving circuit, wherein the gate driving circuit includes: the power tube switch-on circuit comprises a power tube switch-on circuit, a power tube switch-off circuit and at least one light-load marking circuit, wherein the input ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with a main control chip, the output ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with a grid drive end of a power switch tube, and each light-load marking circuit is connected with the power switch-off circuit;
The power tube conducting circuit and the power tube turn-off circuit are alternately conducted according to the control signal of the main control chip, the power tube conducting circuit can generate a power tube conducting signal to control the conduction of the power switch tube when being conducted, and the power tube turn-off circuit can generate a power tube first turn-off signal to control the turn-off of the power switch tube when being conducted;
Each path of light-load marking circuit can judge the working state of the current switch power supply circuit according to the control signal of the main control chip, and generates a second turn-off signal of the power tube when the working state of the current switch power supply circuit is light load, and the second turn-off signal of the power tube and the first turn-off signal of the power tube can jointly control the turn-off of the power switch tube.
Furthermore, the control signal of the main control chip comprises a feedback control signal and a switch control signal, the power tube on circuit and the power tube off circuit are alternately switched on according to the switch control signal, and each light load marking circuit judges the current working state of the switch circuit according to the feedback control signal.
Further, the light load flag circuit includes: the light load mark generating circuit comprises a light load mark generating circuit and a control circuit, wherein the input end of the light load mark generating circuit is connected with the main control chip, and the output end of the light load mark generating circuit is connected with the control circuit;
the light load mark generation circuit can judge the current working state of the switching power supply circuit according to the control chip of the main control chip and generate a light load mark signal when the current working state of the switching power supply circuit is light load;
The control circuit can generate a second turn-off signal of the power tube according to the light-load mark signal.
Furthermore, the control circuit comprises a logic and gate and a first switch tube, a first input end of the logic and gate is connected with the light load mark generation circuit, a second input end of the logic and gate is connected with the power tube turn-off circuit, an output end of the logic and gate is connected with a driving end of the first switch tube, a first end of the first switch tube is connected with a grid driving end of the power switch tube, and a second end of the first switch tube is connected with a signal ground.
furthermore, the power tube turn-off circuit comprises a power tube turn-off signal generating circuit, a second switch tube and a first resistor, wherein the input end of the power tube turn-off signal generating circuit is connected with the main control chip, the output end of the power tube turn-off signal generating circuit is respectively connected with the logic and gate and the driving end of the second switch tube, the first end of the second switch tube is connected with the gate driving end of the power switch tube through the first resistor, and the second end of the second switch tube is connected with a signal ground.
Further, the first switch tube and the second switch tube each comprise an N-type switch tube.
Furthermore, the power tube conducting circuit comprises a power tube conducting signal generating circuit and a third switching tube, the input end of the power tube conducting signal generating circuit is connected with the main control chip, the output end of the power tube conducting signal generating circuit is connected with the driving end of the third switching tube, the first end of the third switching tube is connected with a power supply voltage, and the second end of the third switching tube is connected with the grid driving end of the power switching tube.
Further, the third switch tube comprises an N-type switch tube.
As another aspect of the present invention, a switching power supply circuit is provided, where the switching power supply circuit includes a main control chip, a power switch tube, and the gate driving circuit described above, the main control chip is connected to the gate driving circuit, the gate driving circuit is connected to the power switch tube, and the gate driving circuit can generate a signal for driving the power switch tube to turn on or off under the control of the main control chip.
Through the grid driving circuit, the working state of the current switching power supply circuit can be judged through the light load marking circuit, and the working state can be jointly controlled with a turn-off signal generated by the power tube turn-off circuit to turn off the power switching tube when the working state is light load, so that the aim of improving the discharge capacity under the no-load condition can be fulfilled, the standby power consumption under the no-load condition is further reduced, meanwhile, the discharge speed of the power tube turn-off circuit under the full-load condition is reduced compared with the prior art, the time delay is increased, the EMI under the full-load condition is improved, and the grid driving circuit provided by the embodiment achieves the aim of considering both the EMI under the full-load condition and the standby power consumption under the light load condition.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
Fig. 1 is a schematic diagram of a circuit structure for generating a driving signal of a power switch tube.
Fig. 2 is a waveform diagram corresponding to driving related signals under full load and light load conditions.
Fig. 3 is a block diagram of a gate driving circuit according to an embodiment of the invention.
Fig. 4 is a circuit structure diagram of a gate driving circuit according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
in order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the switching power supply system, the generation of the power switching tube control signal is realized by properly converting the driving logic signal through the gate driving module, and finally driving the power tube to be switched on and off. Fig. 1 shows a schematic diagram of a power tube drive signal generation circuit. The power tube driving signal generating circuit comprises a driving logic signal generating circuit 100 and a gate driving circuit 101. The driving logic signal generating circuit 100 generates a logic control signal 108 by receiving a switch control signal (including an on signal and an off signal) generated from a feedback loop; since the transistor size of the external MOSFET power switch tube 102 is often larger, the driving capability of the external MOSFET power switch tube 102 is limited only by the 100 modules alone, and the external MOSFET power switch tube cannot drive the external MOSFET power switch tube 102, the gate driving circuit 101 is added to increase the driving capability. The gate driving circuit 101 generates a gate driving signal 109 by receiving a high voltage signal 110 and a logic driving signal 108 from an external input, and drives the external power transistor 102 to turn on or off. When the power switch tube 102 is switched on, the primary inductor of the transformer 104 stores energy, the control chip samples the voltage on the primary sampling resistor 103, and the primary sampling voltage value 111 is input to the control chip; at the same time, the secondary rectifier diode 105 is turned off and the output energy is provided by the energy stored on the output capacitor 106. When the switching power tube 102 is turned off, the transformer 104 discharges the stored energy in the form of current through the auxiliary winding Ns, supplying energy to the load 107 and the output capacitor 106.
It should be noted that, for the sake of simplicity, the control chip is not shown in fig. 1. It should be understood by those skilled in the art that the power tube driving signal schematic is applicable to other switching power supply systems and is not limited to this type of system topology.
Fig. 2 shows the corresponding waveforms driving the relevant output signals. Where the PWM waveform 200 corresponds to the output 108 signal shown in fig. 1 operating at full load; the PWM waveform 208 corresponds to the output 108 signal shown in fig. 1 operating under light load conditions; DRV waveform 201 corresponds to the output 109 signal shown in FIG. 1 operating under full load conditions; DRV waveform 209 corresponds to the output 109 signal shown in FIG. 1 operating under light load conditions; the V _ cs waveform 203 corresponds to the output 111 signal shown in FIG. 1 operating under full load conditions; the V _ cs waveform 211 corresponds to the output 111 signal shown in FIG. 1, operating under light load conditions. Waveform 206 is the miller plateau during the rise (switch on) of DRV signal 201; waveform 207 is the miller plateau during the fall (switch off) of DRV signal 201; waveform 214 is the miller plateau during the rise (switch on) of DRV signal 209; waveform 215 is the miller plateau during the fall (switch off) of DRV signal 209. After the rising edge of the logic-on signal 200 arrives, the primary-side sampling voltage 203 does not start to rise because of the existence of the miller platform 206 in the actual gate driving signal 201, and when the miller platform 206 ends, the primary-side sampling voltage 203 starts to rise; similarly, during the turn-off process, when the falling edge 205 of the logic-on signal 200 arrives, the primary-side sampled voltage 203 does not stop rising because of the presence of the miller plateau 207 in the actual gate driving signal 201, and when the miller plateau 207 ends, the primary-side sampled voltage 203 stops rising. Similarly, under light load conditions, after the rising edge of the logic on signal 208 arrives, the primary side sampling voltage 211 does not start to rise, because the miller platform 214 exists in the actual gate driving signal 209, and when the miller platform 214 ends, the primary side sampling voltage 211 starts to rise; similarly, during the turn-off process, when the falling edge 213 of the logic-on signal 208 arrives, the primary-side sampled voltage 211 does not stop rising because of the presence of the miller plateau 215 in the actual gate driving signal 208, and when the miller plateau 215 ends, the primary-side sampled voltage 211 stops rising.
Taking the turn-off delay as an example, the waveforms 204 and 212 shown in fig. 2 correspond to each other, that is, the transmission delay generated in the turn-off process; i.e., the logic shutdown signals 205 and 213, create a delay between the actual shutdown. In certain system applications, the delays 204 and 212 are determined by the gate capacitances of the driver module and the external power switch, so that in certain systems the delay is constant. Thus, the turn-off delays 204 and 212 are equal under full load and light load conditions.
In addition, the waveform 202 is the peak reference level of the primary side sampling voltage 203 under the full load condition; waveform 210 is the peak reference level of the primary sampled voltage 211 under light load conditions.
Comparing the output waveforms 200-207 under full load conditions with the output waveforms 208-215 under light load conditions, it can be seen that the off-delays 204 and 212 due to the miller platform are equal under different load conditions, and assume that the values are Vref. Assume that the area of the shaded portion in the 203 waveform is S204The triangular area of the waveform 203 as a whole is S203(ii) a 211 area of the shaded portion in the waveform is S212The triangular area of the waveform 211 is S211. Since the rising slope of the primary sampled voltage is constant under the determination system, the triangular slopes of waveform 203 and waveform 211The edge slopes are equal and assume their value as k. Assume that the reference level 202 has a value Vref_202The reference level 210 has a value Vref_210。
The ratio of the shadow area to the total area of the respective triangle is calculated as:
In practical systems, the turn-off delay T due to the Miller stagedoften at the ns level, in formula derivation, it can be simply calculated for a concise and intuitive comparison:
Specifically, reference level 202 may be set to 500mV and level 210 may be set to 100mV, then the above equation
From the above analysis, it can be seen that the error amount (in the shaded area S) of the primary side sampling voltage due to the drop delay204Occupies the total area S203Ratio of (A)1To quantify the representation), under full load conditions (i.e., a)1) The effect is less than under light load (i.e. A)2) The resulting effect is much less.
Therefore, in order to reduce standby power consumption, it is necessary to shorten the off delay as much as possible, from the viewpoint of standby power consumption. And the reduction of the turn-off delay can be realized by realizing the mode of providing weak discharge capacity under the full-load condition and providing strong discharge capacity under the no-load condition.
In order to achieve the objective of considering both the EMI effect under the full load condition and the standby power consumption under the no-load condition, a gate driving circuit is provided in this embodiment, and fig. 3 is a block diagram of a structure of a gate driving circuit 101 provided according to an embodiment of the present invention, as shown in fig. 3, including:
The power tube switch-on circuit comprises a power tube switch-on circuit 10, a power tube switch-off circuit 20 and at least one light-load marking circuit 30, wherein the input ends of the power tube switch-on circuit 10 and the light-load marking circuit 30 of the power tube switch-off circuit 20 can be connected with a main control chip, the output ends of the power tube switch-on circuit 10, the power tube switch-off circuit 20 and the light-load marking circuit 30 can be connected with a grid drive end of a power switch tube, and each light-load marking circuit is connected with the power switch-off circuit;
The power tube on-state circuit 10 and the power tube off-state circuit 20 are alternately switched on according to the control signal of the main control chip, the power tube on-state circuit can generate a power tube on-state signal to control the power switch tube to be switched on when being switched on, and the power tube off-state circuit can generate a power tube first off-state signal to control the power switch tube to be switched off when being switched on;
Each of the light-load flag circuits 30 is capable of determining a current operating state of the switching power supply circuit according to a control signal of the main control chip, and generating a second power transistor turn-off signal when the current operating state of the switching power supply circuit is a light load, where the second power transistor turn-off signal and the first power transistor turn-off signal are capable of controlling the power transistor to turn off.
Through the grid driving circuit, the working state of the current switching power supply circuit can be judged through the light load marking circuit, and the working state can be jointly controlled with a turn-off signal generated by the power tube turn-off circuit to turn off the power switching tube when the working state is light load, so that the aim of improving the discharge capacity under the no-load condition can be fulfilled, the standby power consumption under the no-load condition is further reduced, meanwhile, the discharge speed of the power tube turn-off circuit under the full-load condition is reduced compared with the prior art, the time delay is increased, the EMI under the full-load condition is improved, and the grid driving circuit provided by the embodiment achieves the aim of considering both the EMI under the full-load condition and the standby power consumption under the light load condition.
Specifically, the control signal of the main control chip includes a feedback control signal and a switch control signal, the power tube turn-on circuit 10 and the power tube turn-off circuit 20 are both alternately turned on according to the switch control signal, and each light-load flag circuit 30 determines the current working state of the switch circuit according to the feedback control signal.
Specifically, as shown in fig. 4, the light load flag circuit 30 includes: the light load mark generating circuit 402 comprises a light load mark generating circuit 402 and a control circuit, wherein the input end of the light load mark generating circuit 402 is connected with the main control chip, and the output end of the light load mark generating circuit 402 is connected with the control circuit;
The light load flag generating circuit 402 can determine the current operating state of the switching power supply circuit according to the control chip of the main control chip, and generates a light load flag signal when the current operating state of the switching power supply circuit is a light load;
The control circuit can generate a second turn-off signal of the power tube according to the light-load mark signal.
Further specifically, the control circuit includes a logic and gate 406 and a first switch tube 405, a first input end of the logic and gate 406 is connected to the light load flag generating circuit 402, a second input end of the logic and gate 406 is connected to the power tube turn-off circuit, an output end of the logic and gate 406 is connected to a driving end of the first switch tube 405, a first end of the first switch tube 405 is connected to a gate driving end of the power switch tube 102, and a second end of the first switch tube 405 is connected to a signal ground.
Preferably, the first switch tube 405 includes an N-type switch tube, and then the driving end of the first switch tube is a gate, the first end is a drain, and the second end is a source.
Specifically, the power tube turn-off circuit 20 includes a power tube turn-off signal generating circuit 401, a second switch tube 404 and a first resistor 413, an input end of the power tube turn-off signal generating circuit 401 is connected to the main control chip, an output end of the power tube turn-off signal generating circuit 401 is respectively connected to the logic and gate 406 and a driving end of the second switch tube 404, a first end of the second switch tube 404 is connected to a gate driving end of the power switch tube 102 through the first resistor 413, and a second end of the second switch tube 404 is connected to a signal ground.
Preferably, the second switch tube 404 includes an N-type switch tube, and then the driving end of the first switch tube is a gate, the first end is a drain, and the second end is a source.
specifically, the power tube conducting circuit 10 includes a power tube conducting signal generating circuit 400 and a third switching tube 403, an input end of the power tube conducting signal generating circuit 400 is connected to the main control chip, an output end of the power tube conducting signal generating circuit 400 is connected to a driving end of the third switching tube 403, a first end of the third switching tube 403 is connected to a power supply voltage VIN, and a second end of the third switching tube 403 is connected to a gate driving end of the power switching tube 102.
It should be noted that, both the power tube off signal generating circuit 401 and the power tube on signal generating circuit 400 may adopt conventional designs in the prior art, for example, the design of the proportional buffer and the PWM comparator and the power tube on signal generator mentioned in the patent application No. 201910636071.3 may be adopted, and details are not repeated here.
Preferably, the third switch tube 403 includes an N-type switch tube, and then the driving end of the first switch tube is a gate, the first end is a drain, and the second end is a source.
The operation principle of the gate driving circuit provided in this embodiment will be described in detail with reference to fig. 4.
As shown in fig. 4, 400, 401, 402, 403, 404, 405, 406, and 413 collectively constitute the gate driver circuit 101; the 108 signal passes through the power tube on-signal generating circuit 400 to generate a power tube on-signal 407; the 108 signal passes through the power tube off signal generation circuit 401 to generate the power tube off signal 408. Different from the traditional gate driving circuit, in the novel driving mode, a light load mark generating circuit 402 is added, the circuit 402 judges the current working state of the system by receiving a loop feedback control signal, and when the system works under the light load condition, the output signal 409 of the light load mark generating circuit 402 is at a high level. When the power tube turn-off signal 408 is high, the light load flag signal 409 and the power tube turn-off controlA control signal 408, which is a high level output control signal 410 through the logic and gate 406, controls the conduction of the MOS transistor 405, and controls the current discharge capacity 412 of the power switching transistor 102 to be equal; meanwhile, the power transistor turn-off signal 408 alone controls the conduction of the MOS transistor 404, which controls the current leakage capability 411 of the power switch tube 102 to be I1. From the foregoing analysis, in order to improve EMI, the system bleeding capability is often enhanced under an empty/light load condition to reduce the standby power consumption. In this embodiment, the current I is often discharged2Is set to a bleed current I1several times, the magnitude of the bleed current capability that ultimately controls the turn-off of the power switch tube 102 is: i is1+I2。
it will be understood by those skilled in the art that the two-way bleed current I referred to herein1And I2For example only, when changing the application, there may be more branches of the bleed current, or different intensity of the bleed current capability, or different ways of enhancing the bleed current capability, etc., and such changes, substitutions and modifications should not unduly limit the scope of the claims. Under the common control of the 411 and 412 bleeding branches, the bleeding speed of the power switching tube 102 during the idle/light load condition is significantly faster than that during the conventional driving control method, so that the standby power consumption during the idle/light load condition is significantly reduced.
When the switching power supply circuit works under a heavy load condition, the output signal 409 of the light load mark generating circuit 402 is at a low level, when the power tube turn-off signal 408 is at a high level, the light load mark signal 409 and the power tube turn-off control signal 408 output a control signal 410 at a low level through the logic AND gate 406, and the MOS tube 405 is controlled not to be conducted; the power transistor turn-off signal 408 alone controls the conduction of the MOS transistor 404, which controls the current leakage capability 411 of the power switch transistor 102 to be I1The magnitude of the current-discharging capability for finally controlling the turn-off of the power switch tube 102 is I1。
Therefore, under heavy load conditions, the off-state leakage speed of the power switch tube 102 is only I1when designing a switching power supply circuit, the circuit is often designed to be I1Reduce deliberately, and control conventional driveIn this way, the turn-off capability is reduced. Therefore, the voltage drop speed of the gate driving control signal 109 under a heavy load condition becomes slower than the turn-off speed in the conventional manner, and the EMI is improved.
In order to improve the EMI effect, the actual power tube driving signal is often improved from two aspects: the rising edge of the drive signal, the radiating EMI, and the falling edge of the drive signal, conduct EMI. In the present invention, the conducted EMI is improved, that is, the falling edge of the driving signal is processed.
As another embodiment of the present invention, a switching power supply circuit is provided, where the switching power supply circuit includes a main control chip, a power switch tube and the gate driving circuit, the main control chip is connected to the gate driving circuit, the gate driving circuit is connected to the power switch tube, and the gate driving circuit can generate a signal for driving the power switch tube to turn on or off under the control of the main control chip.
The switching power supply circuit provided by the embodiment adopts the gate driving circuit, the working state of the current switching power supply circuit can be judged through the light load marking circuit, and the working state can be jointly controlled with the turn-off signal generated by the power tube turn-off circuit to turn off the power switching tube when the working state is light load, so that the purpose of improving the discharge capacity under the no-load condition can be realized, and further the standby power consumption under the no-load condition is reduced.
Preferably, the main control chip may be specifically implemented by a chip with a model number SP 2689.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. A gate drive circuit, comprising: the power tube switch-on circuit comprises a power tube switch-on circuit, a power tube switch-off circuit and at least one light-load marking circuit, wherein the input ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with a main control chip, the output ends of the power tube switch-on circuit, the power tube switch-off circuit and the light-load marking circuit can be connected with a grid drive end of a power switch tube, and each light-load marking circuit is connected with the power switch-off circuit;
The power tube conducting circuit and the power tube turn-off circuit are alternately conducted according to the control signal of the main control chip, the power tube conducting circuit can generate a power tube conducting signal to control the conduction of the power switch tube when being conducted, and the power tube turn-off circuit can generate a power tube first turn-off signal to control the turn-off of the power switch tube when being conducted;
Each path of light-load marking circuit can judge the working state of the current switch power supply circuit according to the control signal of the main control chip, and generates a second turn-off signal of the power tube when the working state of the current switch power supply circuit is light load, and the second turn-off signal of the power tube and the first turn-off signal of the power tube can jointly control the turn-off of the power switch tube.
2. The gate driving circuit according to claim 1, wherein the control signals of the main control chip include a feedback control signal and a switch control signal, the power tube on circuit and the power tube off circuit are alternately turned on according to the switch control signal, and each of the light load flag circuits determines the current operating state of the switch circuit according to the feedback control signal.
3. the gate driving circuit of claim 1, wherein the light load flag circuit comprises: the light load mark generating circuit comprises a light load mark generating circuit and a control circuit, wherein the input end of the light load mark generating circuit is connected with the main control chip, and the output end of the light load mark generating circuit is connected with the control circuit;
The light load mark generation circuit can judge the current working state of the switching power supply circuit according to the control chip of the main control chip and generate a light load mark signal when the current working state of the switching power supply circuit is light load;
The control circuit can generate a second turn-off signal of the power tube according to the light-load mark signal.
4. The gate driving circuit according to claim 3, wherein the control circuit comprises a logic AND gate and a first switch tube, a first input end of the logic AND gate is connected to the light load flag generation circuit, a second input end of the logic AND gate is connected to the power tube turn-off circuit, an output end of the logic AND gate is connected to a driving end of the first switch tube, a first end of the first switch tube is connected to a gate driving end of the power switch tube, and a second end of the first switch tube is connected to a signal ground.
5. The gate driving circuit according to claim 4, wherein the power tube turn-off circuit comprises a power tube turn-off signal generating circuit, a second switch tube and a first resistor, an input end of the power tube turn-off signal generating circuit is connected to the main control chip, an output end of the power tube turn-off signal generating circuit is respectively connected to the logic and gate and a driving end of the second switch tube, a first end of the second switch tube is connected to the gate driving end of the power switch tube through the first resistor, and a second end of the second switch tube is connected to a signal ground.
6. a gate drive circuit as claimed in claim 5, wherein the first and second switching tubes each comprise an N-type switching tube.
7. The gate driving circuit according to claim 1, wherein the power tube conducting circuit comprises a power tube conducting signal generating circuit and a third switching tube, an input end of the power tube conducting signal generating circuit is connected with the main control chip, an output end of the power tube conducting signal generating circuit is connected with a driving end of the third switching tube, a first end of the third switching tube is connected with a power voltage, and a second end of the third switching tube is connected with a gate driving end of the power switching tube.
8. A gate drive circuit as claimed in claim 7, wherein the third switch transistor comprises an N-type switch transistor.
9. A switching power supply circuit, characterized in that, the switching power supply circuit includes a main control chip, a power switch tube and the gate drive circuit of any one of claims 1 to 8, the main control chip is connected with the gate drive circuit, the gate drive circuit is connected with the power switch tube, the gate drive circuit can generate a signal for driving the power switch tube to turn on or off under the control of the main control chip.
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| CN201910813700.5A CN110572012B (en) | 2019-08-30 | 2019-08-30 | Gate driving circuit and switching power supply circuit |
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| CN201910813700.5A CN110572012B (en) | 2019-08-30 | 2019-08-30 | Gate driving circuit and switching power supply circuit |
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| CN110572012B CN110572012B (en) | 2024-03-01 |
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| CN110572012B (en) | 2024-03-01 |
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