CN110571274B - Gallium oxide transistor and preparation method thereof - Google Patents
Gallium oxide transistor and preparation method thereof Download PDFInfo
- Publication number
- CN110571274B CN110571274B CN201910706502.9A CN201910706502A CN110571274B CN 110571274 B CN110571274 B CN 110571274B CN 201910706502 A CN201910706502 A CN 201910706502A CN 110571274 B CN110571274 B CN 110571274B
- Authority
- CN
- China
- Prior art keywords
- gallium oxide
- layer
- type doped
- channel
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 110
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 110
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 54
- 239000013078 crystal Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 6
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 description 8
- 230000005669 field effect Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Abstract
The invention provides a gallium oxide transistor and a preparation method thereof, wherein the transistor comprises: one side surface of the gallium oxide single crystal material is provided with a channel; an upper electrode disposed atop the channel of the gallium oxide single crystal material; the P-type doping layer is arranged on the channel bottom of the gallium oxide single crystal material; the gate dielectric layer is arranged on the P-type doped layer; the gate electrode is arranged on the gate dielectric layer; and a lower electrode disposed on the other side of the gallium oxide single crystal material. The gallium oxide transistor provided by the invention fully utilizes the performances of extremely wide forbidden band width and high theoretical breakdown field strength of the gallium oxide material to realize the purpose of further improving the high-voltage bearing capacity of the MOSFET.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a gallium oxide transistor, and further relates to a preparation method of the gallium oxide transistor.
Background
Gallium oxide is a novel ultra-wide bandgap semiconductor material, the bandgap width of the gallium oxide exceeds that of the traditional wide bandgap semiconductor materials such as SiC, GaN and the like, and the gallium oxide has higher theoretical breakdown field strength (E)c8MV/cm), which means that it can carry higher voltages without breakdown, by power quality factor (μm)0Ec 2μ is the carrier mobility, m0Carrier effective mass) that exceeds SiC and GaN, and therefore gallium oxide-based power devices are expected to carry higher voltages than SiC and GaN, thereby occupying a niche in the ultra-high voltage field. In addition, large-size, high-quality gallium oxide single crystals can be mass-produced by a modification of the melting method, which is called Edge-Defined Field-Fed Growth, as an important advantage. Furthermore, the gallium oxide homoepitaxy technology, such as MOCVD, HVPE, MBE, PLD, etc., has become mature, and provides a strong support for the design and preparation of devices.
Meanwhile, the activation rate of P-type impurities in the gallium oxide crystal is always low and difficult to apply, so that the structural design of the device is greatly limited, and the device structure of the traditional semiconductor material (such as Si) and the wide bandgap semiconductor material (such as SiC and GaN) cannot be realized. Therefore, a technical scheme for realizing the gallium oxide high-voltage field effect transistor by using the n-type doped material is targeted.
The high-voltage field effect transistor has a normally-on type and a normally-off type, and is different in operation mode, for a normally-on device, a gate electrode is powered off, the device is kept on, and only when voltage is applied to the gate electrode, the device can be switched off. And the normally-off device is opposite, the grid electrode is powered off, the device is kept off, and after voltage is applied to the grid electrode, the device is started. In practical applications, the high-voltage MOSFET is often used as a switching device to be connected in series in a high-voltage circuit, and a high voltage is carried between a source electrode and a drain electrode. The normally-open device can be switched off only by electrifying the grid, if the grid voltage is disturbed to cause misoperation, the device is suddenly switched on from a switching-off state, at the moment, the high voltage is still in the device, and the current conduction means that the device generates heat with great thermal power to burn the device, and more serious, the damage of the large current generated by misoperation to the core equipment of the system can be irreversible. And the normally-off device can be kept off without powering on the grid electrode, so that the risk of turning off is avoided. However, the gallium oxide is difficult to invert, and the P-type impurity is difficult to effectively activate, so that the channel layer and the source/drain active region cannot form an inverted PN junction to effectively turn off, and thus, the normally-off MOSFET based on the gallium oxide material is difficult to realize.
The problems of the prior art for preparing the MOSFET are as follows: the performance of the high-voltage field effect transistor is greatly limited by the small forbidden band width and the low theoretical breakdown field strength of Si; the complex Si-based high-voltage Field effect transistor structure (such as Super-Junction, Reduce Surface Field, and the like) increases the production cost of the device and reduces the stability of the device, so that the cost advantage of the Si material is weakened due to the introduction of a complex process. The SiC-based high-voltage field effect transistor has the problem that interface state density caused by a surface C complex is relatively high, and the stability of a device, such as threshold voltage drift and frequency characteristics, is influenced. The cost of the SiC material is high due to the limitation of the growth mode, so that the cost of the device is difficult to reduce, and the application and popularization of the SiC material are limited. The high bulk defect density of SiC materials limits the voltage capability of high voltage vertical structure SiC-based MOSFETs.
The existing scheme is to utilize a vertical narrow channel to capture a negative charge center by using an interface state and utilize a negative charge electric field to deplete the channel, thereby realizing a normally-off vertical high-voltage MOSFET. Although the high interface state charge depletes the channel and allows for normally-off operation, it also introduces device stability issues.
Disclosure of Invention
Technical problem to be solved
In view of the above, the present invention provides a gallium oxide transistor and a method for fabricating the same to at least partially solve the above technical problems.
(II) technical scheme
According to an aspect of the present invention, there is provided a gallium oxide transistor including:
one side surface of the gallium oxide single crystal material is provided with a channel;
an upper electrode disposed atop the channel of the gallium oxide single crystal material;
the P-type doping layer is arranged on the channel bottom of the gallium oxide single crystal material;
the gate dielectric layer is arranged on the P-type doped layer;
the gate electrode is arranged on the gate dielectric layer;
and the lower electrode is arranged on the other side of the gallium oxide single crystal material.
In a further embodiment, the channel is a vertical channel and the width of the channel is between 200nm and 600 nm.
In a further embodiment, the doping concentration of the P-type doped layer is between 1 × 1018cm-3To 1X 1021cm-3To (c) to (d); the doping material of the P-type doping layer is CuO2、SnO、Ir2O3Or NiO.
In a further embodiment, the gallium oxide single crystal material comprises a first n-type doped gallium oxide layer, a second n-type doped gallium oxide layer and a third n-type doped gallium oxide layer which are sequentially stacked, and the doping concentration of the first n-type doped gallium oxide layer and the doping concentration of the third n-type doped gallium oxide layer are greater than that of the third n-type doped gallium oxide layer.
In a further embodiment, the P-type doped layer has a thickness of 200nm to 500 nm.
According to another aspect of the present invention, there is provided a method for manufacturing a gallium oxide transistor, comprising:
forming a patterned upper electrode on the gallium oxide single crystal material;
etching the gallium oxide single crystal material to form a channel by taking the position of the upper electrode as the top of the channel;
forming a P-type doped layer on the gallium oxide single crystal material forming the channel;
forming a gate dielectric layer on the P-type doped layer;
patterning the bottom of the channel to form a gate electrode layer;
exposing the upper electrode at the top of the channel through an etching process;
and patterning the other side of the gallium oxide single crystal material to form a lower electrode.
In a further embodiment, the gallium oxide single crystal comprises a first n-type doped gallium oxide layer, a second n-type doped gallium oxide layer and a third n-type doped gallium oxide layer which are sequentially stacked, and the doping concentration of the first n-type doped gallium oxide layer and the doping concentration of the third n-type doped gallium oxide layer are greater than that of the third n-type doped gallium oxide layer; the first n-type doped gallium oxide layer is prepared by a mode-guiding method, the second n-type doped gallium oxide layer is grown by hydride vapor phase epitaxy, and the third n-type doped gallium oxide layer is doped by utilizing an ion implantation mode.
In a further embodiment, the width of the channel is between 200nm and 600 nm.
In a further embodiment, the P-type doped layer has a thickness of 200nm to 500 nm.
In a further embodiment, the doping concentration of the P-type doped layer is between 1 × 1018cm-3To 1X 1021cm-3To (c) to (d); the doping material of the P-type doping layer is CuO2、SnO、Ir2O3Or NiO.
(III) advantageous effects
The invention designs a high-voltage vertical transistor based on wide-bandgap semiconductor material gallium oxide, and the purpose of further improving the high-voltage bearing capacity of the MOSFET is realized by fully utilizing the extremely wide bandgap and high theoretical breakdown field strength of the gallium oxide material.
In addition, the large-size and high-quality gallium oxide single crystal can be prepared by an Edge-Defined Field-Fed Growth method, has the characteristics of high Growth speed, high Growth quality, low energy consumption and relatively mature technology, is beneficial to large-scale Growth, has the potential cost advantage of large-scale mass production, and achieves the purpose of reducing the cost of the high-voltage MOSFET device.
Moreover, the beta-phase gallium oxide and the aluminum oxide have low lattice mismatch rate, so that the low interface state density can be obtained, and the purpose of improving the switching characteristic of the transistor can be achieved.
Furthermore, aiming at the problem that the activation rate of P-type doping of gallium oxide crystal is very low (so that a P-type doping layer cannot be used as a channel layer as in SiC to realize a vertical normally-off high-voltage MOSFET), the characteristic that an inversion layer (for example, even if a very high positive voltage is applied to n-type doped gallium oxide crystal, a conducting layer with a hole thin layer is still difficult to appear (such as semiconductor materials of Si, Ge and the like)) is difficult to realize through electric field modulation is adopted in the design scheme, a vertical columnar vertical narrow channel is formed through an etching process, and a P-type oxide is used for helping to deplete the channel, so that the purpose of a vertical enhancement (enhancement type) high-voltage field effect transistor is realized on the n-type doped gallium oxide crystal.
Drawings
Fig. 1-8 are process flow diagrams of methods for fabricating gallium oxide transistors according to embodiments of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
It should be noted that in the drawings or description, the same drawing reference numerals are used for similar or identical parts. Implementations not depicted or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints. Directional phrases used in the embodiments, such as "upper," "lower," "front," "rear," "left," "right," and the like, refer only to the orientation of the figure. Accordingly, the directional terminology used is intended to be in the nature of words of description rather than of limitation.
According to the basic concept of the present invention, there is provided a gallium oxide transistor including: one side surface of the gallium oxide single crystal material is provided with a channel; an upper electrode disposed atop the channel of the gallium oxide single crystal material; the P-type doping layer is arranged on the channel bottom of the gallium oxide single crystal material; the gate dielectric layer is arranged on the P-type doped layer; the gate electrode is arranged on the gate dielectric layer; and the lower electrode is arranged on the other side of the gallium oxide single crystal material. Wherein, by setting the impurity concentration in the P-type doping layer to be high, the depletion of the channel layer is facilitated.
According to another aspect of the embodiments of the present invention, there is also provided a method of manufacturing a gallium oxide transistor, including forming a patterned upper electrode on a gallium oxide single crystal material; etching the gallium oxide single crystal material to form a channel by taking the position of the upper electrode as the top of the channel; forming a P-type doped layer on the gallium oxide single crystal material forming the channel; forming a gate dielectric layer on the P-type doped layer; patterning the bottom of the channel to form a gate electrode layer; exposing the upper electrode at the top of the channel through an etching process; and patterning the other side of the gallium oxide single crystal material to form a lower electrode. The multiplication gallium oxide transistor integral structure provided by the method utilizes the performances of extremely wide forbidden band width and high theoretical breakdown field strength of the gallium oxide material to further improve the high-voltage bearing capacity of the MOSFET.
The present invention will now be described in detail by way of specific examples, but it should be understood that the following specific details are only illustrative of the invention and are not to be construed as limiting the invention.
Referring to fig. 1-8, a method for fabricating a gallium oxide transistor according to an embodiment of the present invention includes the steps of:
(1) the high-quality gallium oxide single crystal material is prepared, has a three-layer structure of low resistance (high n-type doping concentration), high resistance value (low n-type doping concentration) and low resistance (high n-type doping concentration), and comprises a first n-type doped gallium oxide layer 103, a second n-type doped gallium oxide layer 102 and a third n-type doped gallium oxide layer 101 from bottom to top. The first n-type doped gallium oxide layer 103 single crystal material can be prepared by a die-casting method, which is a method for growing a single crystal, and specifically, the material is heated to a molten state by a metal iridium crucible, and then the molten liquid is guided by a seed crystal to diffuse along a gap of a die, so that the size of the crystal is gradually enlarged, and a large-size crystal is pulled out. The second n-type doped gallium oxide layer 102 is realized by HVPE epitaxy, and the third n-type doped gallium oxide layer 101 realizes high doping by ion implantation of Si, thereby realizing ohmic contact with the upper electrode.
(2) Referring to fig. 2, the patterned growth of the upper electrode 110 (source electrode) is realized by photolithography and lift-off process, and the growth mode is electron beam evaporation or magnetic control. The growth site of the upper electrode serves as the top of the space between the trenches in the later stage.
(3) Referring to fig. 3, a vertical narrow channel structure is realized by RIE (reactive ion etching) or ICP (inductively coupled plasma etching) gallium oxide etching process, with a width of 200nm to 600 nm. The depth reaches more than 1 um.
(4) Referring to fig. 4, a layer of P-type semiconductor material 120 is deposited or grown with a higher P-type impurity concentration that will help deplete the channel layer. The doping concentration of the P-type doping layer is 1 × 1018cm-3To 1X 1021cm-3To (c) to (d); the doping material of the P-type doping layer includes but is not limited to CuO2、SnO、Ir2O3Or NiO, etc.; preferably, the thickness of the P-type doped layer is 200nm to 500 nm.
(5) Referring to fig. 5, the gate dielectric layer 130 is deposited by ALD (atomic layer deposition) and the deposition is aluminum oxide or silicon oxide.
(6) Referring to fig. 6, the patterned growth of the gate electrode 140 is realized by photolithography and lift-off process, and the growth mode is electron beam evaporation or magnetic control.
(7) Referring to fig. 7, then, through an etching process, a hole is formed to expose the source electrode (i.e., the upper electrode);
(8) referring to fig. 8, the patterned growth of the lower electrode 150 (drain electrode) is realized by photolithography and lift-off, the growth mode is electron beam evaporation or magnetic control, and the ohmic contact quality can be improved by an annealing process subsequently.
In summary, the present invention is directed to a method for fabricating a high voltage gallium oxide vertical normally-off type field effect transistor, which achieves normally-off operation. Meanwhile, the problem of stability of a device dielectric layer caused by using an interface state charge depletion channel can be avoided.
In addition, because the P-type doped layer has high concentration, a wider channel can be depleted, which means a wider current channel, and the on-resistance of the channel can be effectively reduced, so that higher on-current is obtained.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Furthermore, the definitions of the various elements are not limited to the specific structures, shapes or modes mentioned in the embodiments, and those skilled in the art can easily modify or replace them: similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present invention. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A gallium oxide transistor, comprising:
one side surface of the gallium oxide single crystal material is provided with a channel;
an upper electrode disposed atop the channel of the gallium oxide single crystal material;
the P-type doping layer is arranged on the channel bottom of the gallium oxide single crystal material;
the gate dielectric layer is arranged on the P-type doped layer;
the gate electrode is arranged on the gate dielectric layer;
and the lower electrode is arranged on the other side of the gallium oxide single crystal material.
2. The gallium oxide transistor according to claim 1, wherein the channel is a vertical channel and the width of the channel is 200nm to 600 nm.
3. The gallium oxide transistor according to claim 1, wherein the doping concentration of the P-type doped layer is between 1 x 1018cm-3To 1X 1021cm-3To (c) to (d); the doping material of the P-type doping layer is CuO2、SnO、Ir2O3Or NiO.
4. The gallium oxide transistor according to claim 1, wherein the gallium oxide single crystal material comprises a first n-type doped gallium oxide layer, a second n-type doped gallium oxide layer, and a third n-type doped gallium oxide layer, which are stacked in this order, and the doping concentration of the first n-type doped gallium oxide layer and the third n-type doped gallium oxide layer is greater than the doping concentration of the second n-type doped gallium oxide layer.
5. The gallium oxide transistor according to claim 1, wherein the thickness of the P-type doped layer is 200nm to 500 nm.
6. A method for preparing a gallium oxide transistor, comprising:
forming a patterned upper electrode on the gallium oxide single crystal material;
etching the gallium oxide single crystal material to form a channel by taking the position of the upper electrode as the top of the channel;
forming a P-type doped layer on the gallium oxide single crystal material forming the channel;
forming a gate dielectric layer on the P-type doped layer;
patterning the bottom of the channel to form a gate electrode layer;
exposing the upper electrode at the top of the channel through an etching process;
and patterning the other side of the gallium oxide single crystal material to form a lower electrode.
7. The method according to claim 6, wherein the gallium oxide single crystal comprises a first n-type doped gallium oxide layer, a second n-type doped gallium oxide layer and a third n-type doped gallium oxide layer which are stacked in this order, and the doping concentration of the first n-type doped gallium oxide layer and the third n-type doped gallium oxide layer is greater than that of the second n-type doped gallium oxide layer; the first n-type doped gallium oxide layer is prepared by a mode-guiding method, the second n-type doped gallium oxide layer is grown by hydride vapor phase epitaxy, and the third n-type doped gallium oxide layer is doped by utilizing an ion implantation mode.
8. The method of claim 6, wherein the width of the channel is between 200nm and 600 nm.
9. The method of claim 6, wherein the thickness of the P-type doped layer is 200nm to 500 nm.
10. The method of claim 6, wherein the doping concentration of the P-type doped layer is between 1 x 1018cm-3To 1X 1021cm-3To (c) to (d); the doping material of the P-type doping layer is CuO2、SnO、Ir2O3Or NiO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910706502.9A CN110571274B (en) | 2019-07-31 | 2019-07-31 | Gallium oxide transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910706502.9A CN110571274B (en) | 2019-07-31 | 2019-07-31 | Gallium oxide transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110571274A CN110571274A (en) | 2019-12-13 |
| CN110571274B true CN110571274B (en) | 2021-07-09 |
Family
ID=68774291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910706502.9A Active CN110571274B (en) | 2019-07-31 | 2019-07-31 | Gallium oxide transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110571274B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613662B (en) * | 2020-05-27 | 2021-06-11 | 东北大学 | Method for regulating and controlling spin polarization current generated by bias-induced collinear antiferromagnetic material |
| CN113594252B (en) * | 2021-07-28 | 2022-04-15 | 中山大学 | Super junction structure gallium oxide power transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409987A (en) * | 2016-12-08 | 2017-02-15 | 西安电子科技大学 | Deep ultraviolet APD detection diode based on Ir2O3/Ga2O3 and manufacturing method thereof |
| CN108493234A (en) * | 2018-05-10 | 2018-09-04 | 广东省半导体产业技术研究院 | A kind of gallium oxide vertical field-effect transistor of fin raceway groove and preparation method thereof |
| CN109427915A (en) * | 2017-08-24 | 2019-03-05 | 流慧株式会社 | Semiconductor device |
| WO2019065751A1 (en) * | 2017-09-29 | 2019-04-04 | 株式会社タムラ製作所 | Field effect transistor |
-
2019
- 2019-07-31 CN CN201910706502.9A patent/CN110571274B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409987A (en) * | 2016-12-08 | 2017-02-15 | 西安电子科技大学 | Deep ultraviolet APD detection diode based on Ir2O3/Ga2O3 and manufacturing method thereof |
| CN109427915A (en) * | 2017-08-24 | 2019-03-05 | 流慧株式会社 | Semiconductor device |
| WO2019065751A1 (en) * | 2017-09-29 | 2019-04-04 | 株式会社タムラ製作所 | Field effect transistor |
| CN108493234A (en) * | 2018-05-10 | 2018-09-04 | 广东省半导体产业技术研究院 | A kind of gallium oxide vertical field-effect transistor of fin raceway groove and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110571274A (en) | 2019-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9012984B2 (en) | Field effect transistor devices with regrown p-layers | |
| US10629720B2 (en) | Layered vertical field effect transistor and methods of fabrication | |
| US20150108501A1 (en) | Semiconductor device | |
| WO2016141762A1 (en) | Iii-nitride enhancement hemt and preparation method therefor | |
| CN107393890B (en) | Graphene buried heat dissipation layer and longitudinal channel GaN MISFET cell structure and preparation method | |
| CN110148625B (en) | Gallium oxide vertical junction field effect transistor and preparation method thereof | |
| Lu et al. | Recent advances in NiO/Ga2O3 heterojunctions for power electronics | |
| CN105428412A (en) | Algan/gan heterojunction field effect transistor and preparation method thereof | |
| CN111276541A (en) | Normally-off field effect transistor and preparation method thereof | |
| CN110571274B (en) | Gallium oxide transistor and preparation method thereof | |
| CN110571275A (en) | preparation method of gallium oxide MOSFET | |
| CN110212020A (en) | A kind of MOSFET element and preparation method thereof of the unilateral depth L shape base region structure of silicon carbide | |
| CN109873034A (en) | Normally-off HEMT power device of deposit polycrystalline AlN and preparation method thereof | |
| CN114899227A (en) | Enhanced gallium nitride-based transistor and preparation method thereof | |
| CN113257924A (en) | Schottky diode with high-resistance layer, preparation method of Schottky diode and power diode module | |
| WO2021072812A1 (en) | Lateral gan-based enhancement junction field-effect transistor device and preparation method therefor | |
| CN108054208A (en) | Lateral type gallium nitride-based field effect transistor and preparation method thereof | |
| EP3944337A1 (en) | Hole channel semiconductor transistor, manufacturing method therefor and use thereof | |
| CN110190128A (en) | A kind of MOSFET element and preparation method thereof of silicon carbide bilateral depth L shape base region structure | |
| CN116959991A (en) | Field effect transistor and preparation method thereof and method for preparing groove structure in drift layer of field effect transistor | |
| CN113394096B (en) | HEMT device and self-isolation method and manufacturing method thereof | |
| TWI789797B (en) | Semiconductor device, complementary semiconductor device including same, radio frequency device and electric power device, and method for adjusting distributed electric field of semiconductor device | |
| US20230335631A1 (en) | Semiconductor device and manufacturing method therefor | |
| CN209766426U (en) | Normally-off HEMT device for depositing polycrystalline AlN | |
| Li et al. | A comprehensive review of recent progress on enhancement-mode β-Ga2O3 FETs: Growth, devices and properties |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |