CN110571194A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN110571194A CN110571194A CN201810570900.8A CN201810570900A CN110571194A CN 110571194 A CN110571194 A CN 110571194A CN 201810570900 A CN201810570900 A CN 201810570900A CN 110571194 A CN110571194 A CN 110571194A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
the invention provides a method for manufacturing a semiconductor device, which comprises the steps of firstly forming a first virtual grid structure and a second virtual grid structure with different top surface heights in a first area and a second area, then protecting the first virtual grid structure with the relatively lower top surface height by utilizing an interlayer dielectric layer, replacing the second virtual grid structure with a second metal grid structure, and then lowering the height of the top surface of the second virtual grid structure by a chemical mechanical planarization process until the first virtual grid structure is exposed, so that the first virtual grid structure can be replaced with the first metal grid structure. The performance of the finally prepared semiconductor device is improved.
Description
Technical Field
the invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
The FinFET (FinFET) device is an advanced semiconductor device for 22nm and below process nodes, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can achieve the effect of reducing the width of a grid electrode of the device, generally comprises a Fin (Fin) protruding out of the surface of a semiconductor substrate, a grid electrode stacking structure covering the top surface and/or the side wall of the Fin (channel region), and a source region and a drain region which are positioned in the Fin on two sides of the grid electrode stacking structure, and compared with a planar MOSFET (metal oxide silicon semiconductor field effect transistor) device, the FinFET device can keep low cut-off current and improve driving current at the same time, and therefore the short channel effect can be effectively restrained. Meanwhile, in order to further improve the device performance of the FinFET, a high-K (dielectric constant) metal gate structure (a high-K gate dielectric layer + a metal gate electrode) is commonly used in the industry to replace a commonly used polysilicon gate stack structure (a silicon oxide gate dielectric layer + a polysilicon gate electrode). However, the current manufacturing method of the high-K metal gate structure is difficult to meet the manufacturing of the FinFET device with smaller size and higher performance.
disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can respectively form metal gate structures in different regions, avoid the adverse effects of the formation process of the metal gate structure in a certain region on other regions, such as process damage and the like, ensure the quality of the metal gate structure in each region and improve the performance of the finally formed device.
in order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate having a first region and a second region;
Forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate, wherein the top surface of the first dummy gate structure is lower than the top surface of the second dummy gate structure;
Depositing an interlayer dielectric layer on the surfaces of the first virtual grid structure, the second virtual grid structure and the semiconductor substrate, and flattening the top surface of the interlayer dielectric to the top surface of the second virtual grid structure;
Removing the second dummy gate structure to form a second gate trench, filling a second metal gate structure in the second gate trench, and planarizing the top surface of the second metal gate structure to the top surface of the first dummy gate structure;
and removing the first dummy gate structure to form a first gate trench, and filling a first metal gate structure in the first gate trench.
optionally, the first region is an NMOS region, and the second region is a PMOS region; or, the first region is a PMOS region, and the second region is an NMOS region.
Optionally, the first metal gate structure and the second metal gate structure both include a work function layer and a metal gate electrode layer, where materials of the work function layers of the first metal gate structure and the second metal gate structure are different.
Optionally, the semiconductor substrate includes: a semiconductor substrate; a plurality of fins respectively located on the surface of the semiconductor substrate in the first region and the second region; and the isolation layer is positioned on the surface of the semiconductor substrate, covers part of the side wall of each fin, and the upper surface of the isolation layer is lower than the top surface of each fin.
Optionally, the first dummy gate structure crosses over the fin of the first region and covers a sidewall and a top surface of a partial region of the fin of the first region; the second dummy gate structure crosses over the fins of the second region and covers the sidewalls and the top surface of a partial region of the fins of the second region.
optionally, the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate includes:
sequentially forming a virtual gate dielectric layer, a virtual gate layer and a hard mask layer on the semiconductor substrate so as to form initial virtual gate structures in the first area and the second area on the semiconductor substrate, wherein the initial virtual structures comprise the virtual gate dielectric layer, the virtual gate layer and the hard mask layer;
Etching back the hard mask layer in the initial virtual gate structure in the first region to enable the top surface of the hard mask layer in the first region to be lower than the top surface of the hard mask layer in the second region, so as to form a first virtual gate structure in the first region and a second virtual gate structure in the second region;
optionally, the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate includes:
forming an initial dummy gate structure on the semiconductor substrate, wherein the initial dummy gate structure is positioned in the first region and the second region;
forming a hard mask layer on the initial virtual grid structure and the surface of the semiconductor substrate;
Patterning the hard mask layer, and only reserving the hard mask layer on the top surface of the virtual grid structure;
Etching back the hard mask layer in the first area to enable the top surface of the hard mask layer in the first area to be lower than the top surface of the hard mask layer in the second area, so that a first virtual grid structure in the first area and a second virtual grid structure in the second area are formed;
Optionally, the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate includes:
forming an initial dummy gate structure on the semiconductor substrate, wherein the initial dummy gate structure is positioned in the first region and the second region;
and etching back the initial dummy gate structure in the first region to make the top surface of the dummy gate structure in the first region lower than the top surface of the dummy gate structure in the second region, thereby forming a first dummy gate structure in the first region and a second dummy gate structure in the second region.
optionally, after the initial dummy gate structures located in the first region and the second region are formed on the semiconductor substrate, a gate sidewall is formed on a sidewall of the initial dummy gate structure.
Optionally, before or after the gate sidewall is formed, an ion implantation process or an embedded source-drain epitaxy process is adopted to form source-drain regions in the semiconductor substrate on both sides of the initial virtual gate structure.
optionally, the hard mask layer is made of at least one material selected from the group consisting of silicon nitride, silicon oxynitride, borate silicate glass, borophosphate silicate glass, phosphate silicate glass, ashed removable dielectric, low-K dielectric, heat removable organic polymer, silicon-containing antireflective material, and amorphous carbon.
optionally, the material of the initial dummy gate structure includes at least one of polysilicon, amorphous silicon, germanium, silicon germanium, and silicon carbon.
Optionally, before depositing the interlayer dielectric layer, an etching stop layer is deposited on the surfaces of the first virtual gate structure, the second virtual gate structure and the semiconductor substrate.
Compared with the prior art, the manufacturing method of the semiconductor device has the advantages that after the first virtual grid structure and the second virtual grid structure with different top surface heights are formed in the first area and the second area, the second virtual grid structure with the relatively higher top surface is replaced by the second metal grid structure by means of the protection effect of the interlayer dielectric layer on the first virtual grid structure with the relatively lower top surface, the second metal grid structure is flattened to the top surface of the first virtual grid structure, and then the first virtual grid structure is replaced by the first metal grid structure, so that the adverse effects such as process damage and the like caused by the metal grid structure forming process of a certain area on other areas can be avoided, the quality of the metal grid structure of each area is guaranteed, and the performance of a finally formed device is improved.
Drawings
Fig. 1A to 1C are schematic cross-sectional views of a device structure in a method of manufacturing a semiconductor device;
fig. 2 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 3A to 3G are schematic cross-sectional views of device structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
A Complementary Metal-Oxide-Semiconductor (CMOS) is one of the basic Semiconductor devices that constitute an integrated circuit. The complementary metal oxide semiconductor tube comprises: a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor. In the prior art, in order to control a short channel effect while reducing a Gate size, a back Gate (Gate Last) process is usually adopted to fabricate a FinFET device with a High K Metal Gate (HKMG), that is, a High K dielectric material is adopted to replace a conventional material such as silicon oxide and the like as a Gate dielectric layer of a transistor, and a Metal material is adopted to replace a conventional material such as polysilicon and the like as a Gate electrode layer of the transistor. Moreover, in order to adjust the threshold voltages of the PMOS transistor and the NMOS transistor, a work function layer (work function layer) is generally formed on the surface of the gate dielectric layers of the PMOS transistor and the NMOS transistor, and the work function layers of the PMOS transistor and the NMOS transistor generally adopt different work function adjusting materials, wherein the work function layer of the PMOS transistor needs to have a higher work function, and the work function layer of the NMOS transistor needs to have a lower work function, for example, the work function layer of the PMOS transistor is TiN, and the work function layer of the PMOS transistor is TiAL, so that a common manufacturing process of a FinFET device with a high-K metal gate structure includes the following steps:
Firstly, referring to fig. 1A, a semiconductor substrate 100 having an NMOS region I and a PMOS region II is provided, where fins 100a located in the NMOS region I and the PMOS region II, respectively, are formed on the semiconductor substrate 100, an isolation layer 100b whose top surface is lower than that of the fin 100a is formed between adjacent fins 100, the isolation layer 100b covers part of the side wall of each fin 100a, a polysilicon dummy gate structure (not shown) is formed on the side wall and the top surface of part of the fin 100a, a gate side wall 102 is formed on the side wall of the polysilicon dummy gate structure, embedded source and drain regions 103 are formed on the fin 100a on both sides of the polysilicon dummy gate structure and the gate side wall 102, and the top surface of the embedded source and drain regions 103 is usually higher than the top surface of the fin 100a and can introduce stress to the channel region;
then, with continued reference to fig. 1A, sequentially depositing an etching stop layer 104 (which may be silicon nitride) and a sufficiently thick interlayer dielectric layer 105 (which may be a low-K dielectric having a dielectric constant K lower than 4) on the surfaces of the fin 100a, the isolation layer 100b, the polysilicon dummy gate structure, the gate sidewall 102, and the embedded source-drain region 103, and performing top surface planarization on the interlayer dielectric layer 105 to expose the top surface of the polysilicon dummy gate structure, and then removing the polysilicon dummy gate structures in the NMOS region I and the PMOS region II by using an etching process, thereby forming a gate trench 101A in the NMOS region I and a gate trench 101b in the PMOS region II;
Then, referring to fig. 1B, a high-K gate dielectric layer (K may be greater than 7)106, a TiN (titanium nitride) layer 107, a planarization layer 108, and a patterned photoresist layer 109 are sequentially deposited on the surface of the interlayer dielectric layer 105 and the gate trenches 101a and 101B, where the patterned photoresist layer 109 can shield and protect the PMOS region II and expose the NMOS region I;
then, referring to fig. 1C, with the patterned photoresist layer 109 as a mask, sequentially etching the planarization layer 108 and the TiN layer 107 to remove the TiN layer 107 in the NMOS region I, and leaving the TiN layer 107 in the PMOS region II as a work function layer in the PMOS region II;
thereafter, the patterned photoresist layer 109 and the planarization layer 108 may be removed, a TiAl (titanium aluminum) layer (not shown) and a metal gate electrode layer (e.g., Al, W, etc.) may be sequentially deposited on the surface of the remaining TiN layer 107 and the surface of the high-K gate dielectric layer 106, the deposited metal gate electrode layer may have a thickness sufficient to fill the gate trenches 101a and 101b, and the top surface of the deposited metal gate electrode layer may be planarized to the top surface of the interlayer dielectric layer 105, thereby forming a high-K metal gate structure in the NMOS region I and the PMOS region II simultaneously.
however, in the above method, when the work function layer of the PMOS region II (i.e. the TiN layer 107) is formed, the NMOS region I needs to be exposed by a corresponding photolithography process and etching process to remove the work function layer for the PMOS region II covering the NMOS region I, when the device size is smaller, for example, reduced to 7nm, the adverse effect of the optical proximity effect on the photolithography process is large, so that the patterned photoresist layer 109 formed in fig. 1B will be tapered (taper), the critical dimension of the pattern will exceed the required range, thereby causing the problems of offset and over-etching of the etching process for removing the work function layer for the PMOS region II in the NMOS region I, which easily causes the damage to the fin at the bottom of the gate trench in fig. 1C (e.g. the fin in the 110a dashed-line frame region in fig. 1C) and the structure of the interface region between the NMOS region I and the PMOS region II (e.g. the structure in the 110B dashed-line frame region in fig. 1C), resulting in degradation and even failure of the final device.
According to the technical scheme, the virtual grid structures with different top surface heights are formed in different regions, the virtual grid structures in different regions can be replaced with the metal grid structures respectively without an additional photoetching process, adverse effects such as process damage and the like caused by the metal grid structure forming process in a certain region to other regions can be avoided, the quality of the metal grid structures in each region is ensured, and the performance of a finally formed device is improved.
the present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
referring to fig. 2, a method for manufacturing a semiconductor device includes the following steps:
S1, providing a semiconductor substrate with a first region and a second region;
s2, forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate, wherein the top surface of the first dummy gate structure is lower than the top surface of the second dummy gate structure;
s3, depositing interlayer dielectric layers on the surfaces of the first virtual gate structure, the second virtual gate structure and the semiconductor substrate, and flattening the top surface of the interlayer dielectric to the top surface of the second virtual gate structure;
S4, removing the second dummy gate structure to form a second gate trench, filling a second metal gate structure in the second gate trench, and planarizing the top surface of the second metal gate structure to the top surface of the first dummy gate structure;
And S5, removing the first dummy gate structure to form a first gate trench, and filling a first metal gate structure in the first gate trench.
Referring to fig. 3A, in step S1, the semiconductor substrate 300 is provided to provide a working platform for subsequent processes, which may be any semiconductor substrate known to those skilled in the art, such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a semiconductor substrate with a semiconductor epitaxial layer having a certain thickness on a base surface. In addition, when the semiconductor device to be formed is a FinFET device, a plurality of protruding fins (Fin, not shown, refer to 300a in fig. 1A) and an isolation layer (not shown, refer to 300b in fig. 1A) located between two adjacent fins and having a top surface flush with or lower than a top surface of the fins are formed in the semiconductor substrate 300, and the isolation layer further divides the semiconductor substrate 300 into a first region I and a second region II, wherein a step of providing the semiconductor substrate 300 includes:
Firstly, providing a semiconductor substrate, and forming a semiconductor epitaxial layer on the surface of the semiconductor substrate through an epitaxial growth process;
Then, etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the semiconductor substrate, thereby forming a plurality of fins;
and then, depositing an isolation material on the surfaces of the semiconductor substrate and the fins, and chemically and mechanically flattening the top surface of the isolation material until the top surface of the fins is exposed, so as to form an isolation layer with the top surface being flush with the top surface of the fins, wherein the isolation layer divides the semiconductor substrate into a first area I and a second area II, and further back-etching the isolation layer to a certain depth to enable the top surface of the fins to be higher than the top surface of the rest isolation layer, so that a metal gate structure surrounding the side walls and the top surface of the fins can be formed in the subsequent process, and the device performance is improved.
in other embodiments of the present invention, the step of providing the semiconductor substrate 300 may further include: firstly, forming a graphical hard mask layer with a plurality of grooves on the surface of a semiconductor substrate 300, then epitaxially growing a semiconductor epitaxial layer different from the semiconductor substrate 300 in the grooves, and removing the graphical hard mask layer, wherein the epitaxially grown semiconductor epitaxial layer is a raised fin on the surface of the semiconductor substrate 300; an isolation layer may then be formed in the trenches between the fins by a corresponding deposition and etch-back process. The first region I may be an NMOS region, and the second region II may be a PMOS region; or, the first region I may be a PMOS region, and the second region II may be an NMOS region; or the first region I and the second region II are both NMOS regions or PMOS regions, but work function layers in a metal gate structure formed later are different.
Referring to fig. 3A, in step S2, a dummy gate dielectric layer (not shown) may be formed on the surface of the semiconductor substrate 300 by a deposition process, a thermal oxidation process, or the like, and the dummy gate dielectric layer may be made of a material that may include silicon dioxide (SiO)2) (ii) a Then, sequentially depositing a dummy gate layer 301 and a hard mask layer 302 on the surface of the dummy gate dielectric layer, and forming a patterned photoresist layer (not shown) for defining the shape, position, etc. of the initial dummy gate structure 3020, wherein the hard mask layer 301 may be made of at least one material selected from the group consisting of silicon nitride, silicon oxynitride, borosilicate glass, borophosphate silicate glass, phosphate silicate glass, ashed removable dielectric, low-K dielectric, heat removable organic polymer, silicon-containing anti-reflective material, and amorphous carbon, and the dummy gate layer 302 may be made of a material selected from the group consisting of sige polysilicon, amorphous silicon, germanium, and amorphous carbonat least one of silicon and carbon; then, with the patterned photoresist layer as a mask, sequentially etching the hard mask layer 302, the dummy gate layer 301 and the dummy gate dielectric layer, so as to form initial dummy gate structures 3020 located in the first region I and the second region II, respectively, on the semiconductor substrate 300, where top surfaces of the initial dummy gate structures 3020 in the first region I and the second region II are flush (i.e., have the same height), and each initial dummy gate structure 3020 includes a dummy gate dielectric layer, a dummy gate layer 302 and a hard mask layer 301, which are sequentially stacked on the semiconductor substrate 300, and when the semiconductor substrate 300 has a fin, the initial dummy gate structure 3020 covers sidewalls and a top surface of a partial region (i.e., a channel region) of the fin;
with continuing reference to fig. 1A and fig. 3A, in step S2, a gate sidewall spacer (not shown, refer to 102 in fig. 1A) is formed on a sidewall of each of the initial dummy gate structures 3020 by a sidewall spacer process, so as to protect the sidewall of the initial dummy gate structure 3020, prevent the sidewall of the initial dummy gate structure 3020 from being damaged in the subsequent source/drain region manufacturing process, and protect the sidewall of the subsequent interlayer dielectric layer from being damaged in the removal process of the initial dummy gate structure 3020; the side wall process is a commonly used manufacturing process in the art, and the specific process is not described herein any more, and at this time, the gate side wall covers the side walls of the virtual gate dielectric layer, the virtual gate layer and the hard mask layer, and the gate side wall may be a single-layer structure or a stacked structure, and the material of the gate side wall includes at least one of silicon oxide, silicon nitride and silicon oxynitride;
with continuing reference to fig. 1A and fig. 3A, in step S2, an ion implantation process or an embedded source-drain epitaxy process may be subsequently used to fabricate source-drain regions in the semiconductor substrate 300 on both sides of the gate sidewall and the initial dummy gate structure 3020, where the process of fabricating the embedded source-drain regions includes: an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, a furnace tube process (burn) or the like may be first adopted to deposit a mask layer (not shown) for etching source and drain grooves on the surfaces of the semiconductor substrate 300, the gate side wall and the initial virtual gate structure 3020, and the mask layer may shield and protect other areas, the initial virtual gate structure 3020 and the gate side wall when the source and drain grooves are formed by subsequently etching the initial virtual gate structure 3020 and the semiconductor substrate 300 on both sides of the gate side wall; then, forming a patterned photoresist (not shown) on the surface of the mask layer through photoresist coating, exposing, developing and other photoetching processes, wherein the pattern in the patterned photoresist defines a region of the semiconductor substrate 300 to be etched to form a source-drain groove; and then, with the patterned photoresist as a mask, etching the mask layer and the semiconductor substrate 300 by adopting an etching process of wet etching, dry etching or dry etching plus wet etching to form a source-drain groove, wherein the side wall of the source-drain groove and the surface of the semiconductor substrate are in an L shape, a C shape or a sigma shape, and then, the patterned photoresist and the mask layer can be removed by an oxygen ashing process. In other embodiments of the present invention, the initial dummy gate structure 3020 and the gate sidewall may also be directly used as masks to etch the semiconductor substrate (e.g., fin) on both sides of the initial dummy gate structure 3020 and the gate sidewall, so as to form the source/drain groove 303; then, a suitable stress layer may continue to be epitaxially grown on the surface of the source and drain recesses through a selective epitaxial growth process, in this embodiment, when the semiconductor substrate 300 is a silicon substrate and the device to be formed in the first region I is an NMOS transistor, the material of the stress layer epitaxially grown in the source and drain recesses in the first region I may be at least one selected from silicon, silicon carbon, carbon-silicon-phosphorus, carbon-silicon-arsenic, carbon-silicon-antimony, carbon-silicon-phosphorus-arsenic, carbon-silicon-phosphorus-antimony, and carbon-silicon-phosphorus-arsenic, and when the device to be formed in the second region II is a PMOS transistor, the material of the stress layer epitaxially grown in the source and drain recesses in the second region II may be at least one selected from silicon, germanium, silicon-germanium-boron, gallium, silicon germanium-indium, silicon germanium-boron-gallium and boron-gallium-indium, so that lattice mismatch may be generated, and further introduce a greater stress into the channel, which may enhance carrier mobility, the channel control capability of a subsequently formed metal gate structure is improved, the leakage current is reduced, the SCE effect and the RSCE effect are reduced, and the performance of the device is further improved. It should be noted that, when the semiconductor substrate 300 has fins, source and drain regions are formed on the fins on both sides of the initial dummy gate structure 3020.
referring to fig. 3B, in step S2, the hard mask layer in the initial dummy gate structure 3020 in the first region I is etched back, so that the top surface of the hard mask layer in the first region I is lower than the top surface of the hard mask layer in the second region II, thereby forming a first dummy gate structure 3021 in the first region I and a second dummy gate structure 3022 in the second region II, that is, the first dummy gate structure 3021 includes a sequentially stacked dummy gate dielectric layer, a dummy gate layer 301a and a hard mask layer 302a, the second dummy gate structure 3022 includes a sequentially stacked dummy gate dielectric layer, a dummy gate layer 301B and a hard mask layer 302B, and the top surfaces of the dummy gate dielectric layer of the first dummy gate structure 3021 and the dummy gate layer of the second dummy gate structure 3022 are flush with each other, and the top surfaces of the dummy gate layer 301a and the dummy gate layer 301B are flush with each other, and the top surface of the hard mask layer 302a is lower than the hard mask layer 302 b. The method for forming the first dummy gate structure 3021 and the second dummy gate structure 3022 can reduce the damage to the semiconductor substrate 300 when the initial dummy gate structure 3020 is etched back as much as possible, and can directly manufacture the first dummy gate structure 3021 and the second dummy gate structure 3022 having different top heights by using the original hard mask layer when the initial dummy gate structure 3020 is formed, which is a simple process.
If the gate side wall in the first region I also covers the side wall of the hard mask layer in the first region I, the gate side wall with the same height in the first region I can be etched back while the hard mask layer in the first region I is etched back, and the etching selection ratio of the gate side wall to the hard mask layer is close to 1: 1; or, after the hard mask layer in the first region I is etched back, the gate sidewall in the first region I is trimmed to the top surface of the hard mask layer in the first region I by a suitable process such as wet etching, so as to provide a relatively large and flat process window and process surface for a subsequent process.
in step S2 of other embodiments of the present invention, when the material of the dummy gate layer is suitable, the remaining hard mask layer 302 in fig. 3A may be removed without using the hard mask layer 302 after the etching process for forming the initial dummy gate structure is completed, so as to directly etch back the dummy gate layer in the first region I, and obtain the first dummy gate structure and the second dummy gate structure with different top heights, which includes the following specific processes: first, a dummy gate dielectric layer (not shown) and a dummy gate layer may be sequentially covered on the surface of the semiconductor substrate 300; then, etching the virtual gate layer and the virtual gate dielectric layer until reaching the surface of the semiconductor substrate 300, so as to form initial virtual gate structures respectively located in the first region I and the second region II on the semiconductor substrate 300, where the initial virtual gate structures include the virtual gate layer and the virtual gate dielectric layer; next, the dummy gate layer in the first region I may be directly etched back, so that the top surface of the dummy gate layer in the first region I is lower than the top surface of the dummy gate layer in the second region II, thereby forming a first dummy gate structure 3021 in the first region I and a second dummy gate structure 3022 in the second region II. In addition, before or after the virtual gate layer is etched back, gate side walls may be formed on the side walls of the initial virtual gate structures, and source and drain regions may be formed on the gate side walls and the semiconductor substrate 300 outside the initial virtual gate structures. The first dummy gate structure 3021 and the second dummy gate structure 3022 formed under this method each include a dummy gate dielectric layer and a dummy gate layer stacked in this order, except that the top surface of the dummy gate layer of the first dummy gate structure 3021 is lower than the top surface of the dummy gate layer of the second dummy gate structure 3022.
In step S2 of other embodiments of the present invention, due to the problem of the material of the virtual gate layer and the hard mask layer, the depth of the back-etched virtual gate layer or hard mask layer may not be precisely controlled, and/or when the surface of the semiconductor substrate 300 is easily damaged when the back-etched virtual gate layer or hard mask layer is back-etched, after the etching process for forming the initial virtual gate structure is completed, a gate sidewall is formed on the sidewall of each initial virtual gate structure, and source and drain regions are formed on the gate sidewall and the semiconductor substrate 300 on both sides of the initial virtual gate structure, and then the previous hard mask layer is removed, and a new hard mask layer is covered on the exposed surfaces of the semiconductor substrate 300, the virtual gate layer, and the virtual gate dielectric layer; then, patterning the hard mask layer through an etching process, and only reserving a new hard mask layer on the top surface of the virtual grid structure; then, the new hard mask layer in the first region I is etched back, so that the top surface of the new hard mask layer in the first region I is lower than the top surface of the new hard mask layer in the second region II, thereby forming a first dummy gate structure 3021 in the first region I and a second dummy gate structure 3022 in the second region II. In this way, the first dummy gate structure 3021 and the second dummy gate structure 3022 both include a dummy gate dielectric layer, a dummy gate layer, and a new hard mask layer, the top surfaces of the dummy gate dielectric layer of the first dummy gate structure 3021 and the dummy gate dielectric layer of the second dummy gate structure 3022 are flush, the top surfaces of the dummy gate layer of the first dummy gate structure 3021 and the dummy gate layer of the second dummy gate structure 3022 are flush, and the top surface of the new hard mask layer of the first dummy gate structure 3021 is lower than the top surface of the new hard mask layer of the second dummy gate structure 3022.
Referring to fig. 3C, in step S3, an etching stop layer (not shown) may be formed on the surfaces of the semiconductor substrate 300, the first dummy gate structure 3021 and the second dummy gate structure 3022 by a physical vapor deposition or a chemical vapor deposition process to protect the source/drain regions and other regions of the semiconductor substrate 300; then, an interlayer dielectric (ILD) layer 303 with a sufficient thickness may be covered on the surfaces of the semiconductor substrate 300, the first dummy gate structure 3021 and the second dummy gate structure 3022 by a process such as physical vapor deposition, chemical vapor deposition or spin coating, and the like, where the deposition thickness of the interlayer dielectric layer 303 on the surface of the semiconductor substrate 300 is not less than the height of the second dummy gate structure 3022 on the surface of the semiconductor substrate 300; next, a top surface of the interlayer dielectric layer 303 is chemically and mechanically planarized (CMP, or chemical and mechanical polishing) until a top surface of the second dummy gate structure 3022 is exposed, which in fig. 3C is the top surface of the hard mask layer 302 b. The material of the interlayer dielectric layer 303 needs to be selected according to the materials of the first dummy gate structure 3021 and the second dummy gate structure 3022, as long as the requirement that the first dummy gate structure 3021 and the second dummy gate structure 3022 have a higher etching selectivity when the first dummy gate structure 3021 and the second dummy gate structure 3022 are subsequently removed can be met, for example, the material can be silicon dioxide, silicon oxynitride, a low-K dielectric with a dielectric constant K lower than 4, an Organic Dielectric (ODL), spin-on carbon (SOC), or an anti-reflective dielectric (e.g., an anti-reflective dielectric containing silicon, a Si-ARC, or other bottom anti-reflective dielectric BARC).
referring to fig. 3C, fig. 3D and fig. 3E, in step S4, first, a suitable removing process may be selected according to the materials of the hard mask layer 302b, the dummy gate layer 301b and the dummy gate dielectric layer to remove the second dummy gate structure 3022, for example, the hard mask layer 302b is removed by a dry etching process, and then the dummy gate layer 301b and the dummy gate dielectric layer are removed by a wet etching process, so as to form a second gate trench 303a at the position of the second dummy gate structure; then, a high-K gate dielectric layer (not shown), a work function layer (not shown) and a metal electrode layer (not shown) are sequentially filled in the second gate trench 303a to form a second metal gate structure 304a filled in the second gate trench 303 a; then, the top surface of the second metal gate structure 304a is subjected to chemical mechanical planarization, that is, the top surface of the metal gate electrode layer is subjected to chemical mechanical planarization until the top surface of the first dummy gate structure 3021 is exposed, and at this time, the excess high-K gate dielectric layer, the work function layer, the metal gate electrode layer, and the like above the first dummy gate structure 3021 are removed. Wherein the high-K gate dielectric layer may be formed by Atomic Layer Deposition (ALD), so as to ensure that the deposited high-K gate dielectric layer has excellent coverage (conformability) on the sidewall and bottom of the second gate trench 302a1, the material thereof may be one or more of hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, etc., the work function layer may be formed by Radio Frequency Physical Vapor Deposition (RFPVD), the material thereof may be one or more of Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, and TiAlN, the TiN is commonly used as the work function layer of the P-type metal oxide semiconductor (PMOS), the TiAl is commonly used as the work function layer of the N-type metal oxide semiconductor (NMOS), the metal gate electrode layer may be deposited by vacuum evaporation, sputtering, electroplating, or chemical vapor deposition, and the like, the material thereof may be Al, Cu, Ag, Au, Ag, Au, hf, and zr, and the like, One or more of Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi. In addition, before depositing the work function layer, at least one metal blocking layer for blocking the metal gate electrode layer and the diffusion of the metal in the work function metal layer into the high-K gate dielectric layer may be formed on the surface of the high-K gate dielectric layer, and after depositing the work function layer and before depositing the metal gate electrode layer, at least one metal blocking layer for blocking the downward diffusion of the metal in the metal gate electrode layer may be formed on the surface of the work function layer.
Referring to fig. 3E to fig. 3G, in step S5, when the material of the first dummy gate structure 3021 is the same as the material of the second dummy gate structure 3022, the first dummy gate structure 3021 may be removed by the process of removing the second dummy gate structure 3022 in step S4 to form the first gate trench 303b, which is not repeated herein; then, a high-K gate dielectric layer (not shown), another work function layer (not shown) and a metal electrode layer (not shown) are sequentially filled in the first gate trench 303b to form a first metal gate structure 304b filled in the first gate trench 303 b; thereafter, the top surface of the first metal gate structure 304b may be chemically and mechanically planarized to provide a flat process window for subsequent processes.
In summary, in the manufacturing method of the semiconductor device of the present invention, the first dummy gate structure and the second dummy gate structure with different top heights are formed in the first region and the second region, then the first dummy gate structure with a relatively lower top height is protected by the interlayer dielectric layer, the second dummy gate structure is replaced by the second metal gate structure, and then the height of the top surface of the second dummy gate structure is lowered by the chemical mechanical planarization process again until the first dummy gate structure is exposed, so that the first dummy gate structure can be replaced by the first metal gate structure, therefore, the method of the present invention avoids the original photolithography process and etching process when forming different work function layers, so that the forming processes of the first metal gate structure and the second metal gate structure can be independent from each other, and no additional process damage is caused to the regions of the semiconductor substrate where they are located, the quality of the formed first metal gate structure and the second metal gate structure can be ensured, and the performance of the finally manufactured semiconductor device is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. a method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate having a first region and a second region;
forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate, wherein the top surface of the first dummy gate structure is lower than the top surface of the second dummy gate structure;
Depositing an interlayer dielectric layer on the surfaces of the first virtual grid structure, the second virtual grid structure and the semiconductor substrate, and flattening the top surface of the interlayer dielectric to the top surface of the second virtual grid structure;
removing the second dummy gate structure to form a second gate trench, filling a second metal gate structure in the second gate trench, and planarizing the top surface of the second metal gate structure to the top surface of the first dummy gate structure;
And removing the first dummy gate structure to form a first gate trench, and filling a first metal gate structure in the first gate trench.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first region is an NMOS region, and the second region is a PMOS region; or, the first region is a PMOS region, and the second region is an NMOS region.
3. the method of manufacturing the semiconductor device according to claim 2, wherein the first metal gate structure and the second metal gate structure each comprise a work function layer and a metal gate electrode layer, wherein the work function layers of the first metal gate structure and the second metal gate structure are different in material.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate comprises: a semiconductor substrate; a plurality of fins respectively located on the surface of the semiconductor substrate in the first region and the second region; and the isolation layer is positioned on the surface of the semiconductor substrate, covers part of the side wall of each fin, and the upper surface of the isolation layer is lower than the top surface of each fin.
5. the method of manufacturing a semiconductor device according to claim 4, wherein the first dummy gate structure crosses over the fin of the first region and covers a sidewall and a top surface of a partial region of the fin of the first region; the second dummy gate structure crosses over the fins of the second region and covers the sidewalls and the top surface of a partial region of the fins of the second region.
6. The method for manufacturing the semiconductor device according to claim 1, wherein the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate comprises:
sequentially forming a virtual gate dielectric layer, a virtual gate layer and a hard mask layer on the semiconductor substrate so as to form initial virtual gate structures in the first area and the second area on the semiconductor substrate, wherein the initial virtual structures comprise the virtual gate dielectric layer, the virtual gate layer and the hard mask layer;
and etching back the hard mask layer in the initial virtual gate structure in the first region to enable the top surface of the hard mask layer in the first region to be lower than the top surface of the hard mask layer in the second region, thereby forming a first virtual gate structure in the first region and a second virtual gate structure in the second region.
7. The method for manufacturing the semiconductor device according to claim 1, wherein the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate comprises:
forming an initial dummy gate structure on the semiconductor substrate, wherein the initial dummy gate structure is positioned in the first region and the second region;
forming a hard mask layer on the initial virtual grid structure and the surface of the semiconductor substrate;
Patterning the hard mask layer, and only reserving the hard mask layer on the top surface of the initial virtual grid structure;
And etching back the hard mask layer in the first area to enable the top surface of the hard mask layer in the first area to be lower than that of the hard mask layer in the second area, thereby forming a first virtual grid structure in the first area and a second virtual grid structure in the second area.
8. The method for manufacturing the semiconductor device according to claim 1, wherein the step of forming a first dummy gate structure located in the first region and a second dummy gate structure located in the second region on the semiconductor substrate comprises:
Forming an initial dummy gate structure on the semiconductor substrate, wherein the initial dummy gate structure is positioned in the first region and the second region;
And etching back the initial dummy gate structure in the first region to make the top surface of the dummy gate structure in the first region lower than the top surface of the dummy gate structure in the second region, thereby forming a first dummy gate structure in the first region and a second dummy gate structure in the second region.
9. The method for manufacturing the semiconductor device according to any one of claims 6 to 8, wherein after the initial dummy gate structures in the first region and the second region are formed on the semiconductor substrate, gate spacers are formed on sidewalls of the initial dummy gate structures.
10. The method for manufacturing the semiconductor device according to claim 9, wherein before or after the gate side wall is formed, a source and drain region is formed in the semiconductor substrate on both sides of the dummy gate structure by using an ion implantation process or an embedded source and drain epitaxy process.
11. the method for manufacturing a semiconductor device according to claim 6 or 7, wherein a material of the hard mask layer is at least one selected from the group consisting of silicon nitride, silicon oxynitride, borate silicate glass, borophosphate silicate glass, phosphate silicate glass, ashed removable dielectric, low-K dielectric, heat removable organic polymer, silicon-containing antireflective material, and amorphous carbon.
12. The method for manufacturing a semiconductor device according to any one of claims 6 to 8, wherein a material of the initial dummy gate structure includes at least one of polysilicon, amorphous silicon, germanium, silicon germanium, and silicon carbon.
13. The method of manufacturing a semiconductor device according to claim 1, wherein an etch stop layer is deposited on the surfaces of the first dummy gate structure, the second dummy gate structure, and the semiconductor substrate before the interlayer dielectric layer is deposited.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103854980A (en) * | 2012-11-29 | 2014-06-11 | 中国科学院微电子研究所 | Method for forming semiconductor-device replacement gate and method for manufacturing semiconductor device |
| US8987083B1 (en) * | 2014-03-10 | 2015-03-24 | Globalfoundries Inc. | Uniform gate height for semiconductor structure with N and P type fins |
| CN106206441A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The preparation method of metal gates |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103854980A (en) * | 2012-11-29 | 2014-06-11 | 中国科学院微电子研究所 | Method for forming semiconductor-device replacement gate and method for manufacturing semiconductor device |
| US8987083B1 (en) * | 2014-03-10 | 2015-03-24 | Globalfoundries Inc. | Uniform gate height for semiconductor structure with N and P type fins |
| CN106206441A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The preparation method of metal gates |
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