CN110570888A - Static memory cell, array and device - Google Patents

Static memory cell, array and device Download PDF

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Publication number
CN110570888A
CN110570888A CN201810577974.4A CN201810577974A CN110570888A CN 110570888 A CN110570888 A CN 110570888A CN 201810577974 A CN201810577974 A CN 201810577974A CN 110570888 A CN110570888 A CN 110570888A
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China
Prior art keywords
pull
transistor
transistors
gate
pass
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CN201810577974.4A
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Chinese (zh)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201810577974.4A priority Critical patent/CN110570888A/en
Publication of CN110570888A publication Critical patent/CN110570888A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a static storage unit, an array and a device, wherein two pull-up transistors which are arranged in a diagonal line are arranged in a pull-up transistor group, pull-down transistor groups are positioned at two sides of the pull-up transistor group, a transmission gate transistor group is positioned at the outer side of the pull-down transistor group, the grids of a plurality of pull-down transistors in the pull-down transistors are arranged in a row, and the grids of a plurality of transmission gate transistors in the transmission gate transistor group are arranged in a row.

Description

Static memory cell, array and device
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a static memory cell, an array and a device.
Background
A Static Random Access Memory (SRAM) is one of the memories, has the advantages of high speed, low power consumption, compatibility with standard processes, and the like, and is widely applied to the fields of computers, personal communications, consumer electronics (smart cards, digital cameras, multimedia players), and the like. With the continuous development of semiconductor process technology, process nodes are gradually reduced, a multi-gate device is widely concerned, and a fin field effect transistor (FinFET) is a common multi-gate device, is widely applied to transistors of an SRAM (static random access memory) and can effectively improve the performance of the SRAM.
The read-write speed of the existing fin field effect transistor needs to be improved.
Disclosure of Invention
The invention aims to provide a static memory unit, an array and a device, which are used for improving the read-write speed of the conventional static memory unit, array and device.
In order to achieve the above object, the present invention provides a static memory cell formed on a substrate, the static memory cell comprising a pull-up transistor group, two pull-down transistor groups and two transfer gate transistor groups;
The pull-up body tube group comprises two pull-up transistors, and grid electrodes of the two pull-up transistors are arranged on the substrate in a diagonal line manner; the pull-down transistor group comprises a plurality of pull-down transistors, and the grid electrodes of the pull-down transistors are arranged in a row; the transmission gate transistor group comprises a plurality of transmission gate transistors, and the gates of the transmission gate transistors are arranged in a column;
The two pull-down body tube groups are respectively positioned at the outer sides of the pull-up body tube groups, and the two transmission gate transistor groups are respectively positioned at the outer sides of the two pull-down body tube groups.
Optionally, the number of pull-down transistors in the pull-down transistor group is the same as the number of pass-gate transistors in the pass-gate transistor group.
optionally, the two pull-down transistor groups are respectively a first pull-down transistor group and a second pull-down transistor group, the two transmission gate transistor groups are respectively a first transmission gate transistor group and a second transmission gate transistor group, the first pull-down transistor group is adjacent to the first transmission gate transistor group, and the second pull-down transistor group is adjacent to the second transmission gate transistor group.
Optionally, a first fin structure, a second fin structure, a third fin structure, a fourth fin structure, a fifth fin structure and a sixth fin structure are formed on the substrate and arranged side by side in sequence, gates of two pull-up transistors in the pull-up body tube group are located on the third fin structure and the fourth fin structure respectively, gates of pull-down transistors in the first pull-down body tube group and the second pull-down body tube group are located on the second fin structure and the fifth fin structure respectively, and gates of pass-gate transistors in the first pass-gate transistor group and the second pass-gate transistor group are located on the first fin structure and the sixth fin structure respectively.
Optionally, the gates of the pull-down transistors in the pull-down transistor group and the gates of the transfer gate transistors in the transfer gate transistor group are arranged in a row, and the gates of the pull-down transistors in the pull-down transistor group and the gates of the transfer gate transistors in the transfer gate transistor group are arranged in multiple rows.
optionally, gates of a plurality of transmission gate transistors in the transmission gate transistor group are connected and then connected to a word line; the sources of a plurality of transmission gate transistors in the transmission gate transistor group are connected and then connected with a bit line or a complementary bit line.
Optionally, the two pull-up transistors are a first pull-up transistor and a second pull-up transistor, the first pull-up transistor is adjacent to the first pull-down transistor group, and the second pull-up transistor is adjacent to the second pull-down transistor group.
Optionally, after being connected, gates of a plurality of pull-down transistors in the first pull-down transistor group are connected to a gate of the first pull-up transistor; the grid electrodes of a plurality of pull-down transistors in the second pull-down transistor group are connected and then connected with the grid electrode of the second pull-up transistor; and the sources of a plurality of pull-down transistors in the first pull-down body tube group and the second pull-down body tube group are connected and then are connected with a ground wire.
Optionally, the sources of the first pull-up transistor and the second pull-up transistor are connected and then connected to a power supply voltage.
optionally, drains of a plurality of pass-gate transistors in the pass-gate transistor group are all connected, drains of a plurality of pull-down transistors in the pull-down transistor group are all connected, a drain of a pass-gate transistor in the first pass-gate transistor group is connected to a drain of a pull-down transistor in the first pull-down transistor group and a gate of the first pull-up transistor, and a drain of a pass-gate transistor in the second pass-gate transistor group is connected to a drain of a pull-down transistor in the second pull-down transistor group and a gate of the second pull-up transistor.
Optionally, the drain of the first pull-up transistor is connected to the drain of the pull-down transistor in the first pull-down body tube group, and the drain of the second pull-up transistor is connected to the drain of the pull-down transistor in the second pull-down body tube group.
Optionally, the pull-up transistor is a PMOS field effect transistor, and the pull-down transistor and the transmission gate transistor are NMOS field effect transistors.
The invention also provides a static storage array which comprises a plurality of static flash memory units, and two adjacent static flash memory units are distributed in a mirror symmetry mode.
Optionally, the static memory array further includes a word line, a bit line, a complementary bit line, a power voltage, and a ground line, and gates of a plurality of pass gate transistors in the pass gate transistor group of each static flash memory cell are connected to the word line; the source electrodes of a plurality of transmission gate transistors in the transmission gate transistor group of each static flash memory unit are connected and then connected with the bit line or the complementary bit line; the source electrode of the pull-up transistor of each static flash memory unit is connected with the power supply voltage; and the sources of a plurality of pull-down transistors in the pull-down body tube group of each static flash memory unit are connected and then are connected with the ground wire.
the invention also provides a static memory device which comprises the static memory array.
In the static storage unit, the array and the device provided by the invention, the pull-up transistor group is provided with two pull-up transistors which are arranged in a diagonal line, the pull-down transistor groups are positioned at two sides of the pull-up transistor group, the transmission gate transistor group is positioned at the outer side of the pull-down transistor group, the grids of a plurality of pull-down transistors in the pull-down transistors are arranged in a row, and the grids of a plurality of transmission gate transistors in the transmission gate transistor group are arranged in a row, so that the pull-down transistors and the transmission gate transistors can be conveniently distinguished, and the transmission gate transistors can be independently selected and operated to perform special operation (such as ion injection) on the source electrode, the drain electrode or the grid electrode of the transmission gate transistors, so as to increase the read-write current of the transmission gate transistors and further increase the read-write speed of the static storage unit.
Drawings
FIG. 1 is a schematic diagram of a distribution of static memory cells;
FIG. 2 is a schematic diagram of a static memory cell;
FIG. 3 is a schematic diagram of a static memory array;
FIG. 4 is a distribution diagram of static memory cells according to an embodiment;
FIG. 5 is a schematic structural diagram of a static memory cell according to an embodiment;
FIG. 6 is a schematic diagram of another structure of a static memory cell according to an embodiment;
FIG. 7 is a schematic diagram of a static memory array according to an embodiment;
The transistor comprises a PU-pull-up transistor, a PD-pull-down transistor, a PG-transmission gate transistor, a FIN-FIN structure, an M1-first metal layer, an M2-second metal layer, an M3-third metal layer, an M4-fourth metal layer, an M5-fifth metal layer, an M6-sixth metal layer, an M7-seventh metal layer, a VDD-power voltage, a VSS-ground line, a BL-bit line, a BLB-complementary bit line and a WL-word line.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, a distribution diagram of a 6T static memory unit is shown in fig. 1, where the 6T static memory unit includes two pull-up transistors PU, two pull-down transistors PD and two transmission gate transistors PG, the two pull-up transistors PU are distributed diagonally, the two pull-down transistors PD are distributed diagonally, and the two transmission gate transistors PG are also distributed diagonally, where the two pull-up transistors PU, the two pull-down transistors PD and the two transmission gate transistors PG form two groups of same structures, each group of structures includes the pull-up transistor PU, the pull-down transistor PD and the transmission gate transistor PG, and the two groups of structures are centrosymmetric.
Referring to fig. 2, which is a schematic structural diagram of the 6T static memory cell, as shown in fig. 2, each of the pass gate transistor PG, the pull-up transistor PU and the pull-down transistor PD is located on a substrate, a plurality of FIN structures FIN are formed on the substrate and arranged side by side, gates of the pass gate transistor PG, the pull-up transistor PU and the pull-down transistor PD cross over the FIN structures FIN, and a source and a drain are respectively formed on the FIN structures FIN at two ends of the gate of each transistor, wherein the gate of the pass gate transistor PG is connected to a word line WL, the source is connected to a bit line BL (one is connected to a bit line BL, the other is connected to a bit line BLB, the bit line BL is complementary to the bit line BLB), the gate of the pull-up transistor PU is connected to the adjacent pull-down transistor PD, and the source of the pull-up transistor PU is connected to a power supply voltage VDD, the source of the pull-down transistor PD is connected to a ground line VSS, the drains of the pull-up transistor PU, the pull-down transistor PD and the pass-gate transistor PG in each group of structures are connected through a first metal layer M1, and the gate of the pull-up transistor PU is connected to the drains of the pull-down transistor PD and the pass-gate transistor PG through a second metal layer M2.
The inventor finds that performing a special operation (e.g., ion implantation) on the source, the drain, or the gate of the pass-gate transistor PG alone can increase the read/write current thereof, and thus increase the read/write speed of the 6T static memory cell, please refer to fig. 3, in the 6T static memory array formed by the 6T static memory cell, the pass-gate transistor PG and the pull-down transistor PD are arranged in a staggered manner, if the pass-gate transistor PG is to be operated alone, a mask is required to separate the pass-gate transistor PG from the pull-down transistor PD and the pull-up transistor PU, but since the area of the 6T static memory cell is very small, it is difficult to select the pass-gate transistor PG to operate using the mask without affecting the pull-up transistor PU and the pull-down transistor PD. In addition, the pass gate transistor PG and the pull-down transistor PD of the static memory cell have a plurality of FIN structures FIN, and the FIN structure FIN near the pull-up transistor PU may be influenced by the pressure at the side of the pull-up transistor PU or other factors, so that the electrical performance of the pass gate transistor PG may be deteriorated.
In view of the above, the present embodiment provides a static memory cell, as shown in fig. 4, formed on a substrate, the static memory cell including a pull-up body group, two pull-down body groups, and two transfer gate transistor groups; the pull-up body tube group comprises two pull-up transistors PU, and grid electrodes of the two pull-up transistors PU are arranged on the substrate in a diagonal line manner; the pull-down transistor group comprises a plurality of pull-down transistors PD, and the grid electrodes of the pull-down transistors PD are arranged in a row; the transmission gate transistor group comprises a plurality of transmission gate transistors PG, and the grid electrodes of the transmission gate transistors PG are arranged in a column; the two pull-down body tube groups are respectively positioned at the outer sides of the pull-up body tube groups, and the two transmission gate transistor groups are respectively positioned at the outer sides of the two pull-down body tube groups.
with continued reference to fig. 4, each of the pull-down transistor groups has a plurality of pull-down transistors PD arranged in parallel, each of the pull-down transistors PD is connected in parallel, each of the pass-gate transistor groups has a plurality of pass-gate transistors PG arranged in parallel, each of the pass-gate transistors PG is connected in parallel, in this embodiment, each of the pull-down transistor groups has two pull-down transistors PD arranged in parallel, each of the pass-gate transistor groups has two pass-gate transistors PG arranged in parallel, the number of pull-down transistors PD in each of the pull-down transistor groups matches the number of pass-gate transistors PG in each of the pass-gate transistor groups, in other embodiments, the number of pass-gate transistors PG in each of the pass-gate transistor groups and the number of pass-gate transistors PG in each of the pass-gate transistor groups may be other, for example, 3, 4, etc., and the present embodiment is not limited. The pull-up transistor PU is a PMOS field effect transistor, and the pull-down transistor PD and the transmission gate transistor PG are NMOS field effect transistors.
For convenience of description, in this embodiment, the two pull-down transistor groups are a first pull-down transistor group and a second pull-down transistor group (two groups of pull-down transistor groups on the left and right in fig. 4), respectively, and the two transfer gate transistor groups are a first transfer gate transistor group and a second transfer gate transistor group (two groups of transfer gate transistor groups on the left and right in fig. 4), respectively, the first pull-down transistor group is adjacent to the first transfer gate transistor group, and the second pull-down transistor group is adjacent to the second transfer gate transistor group. Two pull-up transistors PU in the pull-up transistor group are respectively a first pull-up transistor and a second pull-up transistor, the first pull-up transistor is adjacent to the first pull-down transistor group, and the second pull-up transistor is adjacent to the second pull-down transistor group.
Further, in the present embodiment, as shown in fig. 5, a plurality of FIN structures FIN arranged side by side are formed on the substrate, and a first FIN structure, a second FIN structure, a third FIN structure, a fourth FIN structure, a fifth FIN structure and a sixth FIN structure are formed on the substrate and sequentially arranged side by side from left to right, gates of the first pull-up transistor and the second pull-up transistor are respectively located on the third FIN structure and the fourth FIN structure, gates of the pull-down transistors in the first pull-down transistor group and the second pull-down transistor group are respectively located on the second FIN structure and the fifth FIN structure, and gates of the pass-gate transistors in the first pass-gate transistor group and the second pass-gate transistor group are respectively located on the first FIN structure and the sixth FIN structure. And a plurality of groups of source electrodes and drain electrodes are formed in each FIN structure FIN, and each group of source electrodes and drain electrodes are positioned on two sides of each grid electrode and are symmetrically arranged.
The gate of one of the pull-down transistors in the set of pull-down transistors is arranged in a row with the gate of one of the pass-gate transistors in the set of pass-gate transistors, and the gates of a plurality of pull-down transistors in the set of pull-down transistors are arranged in a plurality of rows with the gates of the pass-gate transistors of a plurality of the set of pass-gate transistors, for example: the first pass gate transistor PG in the pass gate transistor group and the first pull-down transistor PD in the pull-down transistor group are arranged in a row, the second pass gate transistor PG in the pass gate transistor group and the second pull-down transistor PD in the pull-down transistor group are arranged in a row …, and the last pass gate transistor PG in the pass gate transistor group and the last pull-down transistor PD in the pull-down transistor group are arranged in a row.
Further, sources of pass gate transistors PG in the pass gate transistor groups are connected and then connected to a bit line BL or a complementary bit line BLB (in this embodiment, sources of pass gate transistors PG in a first pass gate transistor group are connected and then connected to the complementary bit line BLB, sources of pass gate transistors PG in a second pass gate transistor group are connected and then connected to the bit line BL), drains of pass gate transistors PG in the pass gate transistor groups are connected through a seventh metal layer M7, gates of pass gate transistors PG in the pass gate transistor groups are connected through a fifth metal layer M5, and gates of pass gate transistors PG in the first pass gate transistor group and the second pass gate transistor group are connected and then connected to a word line WL.
With continued reference to fig. 5, the gates of the pull-down transistors PD in the first pull-down transistor group are connected to the gate of the first pull-up transistor; the grid electrodes of a plurality of pull-down transistors PD in the second pull-down transistor group are connected and then connected with the grid electrode of the second pull-up transistor, the sources of a plurality of pull-down transistors PD in the first pull-down body tube group and the second pull-down body tube group are connected and then connected with a ground wire VSS, the drains of the pull-down transistors PD in the pull-down body tube group are connected and then connected with the drain of the adjacent pull-up transistor PU through a fourth metal layer M4 (the drains of the pull-down transistors PD in the first pull-down body tube group are connected and then connected with the drain of the first pull-up transistor PU through a fourth metal layer M4, the drains of the pull-down transistors PD in the second pull-down body tube group are connected and then connected with the drain of the second pull-up transistor PU through a fourth metal layer M4), meanwhile, the fourth metal layer M4 also connects the drain of each of the pull-down transistors PD of the same group. Further, the gates of the pull-down transistors PD in the pull-down body tube group are all connected, as shown in fig. 5, the gates of the pull-down transistors PD in the pull-down body tube group are connected through a sixth metal layer M6.
In the static memory unit, the first pull-down transistor group and the first pull-up transistor constitute a reverser, the second pull-down transistor group and the second pull-up transistor constitute another reverser, namely, each static memory unit has two reversers, the drain electrode of the pull-up transistor PU is connected with the drain electrode of the adjacent transmission gate transistor PG and the drain electrode of the adjacent pull-down transistor PD, the source electrode of the pull-up transistor PU is connected with the power voltage VDD, and the grid electrode of the pull-up transistor PU is connected with the drain electrode thereof through a third metal layer M3.
Optionally, the number of FIN structures FIN crossed by the gate of each pull-down transistor PD in the pull-down transistor group is the same, the gate of each of the pull-up transistors PU in the set of pull-up transistors crosses the same number of FIN structures FIN, the gate of each pass gate PG in the pass gate transistor group crosses the same number of FIN structures FIN, and in this embodiment, the gate of each of the pull-up transistor PU, the pull-down transistor PD and the pass-gate transistor PG crosses over a FIN structure FIN, in other embodiments, however, the pull-up transistors PU, the pull-down transistors PD, and the pass-gate transistors PG may span multiple FIN structures FIN, for example, the ratio of the number of FIN structures FIN spanned by the gates of the pull-up transistor PU, the pull-down transistor PD and the pass-gate transistor PG is 1:2: 1; or the ratio of the number of FIN structures FIN crossed by the gates of the pull-up transistor PU, the pull-down transistor PD and the transmission gate transistor PG is 1:2:2, so that the read noise tolerance and the write tolerance of the device are improved.
FIG. 6 is a circuit diagram of the SRAM cell, in which during a read operation, when the word line WL is connected to a high level, the source and drain of the pass gate transistor PG are conducted, since the pull-up transistor PU and the pull-down transistor PD constitute two sets of inverters, the left set of inverter is described first, for example, data "0" is stored at the node QB, and therefore data "1" is stored at the node Q, where "1" makes the source and drain of the pull-down transistor in the first pull-down body tube group conducted, while the source and drain of the first pull-up transistor are not conducted, the bit line BL is connected to a high level "1", charge is passed from the bit line BL to the node QB through the first pass gate transistor PG (for example, data "0" is stored), I1 is generated, and flows to the ground VSS through the pull-down transistor PD in the first pull-down body tube group, I2 is generated, discharge is, at this time, the bit line BL high level changes to low level, i.e., data "0" is read. For the right set of inverters, the complementary bit line BLB is connected to a low level "0", and data "0" stored at node QB makes the source and drain of the second pull-up transistor conductive and the source and drain of the pull-down transistor PD in the second pull-down transistor group nonconductive; the high level "1" of the voltage source VDD flows to the complementary bit line BLB through the second pull-up transistor PU and the pass gate transistor PG of the second pass gate transistor group, i.e., the low level of the complementary bit line changes to the high level.
for example, if the data "0" is stored at the node QB, the data at the node Q is "1", and when a write operation is performed, for example, a "1" needs to be written at the node QB, that is, the data "0" of the node QB is changed to "1". Bit line BL is connected to a high level "1" and complementary bit line BLB is connected to a low level "0". Word line WL is connected to high level, the source and drain of pass-gate transistor PG in the second pass-gate transistor group are turned on, generating current I1 'flowing from node Q to complementary bit line BLB, since node Q stores data "0", the source and drain of second pull-up transistor PU are turned on, generating current I2' flowing from supply voltage VDD to node QB, I1 'is larger than I2', the easier and faster data "1" at node QB is pulled to "0"; the node Q is changed from "1" to "0", the source and drain of the pull-down transistor PD in the second pull-down body tube group are turned on, and the high level "1" of VDD makes the data "0" at the node Q to "1", thereby completing the write operation.
referring to fig. 7, the present embodiment further provides a static memory array, where the static memory array includes the static flash memory cells, and two adjacent static flash memory cells are distributed in a mirror symmetry manner. As can be seen from fig. 6, each group of transfer gate transistor groups and each group of pull-down body transistor groups in the static memory array are vertically arranged, when the transfer gate transistors PD need to be operated, the group of transfer gate transistors is relatively easily selected, the pattern of the required mask plate is relatively simple, and when the group of transfer gate transistors is independently selected, the group of pull-down body transistors and the group of pull-up body transistors are not affected.
The static memory array further comprises a word line WL, a bit line BL, a complementary bit line BLB, a power voltage VDD and a ground line VSS, wherein the grids of a plurality of transmission gate transistors PG in a transmission gate transistor group of each static flash memory unit are connected and then connected with the word line WL; the sources of a plurality of transmission gate transistors PG in the transmission gate transistor group of each static flash memory unit are connected and then connected with the bit line BL or the complementary bit line BLB; the source electrode of the pull-up transistor PU of each static flash memory unit is connected with the power supply voltage VDD; the sources of a plurality of pull-down transistors PD in the pull-down body tube group of each static flash memory unit are connected and then are connected with the ground wire VSS. And a certain static storage unit is convenient to select and operate.
The invention also provides a static memory device comprising the static memory array.
in summary, in the static memory cell, the array and the device provided by the embodiments of the invention, the pull-up transistor group has two pull-up transistors arranged diagonally, the pull-down transistor group is located at two sides of the pull-up transistor group, the transfer gate transistor group is located at an outer side of the pull-down transistor group, gates of the pull-down transistors in the pull-down transistors are arranged in a row, and gates of the transfer gate transistors in the transfer gate transistor group are arranged in a row, so that the pull-down transistors and the transfer gate transistors can be distinguished conveniently, and the transfer gate transistors are selected and operated individually, so as to perform a special operation (e.g., ion implantation) on a source, a drain or a gate of the transfer gate transistors, increase a read-write current of the transfer gate transistors, and further increase a read-write speed of the static memory cell.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (15)

1. A static memory cell is formed on a substrate, and comprises a pull-up body tube group, two pull-down body tube groups and two transmission gate transistor groups;
The pull-up body tube group comprises two pull-up transistors, and grid electrodes of the two pull-up transistors are arranged on the substrate in a diagonal line manner; the pull-down transistor group comprises a plurality of pull-down transistors, and the grid electrodes of the pull-down transistors are arranged in a row; the transmission gate transistor group comprises a plurality of transmission gate transistors, and the gates of the transmission gate transistors are arranged in a column;
The two pull-down body tube groups are respectively positioned at the outer sides of the pull-up body tube groups, and the two transmission gate transistor groups are respectively positioned at the outer sides of the two pull-down body tube groups.
2. The static memory cell of claim 1, wherein a number of pull-down transistors in the set of pull-down transistors is the same as a number of pass-gate transistors in the set of pass-gate transistors.
3. the static memory cell of claim 2, wherein the two pull-down banks are a first pull-down bank and a second pull-down bank, respectively, and the two transfer gate banks are a first transfer gate bank and a second transfer gate bank, respectively, the first pull-down bank being adjacent to the first transfer gate bank and the second pull-down bank being adjacent to the second transfer gate bank.
4. The static memory cell of claim 3, wherein a first fin structure, a second fin structure, a third fin structure, a fourth fin structure, a fifth fin structure and a sixth fin structure are formed on the substrate in a side-by-side arrangement, gates of two pull-up transistors of the pull-up transistor group are respectively located on the third fin structure and the fourth fin structure, gates of pull-down transistors of the first pull-down transistor group and the second pull-down transistor group are respectively located on the second fin structure and the fifth fin structure, and gates of pass-gate transistors of the first pass-gate transistor group and the second pass-gate transistor group are respectively located on the first fin structure and the sixth fin structure.
5. The static memory cell of claim 4, wherein the gate of one of the pull-down transistors in the set of pull-down bodies is arranged in a row with the gate of one of the pass-gate transistors in the set of pass-gate transistors, and wherein the gates of the plurality of pull-down transistors in the set of pull-down bodies are arranged in a plurality of rows with the gates of the pass-gate transistors of the plurality of the set of pass-gate transistors.
6. the static memory cell of claim 3, wherein the gates of a plurality of pass-gate transistors of said set of pass-gate transistors are connected to a word line; the sources of a plurality of transmission gate transistors in the transmission gate transistor group are connected and then connected with a bit line or a complementary bit line.
7. The static memory cell of claim 6, wherein the two pull-up transistors are a first pull-up transistor and a second pull-up transistor, the first pull-up transistor being adjacent to the first set of pull-down transistors, the second pull-up transistor being adjacent to the second set of pull-down transistors.
8. The static memory cell of claim 7, wherein the gates of the plurality of pull-down transistors in the first set of pull-down transistors are connected to the gate of the first pull-up transistor; the grid electrodes of a plurality of pull-down transistors in the second pull-down transistor group are connected and then connected with the grid electrode of the second pull-up transistor; and the sources of a plurality of pull-down transistors in the first pull-down body tube group and the second pull-down body tube group are connected and then are connected with a ground wire.
9. The static memory cell of claim 8, wherein sources of said first pull-up transistor and said second pull-up transistor are connected to a supply voltage.
10. The static memory cell of claim 9, wherein drains of the pass transistors in the set of pass transistors are connected, drains of the pull-down transistors in the set of pull-down transistors are connected, a drain of a pass transistor in the first set of pass transistors is connected to a drain of a pull-down transistor in the first set of pull-down transistors and to a gate of the first pull-up transistor, and a drain of a pass transistor in the second set of pass transistors is connected to a drain of a pull-down transistor in the second set of pull-down transistors and to a gate of the second pull-up transistor.
11. The static memory cell of claim 10, wherein a drain of the first pull-up transistor is connected to a drain of a pull-down transistor in the first set of pull-down transistors, and a drain of the second pull-up transistor is connected to a drain of a pull-down transistor in the second set of pull-down transistors.
12. The static memory cell of claim 1, wherein said pull-up transistor is a PMOS field effect transistor and said pull-down transistor and said pass-gate transistor are NMOS field effect transistors.
13. A static memory array comprising a plurality of static flash memory cells according to any one of claims 1-12, wherein two adjacent static flash memory cells are arranged in mirror symmetry.
14. The static memory array of claim 13, wherein said static memory array further comprises word lines, bit lines, complementary bit lines, power supply voltages, and ground lines, wherein the gates of a plurality of pass-gate transistors of the pass-gate transistor group of each of said static flash memory cells are connected to said word lines; the source electrodes of a plurality of transmission gate transistors in the transmission gate transistor group of each static flash memory unit are connected and then connected with the bit line or the complementary bit line; the source electrode of the pull-up transistor of each static flash memory unit is connected with the power supply voltage; and the sources of a plurality of pull-down transistors in the pull-down body tube group of each static flash memory unit are connected and then are connected with the ground wire.
15. A static memory device comprising a static memory array according to any of claims 13-14.
CN201810577974.4A 2018-06-05 2018-06-05 Static memory cell, array and device Pending CN110570888A (en)

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