CN110556133A - Over-drive voltage generator - Google Patents
Over-drive voltage generator Download PDFInfo
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- CN110556133A CN110556133A CN201810538051.8A CN201810538051A CN110556133A CN 110556133 A CN110556133 A CN 110556133A CN 201810538051 A CN201810538051 A CN 201810538051A CN 110556133 A CN110556133 A CN 110556133A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Abstract
The invention provides an overdrive voltage generator, which comprises a first switch circuit, a booster circuit, a second switch circuit and a comparison circuit. The first switch circuit is coupled between the first power supply and the output end and is used for providing an overdrive voltage to the output end under the control of a switch signal. The boost circuit is coupled between the second power supply and the node and is used for boosting the voltage of the second power supply to provide the pump voltage to the node. The second switch circuit is coupled between the node and the output end and is controlled by the switch signal to provide the overdrive voltage to the output end. The comparison circuit is coupled to the first switch circuit, the second switch circuit and the output end, and is used for comparing the overdrive voltage with the first reference voltage to generate a switch signal.
Description
Technical Field
The present invention relates to a voltage generator, and more particularly, to an overdrive voltage generator.
Background
generally, in order to increase the sensing speed of a Sense Amplifier (SA) of a Dynamic Random Access Memory (DRAM), an overdrive (overdrive) technique is usually used for a bit line maximum level voltage of the sense amplifier. In detail, referring to fig. 1, fig. 1 is a power supply diagram of a sense amplifier of a conventional dram. As shown in fig. 1, the voltage regulator 630 generates a bit line maximum level voltage VBLH according to the second power source VDD2, and provides the bit line maximum level voltage VBLH to the sense amplifier circuit 660 through the switch 650, so that the sense amplifier circuit 660 can sense signals of the bit line pair BL,/BL. In addition, the sensing speed of the sense amplifier circuit 660 can be increased by the voltage regulator 610 and the voltage pump circuit 620 providing the overdrive voltage VOD to the sense amplifier circuit 660 through the switch 640 during the initial operation time period of the sense amplifier circuit 660, wherein the voltage regulator 610 generates the overdrive voltage VOD according to the first power source VDD1, and the voltage pump circuit 620 generates the overdrive voltage VOD according to the second power source VDD 2.
However, since the voltage regulator 610 and the voltage pump circuit 620 have different driving capabilities and different response speeds, the current outputted by the first power supply VDD1 and the current outputted by the second power supply VDD2 cannot be precisely controlled. Therefore, in the case of different voltage drop depths (voltage drops) of the overdrive voltage VOD, the power supply ratios of the first power supply VDD1 and the second power supply VDD2 will be different. In addition, since the response speed of the voltage pump circuit 620 is slower than that of the voltage regulator 610, once the transient load of the overdrive voltage VOD is too large and the overdrive voltage VOD is lowered, the voltage pump circuit 620 may not respond immediately, so that the voltage level of the overdrive voltage VOD cannot be recovered quickly.
In order to avoid the problem that the voltage level of the overdrive voltage VOD cannot be recovered quickly due to the transient overload, a dedicated overdrive voltage generator may be provided for each bank of the dram. However, this design will limit the layout of the floor (floor plan) and the layout of the decoupling capacitor (decoupling capacitor).
Disclosure of Invention
in view of the above, the present invention provides an overdrive voltage generator, which can control the power supply ratio of the first power source and the second power source, and has the characteristics of fast response speed and pre-voltage.
The overdrive voltage generator of the invention comprises a first switch circuit, a booster circuit, a second switch circuit and a comparison circuit. The first switch circuit is coupled between the first power supply and the output end and is used for providing an overdrive voltage to the output end under the control of a switch signal. The boost circuit is coupled between the second power supply and the node and is used for boosting the voltage of the second power supply to provide the pump voltage to the node. The second switch circuit is coupled between the node and the output end and is controlled by the switch signal to provide the overdrive voltage to the output end. The comparison circuit is coupled to the first switch circuit, the second switch circuit and the output end, and is used for comparing the overdrive voltage with the first reference voltage to generate a switch signal.
In an embodiment of the invention, the boosting circuit is further coupled to the comparison circuit to receive the switching signal and is controlled by the switching signal to boost the voltage of the second power source to provide the pumping voltage to the node.
In an embodiment of the invention, when the overdrive voltage is lower than the first reference voltage, the comparison circuit generates the switching signal to trigger the boost circuit and turn on the first switching circuit and the second switching circuit, thereby stabilizing the pump voltage and boosting the overdrive voltage.
In an embodiment of the invention, the first switch circuit includes at least one first transistor. The first terminal of the at least one first transistor is coupled to the first power source, the second terminal of the at least one first transistor is coupled to the output terminal, and the control terminal of the at least one first transistor receives the switching signal. The second switch circuit includes at least one second transistor. The first end of the at least one second transistor is coupled to the node, the second end of the at least one second transistor is coupled to the output end, and the control end of the at least one second transistor receives the switching signal.
In view of the above, the overdrive voltage generator according to the embodiment of the invention can be substantially regarded as a digital voltage regulator, which has the characteristic of fast response speed, and thus can be used to simultaneously provide the overdrive voltage required for the operations of all sense amplifier circuits of the dram. Furthermore, the overdrive voltage generator can pre-pressurize the node to stabilize the pump voltage when the overdrive voltage is lower than the first reference voltage, so as to prevent the pump voltage from being excessively pumped and reduced to be too low. In addition, the power supply proportion of the first power supply and the second power supply can be adjusted by adjusting the conducting number of the first transistors and the conducting number of the second transistors of the overdrive voltage generator.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic power supply diagram of a sense amplifier of a conventional DRAM.
FIG. 2 is a block diagram of an overdrive voltage generator and an application thereof according to an embodiment of the invention.
FIG. 3 is a block diagram of an overdrive voltage generator according to another embodiment of the present invention.
Fig. 4 is a block diagram of a pre-charge control circuit according to an embodiment of the invention.
FIG. 5 is a block diagram of a voltage pump circuit according to an embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating a timing diagram of signals according to an embodiment of the invention.
Description of reference numerals:
100. 200: over-drive voltage generator
110. 210: first switch circuit
120. 220, and (2) a step of: second switch circuit
130. 230: voltage booster circuit
140. 240: comparison circuit
231: pre-voltage control circuit
232: voltage pump circuit
2322: pump clock signal generator
2324: pump voltage generator
250: level shifter
610. 630: voltage regulator
620: voltage pump circuit
660. 900: sensing amplifying circuit
800: voltage regulator
820: comparator with a comparator circuit
BL,/BL: bit line pair
C1, C2, C3: capacitor with a capacitor element
CMP1, CMP 2: comparator with a comparator circuit
GND: grounding terminal
INV 1-INV 4: NOT gate
NR: anti-OR gate
OD: node point
ORG: OR gate
OT: output end
p _ CK: pump clock signal
SC: switching signal
SC 1: level shift signal
SDET: detecting the signal
SRUN: running signal
SP: pulse wave
SW1, SW 21: a first transistor
SW2, SW 22: second transistor
SW81, SW91, SW92, 640, 650: switch with a switch body
T11-T14, T21-T24: point in time
VBLH: maximum bit line level voltage
VDD 1: a first power supply
VDD 2: second power supply
VOD: overdrive voltage
VODP: pump voltage
VREF 1: a first reference voltage
VREF 2: second reference voltage
VREF _ VBLH: reference voltage
Detailed Description
Referring to fig. 2, fig. 2 is a block diagram and an application diagram of an overdrive voltage generator according to an embodiment of the invention. The overdrive voltage generator 100 may be used to provide the overdrive voltage VOD for the operation of the sense amplifying circuit 900 of one to more banks (banks) of the dram, but the present invention is not limited thereto. In fact, the overdrive voltage generator 100 of the present invention can be applied to other circuits requiring overdrive.
As shown in fig. 2, the voltage regulator 800 can generate the bit line maximum level voltage VBLH according to the second power source VDD2, and can provide the bit line maximum level voltage VBLH to the sense amplifying circuit 900 through the switch SW92 after the initial operation time period of the sense amplifying circuit 900, so that the sense amplifying circuit 900 senses the signal of the bit line pair BL,/BL, wherein the voltage of the second power source VDD2 is greater than the bit line maximum level voltage VBLH. In detail, the voltage regulator 800 may include, but is not limited to, a switch SW81, a comparator 820, and a capacitor C3. The first terminal of the switch SW81 is coupled to the second power VDD 2. The second terminal of the switch SW81 outputs the highest bit line level voltage VBLH. The non-inverting input terminal of the comparator 820 receives the reference voltage VREF _ VBLH, the inverting input terminal of the comparator 820 is coupled to the second terminal of the switch SW81 for receiving the bit line highest level voltage VBLH, and the output terminal of the comparator 820 is coupled to the control terminal of the switch SW81 for controlling the on/off of the switch SW 81. The capacitor C3 is coupled between the second terminal of the switch SW81 and the ground GND.
On the other hand, the overdrive voltage generator 100 may generate the overdrive voltage VOD according to the first power source VDD1 and the second power source VDD2 to transmit the overdrive voltage VOD to the sense amplifying circuit 900 through the switch SW91 during an initial operation time period of the sense amplifying circuit 900, so as to increase the sensing speed of the sense amplifying circuit 900, wherein the voltage of the first power source VDD1 is greater than the overdrive voltage VOD, and the overdrive voltage VOD is greater than the voltage of the second power source VDD 2.
In detail, the overdrive voltage generator 100 may include a first switch circuit 110, a second switch circuit 120, a boost circuit 130 and a comparison circuit 140, but the invention is not limited thereto. The first switch circuit 110 is coupled between the first power source VDD1 and the output terminal OT, and is controlled by the switch signal SC to provide the overdrive voltage VOD to the output terminal OT.
The voltage boosting circuit 130 is coupled between the second power supply VDD2 and the node OD, and is configured to boost a voltage of the second power supply VDD2 to provide a pump voltage VODP to the node OD, wherein the pump voltage VODP is less than the voltage of the first power supply VDD1 and greater than the overdrive voltage VOD.
The second switch circuit 120 is coupled between the node OD and the output terminal OT and is controlled by the switch signal SC to provide the overdrive voltage VOD to the output terminal OT.
The comparison circuit 140 is coupled to the first switch circuit 110, the second switch circuit 120 and the output terminal OT, and is used for comparing the overdrive voltage VOD with the first reference voltage VREF1 to generate the switching signal SC. It is understood that the first switch circuit 120 and the second switch circuit 120 are controlled by the switch signal SC generated by the same comparison circuit 140 to provide the overdrive voltage VOD in common.
In an embodiment of the invention, the overdrive voltage generator 100 further includes capacitors C1 and C2, wherein the capacitor C1 is coupled between the output terminal OT and the ground terminal GND, and the capacitor C1 can store electric energy and stabilize the overdrive voltage VOD; the capacitor C2 is coupled between the node OD and the ground GND, and the capacitor C2 can store electric energy and stabilize the pump voltage VODP. The operation of the overdrive voltage generator 100 is described as follows.
The boost circuit 130 may compare the pump voltage VODP with a second reference voltage VREF 2. When the pump voltage VODP is lower than the second reference voltage VREF2, the voltage boost circuit 130 may perform a boost operation to boost the pump voltage VODP. On the other hand, when the pump voltage VODP is higher than or equal to the second reference voltage VREF2, the voltage boost circuit 130 stops performing the voltage boost operation to maintain the pump voltage VODP at the second reference voltage VREF 2. In an embodiment of the present invention, the boost circuit 130 may be implemented by using a known voltage pump circuit, for example, but the present invention is not limited thereto.
On the other hand, when the overdrive voltage VOD is lower than the first reference voltage VREF1, the comparison circuit 140 may generate the switching signal SC (e.g., at a first voltage level) to turn on the first switch circuit 110 and the second switch circuit 120 to boost the overdrive voltage VOD. In contrast, when the overdrive voltage VOD is higher than or equal to the first reference voltage VREF1, the comparison circuit 140 may generate the switching signal SC (e.g., at the second voltage level) to turn off the first and second switching circuits 110 and 120 to maintain the overdrive voltage VOD at the first reference voltage VREF 1.
In an embodiment of the invention, the comparison circuit 140 may include a single comparator CMP1, wherein a non-inverting input terminal of the comparator CMP1 receives the first reference voltage VREF1, an inverting input terminal of the comparator CMP1 is coupled to the output terminal OT to receive the overdrive voltage VOD, and an output terminal of the comparator CMP1 outputs the switching signal SC.
In an embodiment of the present invention, the first switch circuit 110 may include at least one first transistor SW 1. The first terminal of the at least one first transistor SW1 is coupled to the first power source VDD1, the second terminal of the at least one first transistor SW1 is coupled to the output terminal OT, and the control terminal of the at least one first transistor SW1 receives the switching signal SC, wherein the at least one first transistor SW1 may be, for example, a pmos, but is not limited thereto. Similarly, the second switch circuit 120 may include at least one second transistor SW 2. The first terminal of the at least one second transistor SW2 is coupled to the node OD, the second terminal of the at least one second transistor SW2 is coupled to the output terminal OT, and the control terminal of the at least one second transistor SW2 receives the switching signal SC, wherein the at least one second transistor SW2 may be, for example, but not limited to, a pmos.
It should be noted that the first transistor SW1 and the second transistor SW2 are turned on or off by the switching signal SC of the single comparator CMP to maintain the overdrive voltage VOD at the first reference voltage VREF1, so the overdrive voltage generator 100 shown in the embodiment of fig. 2 can be substantially regarded as a digital voltage regulator. The digital voltage regulator has the characteristic of high response speed, and can quickly recover the voltage level of the over-driving voltage VOD once the voltage level of the over-driving voltage VOD is reduced due to the fact that the instantaneous load of the over-driving voltage VOD is overlarge. Therefore, the overdrive voltage generator 100 can be used to simultaneously provide the overdrive voltage VOD required by the sense amplifier circuit 900 of all the regions of the DRAM.
in addition, since the output current of the first power supply VDD1 and the output current of the second power supply VDD2 are related to the number of the first transistors SW1 and the number of the second transistors SW2, respectively, the on number of the first transistors SW1 and the on number of the second transistors SW2 can be controlled according to practical applications or design requirements, so as to adjust the power supply ratio of the first power supply VDD1 to the second power supply VDD 2.
Referring to fig. 3, fig. 3 is a block diagram and an application diagram of an overdrive voltage generator according to another embodiment of the invention. The overdrive voltage generator 200 may be used to provide the overdrive voltage VOD for the operation of the sense amplifier circuit 900 of one or more regions of the dram, but the invention is not limited thereto. In fact, the overdrive voltage generator 200 of the present invention can be applied to other circuits requiring overdrive. In addition, the voltage regulator 800, the switches SW91 and SW92, and the sense amplifier circuit 900 shown in fig. 3 are similar to the voltage regulator 800, the switches SW91 and SW92, and the sense amplifier circuit 900 shown in fig. 2, respectively, and therefore, the above description of fig. 2 can be referred to, and the detailed description thereof is omitted.
The overdrive voltage generator 200 may include a first switching circuit 210, a second switching circuit 220, a boosting circuit 230, a comparing circuit 240, and a level shifter 250, but the present invention is not limited thereto. The comparison circuit 240 is similar to the comparison circuit 140 of fig. 2, so the operations and embodiments thereof can be referred to the related descriptions above, and are not repeated herein. The level shifter 250 is coupled to the comparing circuit 240 for receiving the switching signal SC and shifting a voltage swing range of the switching signal SC to generate the level shifted signal SC 1. The first switch circuit 210 and the second switch circuit 220 are similar to the first switch circuit 110 and the second switch circuit 120 of fig. 2, respectively, except that the first switch circuit 210 and the second switch circuit 220 are controlled by the level shift signal SC1 to provide the overdrive voltage VOD to the output terminal OT. The boosting circuit 230 is coupled between the second power source VDD2 and the node OD, and is controlled by the switching signal SC to boost the voltage of the second power source VDD2 to provide the pump voltage VODP to the node OD, which will be described in detail later.
In an embodiment of the present invention, the first switch circuit 210 may include at least one first transistor SW 21. The first terminal of the at least one first transistor SW21 is coupled to the first power VDD1, the second terminal of the at least one first transistor SW21 is coupled to the output terminal OT, and the control terminal of the at least one first transistor SW21 receives the level shift signal SC1, wherein the at least one first transistor SW21 can be, for example, but not limited to, an nmos transistor. Similarly, the second switch circuit 220 may include at least one second transistor SW 22. The first terminal of the at least one second transistor SW22 is coupled to the node OD, the second terminal of the at least one second transistor SW22 is coupled to the output terminal OT, and the control terminal of the at least one second transistor SW22 receives the level shift signal SC1, wherein the at least one second transistor SW22 may be, for example, but not limited to, an nmos field effect transistor. It should be noted that the level shifter 250 shifts the voltage swing range of the switching signal SC to generate the level shifted signal SC1, so as to ensure that the first transistor SW21 and the second transistor SW22 (which are nmos field effect transistors) can be turned on or off completely.
Similar to the overdrive voltage generator 100 shown in the embodiment of fig. 2, the overdrive voltage generator 200 shown in the embodiment of fig. 3 can be regarded as a digital voltage regulator, so that it has a fast response speed. The overdrive voltage generator 200 may rapidly restore the voltage level of the overdrive voltage VOD once the instantaneous load of the overdrive voltage VOD is excessive to cause the voltage level of the overdrive voltage VOD to be lowered. Therefore, the overdrive voltage generator 200 can be used to simultaneously provide the overdrive voltage VOD required by the sense amplifier circuit 900 of all the regions of the DRAM.
In addition, since the output current of the first power supply VDD1 and the output current of the second power supply VDD2 are related to the number of the first transistors SW21 and the number of the second transistors SW22, respectively, the on number of the first transistors SW21 and the on number of the second transistors SW22 can be controlled according to practical application or design requirements, and the power supply ratio of the first power supply VDD1 to the second power supply VDD2 can be adjusted according to practical application or design requirements.
The operation and implementation of the boost circuit 230 will be described below. As described above, the switching signal SC generated by the comparing circuit 240 can control the operation of the boosting circuit 230. In detail, when the overdrive voltage VOD is lower than the first reference voltage VREF1, the comparison circuit 240 may generate the switching signal SC (e.g., a first voltage level), and generate the level-shifted signal SC1 through the level shifter 250 to turn on the first switching circuit 210 and the second switching circuit 220 to boost the overdrive voltage VOD. At this time, the switching signal SC generated by the comparing circuit 240 also triggers the voltage boosting circuit 230, so that the voltage boosting circuit 230 can pre-pressurize the node OD when the second switching circuit 220 is turned on to stabilize the pumping voltage VODP, thereby preventing the pumping voltage VODP from dropping too low due to the pumping of the pumping voltage VODP by the second switching circuit 220.
On the contrary, when the overdrive voltage VOD is higher than or equal to the first reference voltage VREF1, the comparison circuit 240 generates the switching signal SC (e.g., at the second voltage level), and generates the level-shifted signal SC1 to turn off the first and second switching circuits 210 and 220 through the level shifter 250, so as to maintain the overdrive voltage VOD at the first reference voltage VREF 1. At this time, the switching signal SC stops triggering the boosting circuit 230.
In addition, similar to the boosting circuit 130 of fig. 2, the boosting circuit 230 of fig. 3 can also compare the pump voltage VODP with the second reference voltage VREF2 to determine whether to boost the pump voltage VODP, and the detailed operations thereof can refer to the related description of the boosting circuit 130 of fig. 2, and are not repeated herein.
In an embodiment of the present invention, the voltage boost circuit 230 may include a pre-boost control circuit 231 and a voltage pump circuit 232. The pre-voltage control circuit 231 is coupled to the comparison circuit 240 for receiving the switching signal SC and generating the pulse wave SP in response to the switching signal SC. The voltage pump circuit 232 is coupled to the pre-voltage control circuit 231 for receiving the pulse SP and boosting the voltage of the second power VDD2 in response to the pulse SP to generate and provide the pump voltage VODP to the node OD. In detail, the voltage pump circuit 232 boosts the voltage of the second power source VDD2 in response to the pulse SP to pre-charge the node OD, thereby stabilizing the pump voltage VODP. In addition, the voltage pump circuit 232 may further compare the pump voltage VODP with a second reference voltage VREF 2. When the pump voltage VODP is lower than the second reference voltage VREF2, the voltage pump circuit 232 boosts the voltage of the second power supply VDD2 to raise the pump voltage VODP.
In an embodiment of the present invention, the pre-voltage control circuit 231 may include a one-shot circuit (one-shot circuit), which generates the pulse wave SP according to an edge (e.g., a rising edge or a falling edge) of the switching signal SC.
In another embodiment of the present invention, as shown in fig. 4, the pre-charge control circuit 231 may include not gates INV1 to INV4 and an or gate NR. An input terminal of the not gate INV1 receives the switching signal SC, and an output terminal of the not gate INV1 is coupled to the first input terminal of the or gate NR. NOT gate
INVs 2-4 are connected in series between the output terminal of the NOT gate INV1 and the second input terminal of the NOR gate NR. The output of the NOR gate NR can output a pulse SP.
In one embodiment of the present invention, as shown in fig. 5, the voltage pump circuit 232 may include a comparator CMP2, an or gate ORG, a pump clock signal generator 2322, and a pump voltage generator 2324. The non-inverting input of the comparator CMP2 receives the second reference voltage VREF2, the inverting input of the comparator CMP2 is coupled to the node OD (shown in fig. 3) to receive the pump voltage VODP, and the output of the comparator CMP2 outputs the detection signal SDET. A first input terminal of the or gate ORG is coupled to the output terminal of the comparator CMP2 for receiving the detection signal SDET, a second input terminal of the or gate ORG is coupled to the pre-voltage control circuit 231 (shown in fig. 3) for receiving the pulse SP, and an output terminal of the or gate ORG outputs the run signal SRUN. The pump clock signal generator 2322 is coupled to the output of the or gate ORG to receive the run signal SRUN and accordingly generate the pump clock signal P _ CK. The pump voltage generator 2324 is coupled to the pump clock signal generator 2322 to receive the pump clock signal P _ CK and accordingly generate the pump voltage VODP. In an embodiment of the invention, the pump clock signal generator 2322 and the pump voltage generator 2324 can be implemented by a known pump clock signal generating circuit and a known pump voltage generating circuit, respectively.
referring to fig. 3 to 6, fig. 6 is a signal timing diagram of the overdrive voltage generator of fig. 3, the pre-boost control circuit of fig. 4 and the voltage pump circuit of fig. 5 according to an embodiment of the invention. First, at the time point T11, the comparison circuit 240 determines that the overdrive voltage VOD is lower than the first reference voltage VREF1, so the comparison circuit 240 can output the switching signal SC with a logic high level, for example, and turn on the first switching circuit 210 and the second switching circuit 220 through the level shifter 250 to boost the overdrive voltage VOD. At this time, the pre-voltage control circuit may generate a pulse SP in response to a rising edge of the switching signal SC, and output the running signal SRUN through the or gate ORG of the voltage pump circuit 232 to enable the pump clock signal generator 2322 and the pump voltage generator 2324 to start operating, so that the pump voltage generator 2324 may pre-pressurize the node OD for a period of time (i.e., a width of the pulse SP) when the second switching circuit 220 is turned on, so as to prevent the pump voltage VODP from being lowered to be too low due to the pumping of the pump voltage VODP by the second switching circuit 220.
As the second switch circuit 220 continuously pumps the pump voltage VODP, the pump voltage VODP starts to decrease and the overdrive voltage VOD starts to rise. At time T12, the comparator CMP2 (shown in fig. 5) of the voltage pump circuit 232 determines that the pump voltage VODP is lower than the second reference voltage VREF2, so the comparator CMP2 can output the detection signal SDET at a logic high level, for example, and output the running signal SRUN at a logic high level through the or gate ORG of the voltage pump circuit 232, so that the pump clock signal generator 2322 and the pump voltage generator 2324 can maintain operation to continuously pressurize the node OD.
at the time point T13, the comparison circuit 240 determines that the overdrive voltage VOD has risen to be equal to the first reference voltage VREF1, so that the comparison circuit 240 can output the switching signal SC with, for example, a logic low level and turn off the first switching circuit 210 and the second switching circuit 220 through the level shifter 250. At this time, since the second switch circuit 220 is turned off to stop pumping the pump voltage VODP, the pump voltage VODP starts to rise. At time T14, the comparator CMP2 of the voltage pump circuit 232 determines that the pump voltage VODP has risen to be equal to the second reference voltage VREF2, so that the comparator CMP2 can output the detection signal SDET at a logic low level, for example, and output the running signal SRUN at a logic low level through the or gate ORG of the voltage pump circuit 232, so that the pump voltage generator 2324 stops pressurizing the node OD.
in addition, the operations of the overdrive voltage generator 200 at the time points T21-T24 in fig. 6 are similar to the operations at the time points T11-T14, respectively, so that the related descriptions can be referred to, and are not repeated herein.
in summary, the overdrive voltage generator of the present invention can be regarded as a digital voltage regulator, which has a fast response speed, and thus can be used to simultaneously provide the overdrive voltages required by all sense amplifier circuits of the dram. Furthermore, the power supply proportion of the first power supply and the second power supply can be adjusted by adjusting the conducting number of the first transistors and the conducting number of the second transistors of the overdrive voltage generator. In addition, the overdrive voltage generator can pre-pressurize the node to stabilize the pump voltage when the overdrive voltage is lower than the first reference voltage, so as to prevent the pump voltage from being excessively pumped and reduced to be too low.
although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. An overdrive voltage generator, comprising:
A first switch circuit coupled between a first power supply and an output terminal, for providing an overdrive voltage to the output terminal under control of a switch signal;
The voltage boosting circuit is coupled between a second power supply and a node and used for boosting the voltage of the second power supply to provide a pump voltage to the node;
A second switch circuit coupled between the node and the output terminal for providing the overdrive voltage to the output terminal under the control of the switch signal; and
The comparison circuit is coupled to the first switch circuit, the second switch circuit and the output end, and is used for comparing the overdrive voltage with a first reference voltage to generate the switch signal.
2. the overdrive voltage generator as claimed in claim 1, wherein when the overdrive voltage is lower than the first reference voltage, the comparison circuit generates the switch signal to turn on the first switch circuit and the second switch circuit; the comparison circuit generates the switching signal to turn off the first and second switching circuits when the overdrive voltage is higher than or equal to the first reference voltage.
3. The overdrive voltage generator as claimed in claim 1, wherein the boost circuit is further coupled to the comparison circuit for receiving the switch signal and is controlled by the switch signal to boost the voltage of the second power source for providing the pump voltage to the node.
4. The overdrive voltage generator as claimed in claim 3, wherein when the overdrive voltage is lower than the first reference voltage, the comparison circuit generates the switching signal to trigger the boost circuit and turn on the first and second switching circuits; when the overdrive voltage is higher than or equal to the first reference voltage, the comparison circuit generates the switching signal to stop triggering the boost circuit and turn off the first switching circuit and the second switching circuit.
5. The overdrive voltage generator as claimed in claim 1, wherein the boost circuit compares the pump voltage with a second reference voltage, and performs a boost operation when the pump voltage is lower than the second reference voltage; when the pump voltage is higher than or equal to the second reference voltage and the overdrive voltage is higher than or equal to the first reference voltage, the boost circuit stops the boost operation.
6. The overdrive voltage generator as claimed in claim 5, wherein the second reference voltage is higher than the first reference voltage.
7. The overdrive voltage generator as claimed in claim 1,
The first switching circuit includes:
at least one first transistor, a first terminal of which is coupled to the first power source, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the switching signal;
Wherein the second switching circuit comprises:
The first end of the at least one second transistor is coupled to the node, the second end of the at least one second transistor is coupled to the output end, and the control end of the at least one second transistor receives the switch signal.
8. The overdrive voltage generator as claimed in claim 7, wherein the at least one first transistor and the at least one second transistor are P-type metal oxide semiconductor field effect transistors.
9. The overdrive voltage generator as claimed in claim 1, further comprising:
A level shifter coupled to the comparison circuit for receiving the switching signal and shifting a voltage swing range of the switching signal to generate a level shifted signal,
Wherein the first switching circuit comprises:
At least one first transistor, a first terminal of the at least one first transistor being coupled to the first power source, a second terminal of the at least one first transistor being coupled to the output terminal, and a control terminal of the at least one first transistor receiving the level shifted signal;
Wherein the second switching circuit comprises:
The first end of the at least one second transistor is coupled to the node, the second end of the at least one second transistor is coupled to the output end, and the control end of the at least one second transistor receives the level shift signal.
10. the overdrive voltage generator as claimed in claim 9, wherein the at least one first transistor and the at least one second transistor are N-type mosfets.
11. The overdrive voltage generator as claimed in claim 1, wherein the boost circuit comprises:
A pre-voltage control circuit coupled to the comparison circuit to receive the switching signal and generate a pulse wave in response to the switching signal; and
And the voltage pump circuit is coupled with the pre-voltage control circuit to receive the pulse wave and responds to the pulse wave to boost the voltage of the second power supply so as to generate and provide the pump voltage to the node.
12. The overdrive voltage generator as claimed in claim 11, wherein the pre-charge control circuit comprises:
And the single-shot trigger circuit is used for generating the pulse wave according to the edge of the switch signal.
13. The overdrive voltage generator as claimed in claim 11, wherein the voltage pump circuit boosts the voltage of the second power source in response to the pulse wave to generate and stabilize the pump voltage.
14. The overdrive voltage generator as claimed in claim 11, wherein:
the voltage pump circuit also compares the pump voltage with a second reference voltage, and when the pump voltage is lower than the second reference voltage, the voltage pump circuit boosts a voltage of the second power supply to boost the pump voltage.
15. The overdrive voltage generator as claimed in claim 11, wherein the voltage pump circuit comprises:
A comparator, a non-inverting input of which receives a second reference voltage, an inverting input of which is coupled to the node to receive the pump voltage, and an output of which outputs a detection signal;
an or gate having a first input coupled to the output of the comparator for receiving the detection signal, a second input coupled to the pre-voltage control circuit for receiving the pulse wave, and an output outputting a running signal;
A pump clock signal generator coupled to the output terminal of the or gate to receive the operation signal and generate a pump clock signal accordingly; and
The pump voltage generator is coupled with the pump clock signal generator to receive the pump clock signal and generate the pump voltage according to the pump clock signal.
16. The overdrive voltage generator as claimed in claim 1, wherein the comparison circuit comprises:
A single comparator, a non-inverting input of the single comparator receiving the first reference voltage, an inverting input of the single comparator coupled to the output to receive the overdrive voltage, and an output of the single comparator outputting the switching signal.
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