CN110554984A - Serial port bridging method and system based on CPLD - Google Patents

Serial port bridging method and system based on CPLD Download PDF

Info

Publication number
CN110554984A
CN110554984A CN201910684038.8A CN201910684038A CN110554984A CN 110554984 A CN110554984 A CN 110554984A CN 201910684038 A CN201910684038 A CN 201910684038A CN 110554984 A CN110554984 A CN 110554984A
Authority
CN
China
Prior art keywords
cpld
sent
serial port
characters
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910684038.8A
Other languages
Chinese (zh)
Other versions
CN110554984B (en
Inventor
李小军
吴闽华
孟庆晓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Genew Technologies Co Ltd
Original Assignee
Shenzhen Genew Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Genew Technologies Co Ltd filed Critical Shenzhen Genew Technologies Co Ltd
Priority to CN201910684038.8A priority Critical patent/CN110554984B/en
Publication of CN110554984A publication Critical patent/CN110554984A/en
Application granted granted Critical
Publication of CN110554984B publication Critical patent/CN110554984B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a serial port bridging method and a serial port bridging system based on a CPLD (complex programmable logic device), wherein the method comprises the following steps: when the master device accesses a plurality of slave devices, the master device communicates with the CPLD and writes characters to be sent into a sending data register of the CPLD; the CPLD controls the TXD signals and sends the characters to be sent to the plurality of slave devices according to set parameters; after the characters to be sent are sent, the CPLD sends IPR interrupt signals to the main equipment; and the master device triggers the driving software to send the next character to be sent to the CPLD. According to the invention, a serial port protocol of the address bit of the multi-way mode is realized through the CPLD, so that the communication of the serial port protocol of the multi-way mode is supported between the CPLD and the MCU, the bridging function of the multi-way mode of the CPLD serial port is realized, and further, the communication between the master device and the plurality of slave devices is realized.

Description

serial port bridging method and system based on CPLD
Technical Field
the invention relates to the technical field of embedded driving, in particular to a serial port bridging method and system based on a Complex Programmable Logic Device (CPLD).
Background
Serial ports are used in a large amount in a slow communication protocol, and are generally applied to applications requiring less data to be transmitted and low in speed. As shown in FIG. 1, FIG. 1 is a schematic diagram of a serial port protocol, starting START (not occupying the frame content), data bits (5-8 bits), followed by optional parity bits, and finally a stop bit. Wherein the parity may be set to: odd check, even check, no check; the stop bit may be set to: 1bit, 1.5bit, 2 bit. The serial port protocol has several important parameters including baud rate, stop bit, data bit and parity bit, and two end devices participating in serial communication must configure the above parameters completely the same to correctly communicate. As shown in fig. 2, when serial port terminal software under Windows sets a serial port attribute, it is necessary to set the same attribute as that of an opposite terminal device to perform communication.
the one-to-one serial port communication connection is simple, the transmission and the reception are simple, namely, the transmission and the reception are carried out at once, the master device does not need to be determined to communicate with which slave device, and therefore address bits are not needed. In the multi-node serial port communication system, a Master device Master and a plurality of slave devices Master are provided, a serial port transmitting TX of the Master device is connected with receiving RX of all the slave devices, and transmitting TX of all the slave devices is connected with receiving RX of the Master device. When the master device sends a character, other Slave devices can receive the character, but the Slave devices cannot determine that the sent message is addressed to the Slave device, as shown in fig. 3 and 4, by encoding different serial port addresses for each device, when the master device wants to send a character to the Slave device Slave 1, the first byte is a character with an address Bit Addr Bit equal to 1 and a data Bit equal to 1, and the second byte starts with an address Bit Addr Bit equal to 0, where the data Bit is an actual character to be sent. All the slave devices receive the information sent by the master device, receive the first character with address bit, judge whether the address value is equal to their own address, if not, discard the message, otherwise, receive, the mechanism is a multi-way mode (multi-way). The multi-path mode is divided into a manual mode and an automatic mode, the automatic mode is automatically judged to be discarded by hardware, and the manual mode is judged to be discarded or not by a program. Frame format of multi-path mode: the function is usually found in MC68681 dual, MC68HC11 SCI, DSP56000 SCI and Intel 8051 serviceface, where the start Bit, 5/6/7/8Bit data bits (5-8 bits can be matched), address bits, parity bits (optional), stop bits, and one more address Bit than in the normal mode, when Addr Bit is 1, the first byte of the frame is the node address, not the message content, and when Addr Bit is 0, the content of the whole frame is the message data. However, many CPUs with their own NS16550 serial ports do not support Addr Bit, and if the CPUs need to communicate with MCU singlechips using address bits, the CPUs cannot work.
Accordingly, the prior art is yet to be improved and developed.
disclosure of Invention
Therefore, it is necessary to provide a serial port bridging method and system based on the CPLD to implement serial port protocol communication between the CPLD and the MCU, which supports the multidrop mode, in view of the above technical problems.
A serial port bridging method based on a CPLD comprises the following steps:
A. when the master device accesses a plurality of slave devices, the master device communicates with the CPLD and writes characters to be sent into a sending data register of the CPLD;
B. The CPLD controls the TXD signals and sends the characters to be sent to the plurality of slave devices according to set parameters;
C. After the characters to be sent are sent, the CPLD sends IPR interrupt signals to the main equipment;
D. And the master device triggers the driving software to send the next character to be sent to the CPLD.
The invention further sets up that, in the control of TXD signal by CPLD and the transmission of the character to be transmitted to the plurality of slave devices according to the set parameters, the invention also includes:
b1, the CPLD sends address bit information to the serial bus, the plurality of slave devices receive the address bit information and compare the address bit information with the set serial address bit information, if the comparison result is consistent, the characters to be sent transmitted by the CPLD are received, otherwise, the characters are not received.
The invention further sets up that, in the control of TXD signal by CPLD and the transmission of the character to be transmitted to the plurality of slave devices according to the set parameters, the invention also includes:
B2, if the address value is to be sent currently, after the sending TXD end of the CPLD sends the character to be sent, the sending address bit Addr bit is 1; if the current data to be transmitted is common data, after the transmitting TXD end of the CPLD transmits the character to be transmitted, the transmitting address bit Addr bit is 0.
The invention further sets up that after the main device triggers the driving software to send the next character to be sent to the CPLD, the method also comprises the following steps:
D1, the master device writes the next character to be sent into the sending data register of the CPLD;
d2, repeating the steps A to D1 until all the characters to be sent are sent.
the invention further comprises the following steps:
E. After the data to be sent is sent, the CPLD sends an IPR interrupt signal to the main equipment, simultaneously, the CPLD scans an RXD signal, and after a correct character to be sent is received, the received correct character to be sent is stored in a data receiving register;
F. And after receiving a character to be sent, the CPLD sends an IPR interrupt signal to the main equipment and sends the received character to be sent to the upper-layer software.
In step a, the master device accesses the CPLD through the local bus, and the TXD of the CPLD is connected to the signal receiving ends of the plurality of slave devices, and the RXD of the CPLD is connected to the signal transmitting ends of the plurality of slave devices.
further arrangements of the invention are provided wherein the setting parameters include baud rate, data bits, parity and stop bits.
According to a further configuration of the present invention, the length of the data to be sent is 8 bits.
the invention further sets serial port address bit information of the slave devices in advance.
A serial port bridging system based on a CPLD comprises a master device, the CPLD and a plurality of slave devices, wherein the CPLD stores a plurality of instructions which are suitable for being loaded and executed by a processor to realize the above any serial port bridging method based on the CPLD.
The invention provides a serial port bridging method and a serial port bridging system based on a CPLD (complex programmable logic device), wherein the method comprises the following steps: when the master device accesses a plurality of slave devices, the master device communicates with the CPLD and writes characters to be sent into a sending data register of the CPLD; the CPLD controls the TXD signals and sends the characters to be sent to the plurality of slave devices according to set parameters; after the characters to be sent are sent, the CPLD sends IPR interrupt signals to the main equipment; and the master device triggers the driving software to send the next character to be sent to the CPLD. According to the invention, the serial port protocol of the address bit of the multidrop mode (multi-channel mode) is realized through the CPLD, so that the communication of the serial port protocol of the multidrop mode is supported between the CPLD and the MCU, the bridging function of the serial port multidrop mode of the CPLD is realized, and further, the communication between the master equipment and the plurality of slave equipment is realized.
drawings
fig. 1 is a schematic diagram of a serial protocol.
fig. 2 is a schematic diagram of serial port terminal software attributes.
FIG. 3 is a schematic diagram of a multi-node serial communication system.
fig. 4 is a schematic diagram of a multi-node frame format.
fig. 5 is a flowchart illustrating a preferred implementation of the CPLD-based serial port bridging method according to an embodiment.
Fig. 6 is a logic block diagram of a preferred implementation of the CPLD-based serial port bridging method in one embodiment.
fig. 7 is a schematic diagram of CPLD sending address values.
Fig. 8 is a schematic diagram of CPLD transmitting normal data.
fig. 9 is a schematic diagram of the CPLD sending address values to the slave MCU 1.
fig. 10 is a diagram illustrating the CPLD sending address values to the slave MCU 2.
fig. 11 is a flowchart illustrating a process of the master device sending data to the slave device.
Fig. 12 is a flowchart illustrating a process of transmitting data from a slave device to a master device.
Detailed Description
the invention provides a serial port bridging method and a serial port bridging system based on a CPLD (complex programmable logic device), and in order to make the purpose, the technical scheme and the advantages of the invention clearer and clearer, the invention is further described in detail by referring to the attached drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
the invention will be further explained by the description of the embodiments with reference to the drawings.
As shown in fig. 5, fig. 5 is a flowchart of a preferred embodiment of a serial port bridging method based on CPLD in the embodiment, where the method includes the following steps:
S100, when the master device accesses a plurality of slave devices, the master device communicates with the CPLD and writes characters to be sent into a sending data register of the CPLD. And the length of the data to be sent is 8 bits.
Specifically, as shown in fig. 6, fig. 6 is a logic block diagram of a preferred implementation of the serial port bridging method based on CPLD in an embodiment. The master Device may be an embedded master control CPU (Central processing Unit, CPU), the slave Device may be a peripheral chip MCU (Microcontroller Unit, MCU) serving as a master control CPU, and accesses a CPLD (Complex Programmable Logic Device, logical bridge chip) through a local bus, and a transmitting TXD end of the CPLD is connected to signal receiving ends RXD of the plurality of slave devices, and a receiving RXD end of the CPLD is connected to signal transmitting ends TXD of the plurality of slave devices. The CPLD provides three registers, which are: addrctrl reg, an address bit control register, if addrctrl reg is 0, the data sent in the TxDataReg register is not the address to the slave device, if addrctrl reg is 1, the content in the TxDataReg register is the address to be sent to the slave device; the TxDataReg sends a data register, and data sent by software is stored in the data register; RxDataReg, a receiving data register, and the data received by the CPLD is stored in the receiving data register. When the master device accesses the slave device, the master device writes characters to be sent, which are sent by software, into a send data register.
s200, the CPLD controls the TXD signals and sends the characters to be sent to the plurality of slave devices according to set parameters;
Specifically, the CPLD controls the TXD signal, and sends the characters to be sent to all slave devices in a binary manner according to the set parameters including baud rate, data bits, parity, stop bits, and the like.
Wherein, in the control of TXD signal and the sending of said character to be sent to said several slave devices according to the set parameter of CPLD, also include the step:
s201, the CPLD sends address bit information to the serial port bus, the slave devices receive the address bit information and compare the address bit information with set serial port address bit information, if the comparison result is consistent, characters to be sent transmitted by the CPLD are received, and otherwise, the characters are not received. And presetting serial port address bit information of the plurality of slave devices.
Specifically, the CPLDs send address bit information to the serial bus, all the slave devices can receive the address bit information, and then each slave device compares the address bit information with preset serial address bit information, if the received address bit information is consistent with the preset serial address bit information, the characters sent by the next CPLD are received, that is, the characters to be sent are received, and if the received address bit information is inconsistent with the preset serial address bit information, the characters sent by the next CPLD are not received.
S202, if the address value is to be sent currently, after the sending TXD end of the CPLD sends a byte of data, the sending address bit Addr bit is 1; if the current data to be transmitted is the common data, after the transmitting TXD end of the CPLD transmits a byte of data, the transmitting address bit Addr bit is 0.
The common data is an actual character to be sent by the CPLD, the slave device compares an address value sent by the CPLD with a preset serial port address bit, determines whether the currently sent character to be sent is data to be received by the slave device, and determines which slave device receives the character to be sent, and then the CPLD sends the address bit Addr bit equal to 0, so that the CPLD sends the character to be sent to the slave device. As shown in fig. 7, when the transmission address bit Addr bit is 1, the 8-bit data before Addr bit 1 is an address, and as shown in fig. 8, when the transmission address bit Addr bit is 0, the 8-bit before Addr bit 0 is the data to be actually transmitted.
And S300, after the characters to be sent are sent, the CPLD sends an IPR interrupt signal to the main equipment.
And S400, the master device triggers the driving software to send the next character to be sent to the CPLD.
After the master device triggers the driver software to send the next character to be sent to the CPLD, the method also comprises the following steps:
S401, writing the next character to be sent into a sending data register of the CPLD by the main equipment;
S402, repeating the step S100 to the step S401 until all the characters to be sent are sent.
S500, after the data to be sent is sent, the CPLD sends an IPR (Interrupt Request) Interrupt signal to the main equipment, and simultaneously scans an RXD signal, and after a correct character to be sent is received, the received correct character to be sent is stored in a data receiving register.
s600, after receiving data to be sent, the CPLD sends an IPR interrupt signal to the main equipment and sends the received data to be sent to the upper layer software.
According to the invention, a serial port protocol of the address bit of the multi-way mode is realized through the CPLD, so that the communication of the serial port protocol of the multi-way mode is supported between the CPLD and the MCU, the bridging function of the multi-way mode of the CPLD serial port is realized, and further, the communication between the master device and the plurality of slave devices is realized.
It should be understood that, although the steps in the flowchart of fig. 5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The following description will be made of an example of a case where the slave devices are provided in two.
As shown in fig. 6, fig. 6 is a logic block diagram of communication between a master device and a slave device, where the master CPU accesses a logical bridge Chip (CPLD) through a local bus, and the logical bridge chip is connected to a slave device MCU1 and a slave device MCU 2. The TXD end of the CPLD is connected with the receiving signal ends of the slave device MCU1 and the slave device MCU2, and the RXDs of the CPLD are connected with the transmitting signal ends of the slave device MCU2 and the slave device MCU 2. Meanwhile, the serial address bit Addr bit of the slave device MCU1 is set to 1, and the serial address bit Addr bit of the MCU2 is set to 2.
As shown in fig. 9, if the CPU wants to communicate with the slave MCU1, the CPLD first sends address 1 to the serial bus, and both the slave MCU1 and 2 receive this data. The slave MCU1 compares address bit 1 to confirm its address and receives the next character from the CPLD. The MCU2 receives the character at address bit 1 to confirm that the character is not addressed to itself, and the character from the next CPLD will not be received.
As shown in fig. 10, if the CPU wants to communicate with the slave MCU2, the CPLD sends address 2 to the serial bus, and both the slave MCU1 and 2 receive this data. The slave MCU2 compares address bit 2 to its own address and receives the next character from the CPLD. And the slave device MCU1 receives the character with address value 2, and confirms that the character is not a message addressed to itself, and the character sent from the next CPLD will not be received.
As shown in fig. 11, fig. 11 is a flow chart diagram illustration of the master device transmitting data to the slave device MCU2, which includes the steps of:
S10, starting;
s11, serial port parameters of the main control CPU are set, wherein the baud rate is 115200, the stop bit is 1, the check bit is not available, and then data [ ] is sent;
S12, enabling the sending of the interrupt;
S13, if the address bit control register is addrctrl reg ═ 1, and the transmit data register TxDataReg ═ 2, it indicates that the transmitted data is an address transmitted to the slave MCU2, and the address value is 2;
S14, judging whether the number of remaining bytes is 0, namely judging whether the data is sent, if so, executing a step S18, otherwise, executing a step S15;
s15, the address bit control register addrctrl reg is 0, and the transmission data register TxDataReg is data [ n ], where n is the nth byte currently transmitted;
S16, blocking the sending completion semaphore; if the current data transmission is not finished, the CPLD needs to wait for the completion of the transmission, and after the data transmission is finished, the CPLD transmits an IRQ interrupt signal to the main control CPU;
S17, after one byte is sent, the remaining bytes are counted again, namely the number of bytes needing to be sent is reduced by 1;
s18, finishing transmission;
And S19, ending.
as shown in fig. 12, fig. 12 is a schematic flow chart of transmitting data from the device MCU2 to the master device, which includes the following steps:
S20, starting;
S21, serial port parameters of the MCU2 of the slave device are set, wherein the baud rate is 115200, the stop bit is 1, the check bit is not available, and then data [ ]isreceived;
S22, enabling to receive interrupt;
S23, judging whether the number of remaining bytes is 0, namely judging whether the data is sent, if so, executing a step S30, otherwise, executing a step S24;
S24, blocking the receiving completion semaphore; if the current data reception is not completed, the CPLD needs to wait for the completion of the reception, and after the data reception is completed, the CPLD sends an IRQ interrupt signal to the master control CPU;
s25, the CPLD always scans the RXD signal and stores the received correct byte in the received data register, where the received data register TxDataReg is data [ n ], where n is the nth byte sent from the device MCU2 to the main control CPU, that is, n is the nth byte received by the current CPLD;
S26, recounting the byte number sent to the main control CPU from the MCU2, and subtracting 1 after finishing sending one byte;
s27, finishing the sending;
and S28, ending.
the data sent by the slave node can be only received by the master node, so that a local master value is not needed, namely, an address bit is not needed in the process of sending the data from the slave to the master, and the data is sent more simply and efficiently.
In one embodiment, as shown in fig. 6, a serial port bridging communication system based on a CPLD is provided, which includes a master device, a CPLD and several slave devices, where the CPLD stores multiple instructions, and the instructions are adapted to be loaded and executed by a processor to implement any one of the above serial port bridging methods based on a CPLD. For specific limitations of a serial port bridging communication system based on a CPLD, reference may be made to the above limitations of a serial port bridging method based on a CPLD, which are not described herein again.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. a serial port bridging method based on a CPLD is characterized by comprising the following steps:
A. when the master device accesses a plurality of slave devices, the master device communicates with the CPLD and writes characters to be sent into a sending data register of the CPLD;
B. the CPLD controls the TXD signals and sends characters to be sent to the plurality of slave devices according to set parameters;
C. After the characters to be sent are sent, the CPLD sends IPR interrupt signals to the main equipment;
D. And the master device triggers the driving software to send the next character to be sent to the CPLD.
2. The serial port bridging method based on the CPLD of claim 1, wherein the step of controlling TXD signals by the CPLD and sending the characters to be sent to the plurality of slave devices according to the set parameters further comprises:
B1, the CPLD sends address bit information to the serial bus, the plurality of slave devices receive the address bit information and compare the address bit information with the set serial address bit information, if the comparison result is consistent, the characters to be sent transmitted by the next CPLD are received, otherwise, the characters are not received.
3. the serial port bridging method based on the CPLD of claim 2, wherein the step of controlling TXD signals by the CPLD and sending the characters to be sent to the plurality of slave devices according to the set parameters further comprises:
B2, if the address value is to be sent currently, after the sending TXD end of the CPLD sends the data to be sent, the sending address bit Addr bit is 1; if the current data to be transmitted is common data, after the transmitting TXD end of the CPLD transmits the character to be transmitted, the transmitting address bit Addr bit is 0.
4. The serial port bridging method based on the CPLD of claim 1, wherein after the host device triggers the driver software to send the next character to be sent to the CPLD, the method further comprises the steps of:
d1, the master device writes the next character to be sent into the sending data register of the CPLD;
d2, repeating the steps A to D1 until all the characters to be sent are sent.
5. The CPLD-based serial port bridging method according to claim 1, further comprising the steps of:
E. After the data to be sent is sent, the CPLD sends an IPR interrupt signal to the main equipment, simultaneously, the CPLD scans an RXD signal, and after a correct character to be sent is received, the received correct character to be sent is stored in a data receiving register;
F. And after receiving data to be sent, the CPLD sends an IPR interrupt signal to the main equipment and sends the received characters to be sent to the upper-layer software.
6. the serial port bridging method based on the CPLD as claimed in claim 1, wherein in step a, the master device accesses the CPLD through the local bus, and the TXD end of the CPLD is connected to the signal receiving ends of the plurality of slave devices, and the RXD end of the CPLD is connected to the signal transmitting ends of the plurality of slave devices.
7. The CPLD-based serial port bridging method according to claim 1, wherein the setting parameters include baud rate, data bits, parity and stop bits.
8. The CPLD-based serial port bridging method according to any one of claims 1 to 5, characterized in that the length of the character to be transmitted is 8 bits.
9. The CPLD-based serial port bridging method according to claim 2, wherein serial port address bit information of the slave devices is preset.
10. a CPLD-based serial port bridging system, comprising a master device, a CPLD and several slave devices, wherein the CPLD stores a plurality of instructions, and the instructions are suitable for being loaded and executed by a processor to implement the CPLD-based serial port bridging method according to any one of claims 1 to 9.
CN201910684038.8A 2019-07-26 2019-07-26 CPLD-based serial port bridging method and system Active CN110554984B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910684038.8A CN110554984B (en) 2019-07-26 2019-07-26 CPLD-based serial port bridging method and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910684038.8A CN110554984B (en) 2019-07-26 2019-07-26 CPLD-based serial port bridging method and system

Publications (2)

Publication Number Publication Date
CN110554984A true CN110554984A (en) 2019-12-10
CN110554984B CN110554984B (en) 2023-11-03

Family

ID=68736534

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910684038.8A Active CN110554984B (en) 2019-07-26 2019-07-26 CPLD-based serial port bridging method and system

Country Status (1)

Country Link
CN (1) CN110554984B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1556608A (en) * 2004-01-05 2004-12-22 中兴通讯股份有限公司 Method of realizing RS485 master slave multi machine communication using universal asynchronous recerver transmitter
CN101146090A (en) * 2007-10-16 2008-03-19 深圳国人通信有限公司 A method and device for transmitting and receiving data based on USART bus
US20150103845A1 (en) * 2012-10-11 2015-04-16 Jiangsu Xidiannanzi Smart Electric Power Equipment Co., Ltd Synchronization time-division multiplexing bus communication method adopting serial communication interface
CN107301138A (en) * 2017-06-01 2017-10-27 深圳震有科技股份有限公司 A kind of universal serial bus bridging method and serial bus system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1556608A (en) * 2004-01-05 2004-12-22 中兴通讯股份有限公司 Method of realizing RS485 master slave multi machine communication using universal asynchronous recerver transmitter
CN101146090A (en) * 2007-10-16 2008-03-19 深圳国人通信有限公司 A method and device for transmitting and receiving data based on USART bus
US20150103845A1 (en) * 2012-10-11 2015-04-16 Jiangsu Xidiannanzi Smart Electric Power Equipment Co., Ltd Synchronization time-division multiplexing bus communication method adopting serial communication interface
CN107301138A (en) * 2017-06-01 2017-10-27 深圳震有科技股份有限公司 A kind of universal serial bus bridging method and serial bus system

Also Published As

Publication number Publication date
CN110554984B (en) 2023-11-03

Similar Documents

Publication Publication Date Title
CN106951388B (en) PCIe-based DMA data transmission method and system
US5031091A (en) Channel control system having device control block and corresponding device control word with channel command part and I/O command part
US8185680B2 (en) Method for changing ownership of a bus between master/slave devices
JP3596799B2 (en) System and method for dynamically controlling a bus
US5978865A (en) System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted
US11921660B2 (en) Equalization time configuration method, chip, and communications system
US20160350248A1 (en) Methods and apparatus for a multiple master bus protocol
US10033546B2 (en) Method and system for reprogramming
US7353300B2 (en) Apparatus to improve the firmware efficiency for a multiframe serial interface
US7117283B2 (en) Multi-master extended I2C protocol
CN110750478A (en) Multi-serial port communication method and system
JP2003534580A (en) Improved device-to-device serial bus protocol
US20030149824A1 (en) Method and apparatus for addressing multiple devices simultaneously over a data bus
TW201731272A (en) SPI interface with automatic slave select generation
US10169281B2 (en) Switch system and operation method thereof
CN104615558B (en) A kind of data transferring method and electronic device
CN110554984B (en) CPLD-based serial port bridging method and system
US8166225B2 (en) USB interface data transmission device and USB interface data communication system
US6912607B2 (en) Method and apparatus for ascertaining the status of multiple devices simultaneously over a data bus
KR100811452B1 (en) Remote module for use in PLC system and control method thereof
KR970007257B1 (en) Packet transmission system and method utilizing both data bus and dedicated control lines
JP2003264601A (en) Communication control unit and image formation system
CN116860689A (en) IO expansion system and method based on SPI bus
CN115708076A (en) Communication method, device, server and storage medium for single bus
KR100220518B1 (en) The data structure od car lan system and clock adjusting system using that

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant