CN110554879A - Burning method and system based on processor and computer equipment - Google Patents
Burning method and system based on processor and computer equipment Download PDFInfo
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- CN110554879A CN110554879A CN201910684770.5A CN201910684770A CN110554879A CN 110554879 A CN110554879 A CN 110554879A CN 201910684770 A CN201910684770 A CN 201910684770A CN 110554879 A CN110554879 A CN 110554879A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
Abstract
The invention provides a processor-based burning method, a system and computer equipment, wherein the method is applied to a first processor in a processor-based burning system and comprises the following steps: when detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor; and burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor. By the method, when the second processor is in a to-be-burnt state, the access right of the second flash memory is switched, and the second starting program prestored in the first processor is burnt into the second processor, so that the burning starting program for the other processor is realized through the processor, an additional burning tool is not needed, the operation process is not complex, the burning process does not need human participation, and the burning efficiency is greatly improved.
Description
Technical Field
the invention relates to the technical field of embedded hardware, in particular to a burning method and system based on a processor and computer equipment.
Background
Currently, in an embedded hardware system, there may be multiple processors on a single hardware board, and each processor has a set of independent minimum systems, including a BOOT (BOOT) program. Generally, the BOOT program is written into a BOOT FLASH (BOOT FLASH) by writing software and hardware tools in an auxiliary manner, and if the types of the processors are different, a writing tool corresponding to the processor is required to write into each processor, so that the operation is troublesome, errors are easy to occur, and the efficiency is greatly reduced.
therefore, there is a great need for improvement and development of the prior art.
disclosure of Invention
In view of the defects of the prior art, the invention provides a processor-based burning method, a processor-based burning system and computer equipment, and aims to solve the technical problems of troublesome operation, high error probability and low efficiency of the conventional burning technology.
in a first aspect, an embodiment of the present invention provides a processor-based burning method, which is applied to a first processor in a processor-based burning system, and the method includes:
When detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor;
And burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
As a further improved technical solution, the first processor includes a first memory, and the second processor includes a second memory; the method further comprises the following steps: the method comprises the steps of storing a first starting program and a second starting program into a first memory and a second memory in advance, wherein the first starting program is a starting program of a first processor, and the second starting program is a starting program of a second processor.
As a further improved technical solution, the controlling the second processor to be disconnected from the second flash memory and the controlling the first processor to be connected to the second flash memory by the CPLD includes:
The control register of the CPLD is set to 1 so that the second processor is disconnected from the second flash memory and the first processor is connected to the second flash memory.
as a further improved technical solution, after burning the pre-stored second boot program into the second flash memory, the method includes:
controlling the second processor to reset through the CPLD
In a second aspect, an embodiment of the present invention provides a processor-based burning method, which is applied to a second processor in a processor-based burning system, and the method includes:
When detecting that a first processor is in a state to be burned, controlling the first processor to be disconnected with a first flash memory through a CPLD, and controlling a second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor;
and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
As a further improved technical solution, the controlling the first processor to be disconnected from the first flash memory and the controlling the second processor to be connected to the first flash memory by the CPLD includes:
And setting a control register of the CPLD to 2, so that the first chip selection end of the first processor is disconnected with the first flash memory, and the first chip selection end of the second processor is connected with the first flash memory.
As a further improved technical solution, the burning a pre-stored first boot program to a first flash memory, then, includes:
And controlling the first processor to reset through the CPLD.
in a third aspect, an embodiment of the present invention provides a processor-based burning system, where the system includes: the system comprises a first processor, a second processor, a first flash memory, a second flash memory and a CPLD; the first processor is connected with the first flash memory, the second flash memory and the CPLD; the second processor is connected with the first flash memory, the second processor is connected with the second flash memory, and the second processor is connected with the CPLD;
the first processor is used for controlling the second processor to be disconnected from a second flash memory through a CPLD and controlling the first processor to be connected with the second flash memory when the second processor is detected to be in a to-be-burnt state, wherein the second flash memory is the flash memory of the second processor; burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor;
the second processor is used for controlling the first processor to be disconnected from the first flash memory through the CPLD and controlling the second processor to be connected with the first flash memory when the first processor is detected to be in a to-be-burned state, wherein the first flash memory is a flash memory of the first processor; and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
in a fourth aspect, an embodiment of the present invention provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements the following steps when executing the computer program:
When detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor; burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor;
Or when detecting that the first processor is in a to-be-burned state, controlling the first processor to be disconnected from the first flash memory through the CPLD, and controlling the second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor; and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
in a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following steps:
when detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor; burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor;
Or when detecting that the first processor is in a to-be-burned state, controlling the first processor to be disconnected from the first flash memory through the CPLD, and controlling the second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor; and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
Compared with the prior art, the embodiment of the invention has the following advantages:
The method provided by the embodiment of the invention is applied to a first processor in a processor-based burning system, and comprises the following steps: when detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor; and burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor. By the method, when the second processor is in a to-be-burnt state, the access right of the second flash memory is switched, and the second starting program prestored in the first processor is burnt into the second processor, so that the burning starting program for the other processor is realized through the processor, an additional burning tool is not needed, the operation process is not complex, the burning process does not need human participation, and the burning efficiency is greatly improved.
drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart of a processor-based burning method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the connection between a first processor, a second processor, a first flash memory, a second flash memory and a complex programmable logic device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a connection relationship when neither the first processor nor the second processor requires burning in the embodiment of the present invention;
FIG. 4 is a diagram illustrating a connection relationship between a first processor and a second processor for burning.
FIG. 5 is a flowchart illustrating a software process of a first processor when the first processor is burning a second processor according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a method for processor-based programming according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a connection relationship for burning a first processor by a second processor according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating a software process of the second processor when the second processor is burning the first processor according to the embodiment of the present invention;
FIG. 9 is a schematic diagram of a processor-based burning system according to the present invention;
Fig. 10 is an internal structural view of a computer device in the embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Various non-limiting embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a processor-based burning method in an embodiment of the present invention is shown, which is applied to a first processor in a processor-based burning system, and the method includes:
and S1, when the second processor is detected to be in a to-be-burned state, controlling the second processor to be disconnected from the second flash memory through the CPLD, and controlling the first processor to be connected with the second flash memory, wherein the second flash memory is the flash memory of the second processor.
In this embodiment of the present invention, fig. 2 is a schematic diagram of connections among a first processor, a second processor, a first flash memory, a second flash memory and a complex programmable logic device in this embodiment of the present invention, and referring to fig. 2, connections among the first processor, the second processor, the first flash memory, the second flash memory and the Complex Programmable Logic Device (CPLD) are first established, specifically, the first processor is connected with the first flash memory, the second flash memory and the CPLD, and the second processor is connected with the first flash memory, the second flash memory and the CPLD.
In the embodiment of the present invention, although the first processor is connected to the second flash memory, the first processor cannot access the second memory in the non-specific burning state, for example, when neither the first processor nor the second processor needs to burn, the first processor cannot access the second flash memory, and the second processor cannot access the first flash memory; when the second processor is in a state to be burned, the first processor can access the second memory by changing the state of the CPLD to switch the access authority of the flash memory. The first processor and the second processor may be of the same architecture or of different architectures. For example, the POWER-PC and the ARM are two processors with different architectures, and each has dedicated burning software and hardware.
For example, fig. 3 is a schematic diagram of a connection relationship when neither the first processor nor the second processor needs to be burned, referring to fig. 3, where the first processor is a powerrp-PC, the second processor is an ARM, and when neither the first processor nor the second processor needs to be burned, the BIT0 of the control register (ctrl reg, CR) in the CPLD is controlled to have a value of 0, the BIT1 of the control register (ctrl reg, CR) is controlled to have a value of 0, that is, the value of CR is 0, so that the chip select end LCS1 of the powerrp-PC cannot access the second FLASH memory FLASH-2 of the second process, that is, the CPLD controls the second processor to be disconnected from the second FLASH memory, and the chip select end CS1 of the ARM cannot access the first FLASH memory FLASH-1 of the first process.
Specifically, step S1 further includes:
And S11, setting the control register of the CPLD to be 1 so as to disconnect the second processor from the second flash memory and connect the first processor with the second flash memory.
In the embodiment of the invention, when the second processor is used for the first time, cannot be started or needs to be upgraded, the starting program needs to be burned for the second processor. When the second processor is detected to be in a to-be-burnt state, the first processor controls the logic value of CR in the CPLD to switch the access right of the flash memory, so that the second processor is disconnected from the second flash memory, and the first processor is controlled to be connected with the second flash memory.
for example, fig. 4 is a schematic diagram illustrating a connection relationship between a first processor and a second processor for programming, in an embodiment of the present invention, please refer to fig. 4, where the first processor is a power-PC, the second processor is an ARM, and when the power-PC detects that the ARM is in a to-be-programmed state, the power-PC sets a control register of the CPLD to 1, that is, BIT0 position 1 and BIT1 position 0 of CR in the CPLD are controlled, in a binary system, BIT0 is 1, BIT1 is 0, and a value of the control register of the CPLD is 1. The control register of the CPLD is set to 1, so that the chip selection end CS0 of the ARM cannot access the FLASH-2, namely, the connection between the ARM and the FLASH-2 is disconnected, meanwhile, the chip selection end CS1 of the ARM cannot access the FLASH-1, namely, the connection between the ARM and the FLASH-1 is disconnected, and the chip selection end LCS1 of the first processor POWERP-PC accesses the second FLASH FLASH-2 of the second processor ARM.
before step S1, the method further includes:
S0, storing a first boot program and a second boot program in a first memory and a second memory in advance, where the first memory is a memory of the first processor, the second memory is a memory of the second processor, the first boot program is a boot program of the first processor, and the second boot program is a boot program of the second processor.
For example, in the above example, the first processor is a POWERP-PC, the BOOT program of the POWERP-PC is BOOT-1, the second processor is an ARM, and the BOOT program of the ARM is BOOT-2; BOOT-1 and BOOT-2 are both preserved in advance in the memory of POWERP-PC and the memory of ARM.
and S2, burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
in the embodiment of the present invention, the second boot program is stored in the first processor through step S0, and the connection between the first processor and the second flash memory is established through step S1, so that the pre-stored second boot program is burned into the second flash memory, that is, the burning of the boot program into the second processor is realized, and no additional burning hardware is required in the process.
For example, in the above example, the chip select LCS1 of the first processor power-PC accesses the second FLASH-2 of the second processor ARM, and through this connection, the BOOT-2 in the memory of the power-PC is burned into the FLASH-2.
After step S2, the method further includes:
And S3, setting the control register of the CPLD to 0 so that the second processor is connected with the second flash memory and the first processor is disconnected with the second flash memory.
In the embodiment of the invention, after the burning is finished, the first processor does not access the second FLASH memory any more, the first processor is a power-on-PC, the second processor is an ARM, after the burning is finished, the control register of the CPLD is set to 0, the value of BIT0 BIT of the control register (ctrl reg, CR) in the CPLD is 0, the value of BIT1 BIT is 0, that is, the value of CR is 0, so that the chip select terminal LCS1 of the power-on-PC cannot access the second FLASH memory FLASH-2 of the second processing, that is, the connection between the first processor and the second FLASH memory is disconnected, and meanwhile, the chip select terminal CS1 of the ARM cannot access the first FLASH memory FLASH-1 of the first processing.
And S4, controlling the second processor to reset through the CPLD.
In the embodiment of the present invention, after the first processor completes the programming of the second processor, the reset register in the CPLD needs to be controlled to reset the second processor, and the second processor reads the programmed second boot program after being reset, so that the second processor can be normally booted.
for example, in the above example, the first processor controls the reset register (ResetReg) in the CPLD to reset BIT0 position 1 and BIT1 position 0 in the register to a value of 1, so that the ARM is reset.
fig. 5 is a software flow chart of the first processor when the first processor is burning the second processor in the embodiment of the present invention, referring to fig. 5, when the ARM is in the state to be burned, the software flow of POWER-pc (ppc) is as follows:
PPC detects that ARM is in a state to be burned;
and (a 2) loading a BOOT program BOOT-2 of the ARM by the PPC, and judging whether the loading is successful.
a31. If the loading fails, the burning fails.
The BOOT-2 is pre-stored in the memory of the PPC, and usually there is no loading failure, and if the loading fails, it may be that there is no BOOT-2 pre-stored in the PPC, the PPC cannot be the ARM burn start program.
and controlling the CrtlReg to be 1 by the PPC, namely controlling the BIT1 position 0 and the BIT0 position 1 of the CrtlReg, so that the PPC can access the FLASH-2 of the ARM through the chip selection end LCS 1.
a4. And writing the BOOT-2 into the FLASH-2, namely realizing that the PPC is an ARM burning starting program.
a5. After the burning is finished, the PPC controls the CrtlReg to be 0, namely, when the burning is not needed, the PPC can not access the FLASH-2 state of the ARM.
and 6, controlling ResetReg to be 1 by the PPC, namely controlling the ARM to reset, completing the burning of the ARM, and restarting the ARM after resetting.
Referring to fig. 6, a processor-based burning method in an embodiment of the present invention is shown, which is applied to a second processor in a processor-based burning system, and the method includes:
k1, when detecting that the first processor is in a to-be-burnt state, controlling the first processor to be disconnected from the first flash memory through a CPLD, and controlling the second processor to be connected with the first flash memory, wherein the first flash memory is the flash memory of the first processor;
in the embodiment of the present invention, first, connections between a first processor, a second processor, a first flash memory, a second flash memory, and a Complex Programmable Logic Device (CPLD) are established, specifically, the first processor is connected with the first flash memory, the second flash memory, and the CPLD, respectively, and the second processor is connected with the first flash memory, the second flash memory, and the CPLD, respectively. In the embodiment of the invention, the first processor switches the access authority of the flash memory by changing the state of the CPLD, and when the first processor and the second processor do not need to be burned, the first processor cannot access the second flash memory, and the second processor cannot access the first flash memory. The first processor and the second processor may be of the same architecture or of different architectures. For example, the POWER-PC and the ARM are two processors with different architectures, and each has dedicated burning software and hardware.
for example, the first processor is a power rp-PC, the second processor is an ARM, and when neither the first processor nor the second processor needs to be burned, the value of the first BIT0 and the value of the second BIT1 of the control register (ctrl reg, CR) in the CPLD are 0 and 0, so that the chip select end LCS1 of the power rp-PC cannot access the second FLASH memory FLASH-2 of the second process, and the chip select end CS1 of the ARM cannot access the first FLASH memory FLASH-1 of the first process.
specifically, the step K1 further includes:
k11, setting the control register of the CPLD to be 2 so that the first chip selection end of the first processor is disconnected with the first flash memory, and the first chip selection end of the second processor is connected with the first flash memory
in the embodiment of the invention, when the first processor is used for the first time, cannot be started or needs to be upgraded, the starting program needs to be burned for the first processor. When the first processor is detected to be in a to-be-burned state, the second processor controls the logic value of the CR in the CPLD to switch the access right of the flash memory, so that the first processor is disconnected from the first flash memory, and the second processor is controlled to be connected with the first flash memory.
For example, referring to fig. 7, the first processor is a POWERP-PC, the second processor is an ARM, and when the ARM detects that the POWERP-PC is in a to-be-recorded state, the ARM controls CR in the CPLD to have a BIT0 position 0 and a BIT1 position 1, that is, the value of CR is 2, so that the chip select end LCS1 of the POWERP-PC disconnects the first FLASH memory FLASH-1, meanwhile, the chip select end LCS1 of the POWERP-PC disconnects the second FLASH memory FLASH-2, and the chip select end CS1 of the ARM accesses the first FLASH memory FLASH-1.
before the step K1, the method further includes:
And K0, storing a first starting program and a second starting program into a first memory and a second memory in advance, wherein the first memory is a memory of the first processor, the second memory is a memory of the second processor, the first starting program is a starting program of the first processor, and the second starting program is a starting program of the second processor.
For example, in the above example, the first processor is a POWERP-PC, the BOOT program of the POWERP-PC is BOOT-1, the second processor is an ARM, and the BOOT program of the ARM is BOOT-2; BOOT-1 and BOOT-2 are both preserved in advance in the memory of POWERP-PC and the memory of ARM.
K2 records a pre-stored first boot program into a first flash memory, wherein the first boot program is a boot program of the first processor.
In the embodiment of the invention, the second boot program is stored in the first processor through the step K0, and the connection between the second processor and the first flash memory is established through the step K1, so that the pre-stored first boot program is burned into the first flash memory, that is, the burning of the boot program for the first processor is realized, and no additional burning hardware is required in the process.
for example, in the above example, the chip select terminal CS1 of the second processor ARM accesses the first FLASH memory FLASH-1 of the first processor POWERP-PC, and records the BOOT-1 in the ARM memory into FLASH-1 through this connection.
After step K2, the method further comprises:
K3, setting the control register of CPLD to 0 to connect the first processor with the first flash memory and control the disconnection of the second processor with the first flash memory.
In the embodiment of the invention, after the burning is finished, the second processor does not access the second FLASH memory any more, for example, the first processor is a power-on-PC, the second processor is an ARM, after the burning is finished, the control register of the CPLD is set to 0, the value of BIT0 BIT of the control register (ctrl reg, CR) in the CPLD is 0, the value of BIT1 BIT is 0, that is, the value of CR is 0, so that the chip select terminal CS1 of the ARM cannot access the first FLASH memory FLASH-1 of the power-on-PC, that is, the connection between the second processor and the first FLASH memory is disconnected, and meanwhile, the chip select terminal LCS1 of the power-on-PC cannot access the second FLASH memory FLASH-2 of the power-on-PC.
K4, controlling the first processor to reset through CPLD.
In the embodiment of the present invention, after the second processor completes the programming of the first processor, the reset register in the CPLD needs to be controlled to reset the first processor, and the first processor reads the programmed first boot program after being reset, so that the first processor can be normally booted.
for example, in the above example, the second processor controls the reset register (ResetReg) in the CPLD to reset BIT1 position 1 and BIT0 position 0 in the register to a value of ResetReg of 2 to cause the ARM to reset.
Referring to fig. 8, a software flow of ARM when POWER-pc (ppc) is in a state to be burned is shown, as follows:
b1, detecting that the PPC is in a to-be-burned state by the ARM;
and b2, loading a start program BOOT-1 of the PPC by the ARM, and judging whether the loading is successful.
b31. If the loading fails, the burning fails.
The BOOT-1 is pre-stored in the memory of the ARM, the loading failure is usually avoided, and if the loading failure is possible, the ARM cannot record the BOOT program for the PPC because the ARM does not have the pre-stored BOOT-1.
And b3, controlling the CrtlReg to be 2 by the ARM, namely controlling the BIT1 position 1 and the BIT0 position 0 of the CrtlReg, and realizing that the ARM can access the FLASH-1 of the PPC through the chip selection terminal CS 1.
b4. And writing the BOOT-1 into the FLASH-1, thereby realizing the burning starting program of the PPC by the ARM.
b5. After the burning is finished, the ARM controls the CrtlReg to be 0, namely, when the burning is not needed, the ARM cannot access the state of the FLASH-1 of the PPC.
And b6, controlling ResetReg to be 2 by the ARM, namely controlling the PPC to reset, wherein the PPC is completely burned and can be restarted after being reset.
Based on the above-mentioned burning method based on the processor, the present invention further provides a burning system based on the processor, referring to fig. 9, the system includes: a first processor 501, a second processor 502, a first flash memory 503, a second flash memory 504 and a CPLD 505; wherein, the first processor 501 is connected to the first flash memory 503, the first processor 501 is connected to the second flash memory 504, and the first processor 501 is connected to the CPLD 505; the second processor 502 is connected to the first flash memory 503, the second processor 502 is connected to the second flash memory 504, and the second processor 502 is connected to the CPLD 505;
The first processor 501 is configured to, when detecting that the second processor 502 is in a to-be-burned state, control the second processor 502 to disconnect from the second flash memory 504 through the CPLD505, and control the first processor 501 to connect to the second flash memory 504, where the second flash memory 504 is a flash memory of the second processor 502; a pre-stored second boot program is burned into the second flash memory 504, wherein the second boot program is a boot program of the second processor 502.
the second processor 502 is configured to, when it is detected that the first processor 501 is in a to-be-burned state, control the first processor 501 to disconnect from the first flash memory 503 through the CPLD505, and control the second processor 502 to connect to the first flash memory 503, where the first flash memory 503 is a flash memory of the first processor 501; a pre-stored first boot program is burned into the first flash memory 503, wherein the first boot program is a boot program of the first processor 501.
Referring to fig. 10, a computer device, which may be a terminal, having an internal structure as shown in fig. 10 according to an embodiment of the present invention is shown. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a processor-based burning method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the illustration in fig. 10 is merely a block diagram of a portion of the structure associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
the embodiment of the invention provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the computer equipment is characterized in that the processor executes the computer program and realizes the following steps:
when detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor;
And burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
Or when detecting that the first processor is in a to-be-burned state, controlling the first processor to be disconnected from the first flash memory through the CPLD, and controlling the second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor;
And burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following steps:
when detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor;
And burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
Or when detecting that the first processor is in a to-be-burned state, controlling the first processor to be disconnected from the first flash memory through the CPLD, and controlling the second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor;
And burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
the technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
the above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1.a processor-based burning method is applied to a first processor in a processor-based burning system, and comprises the following steps:
When detecting that a second processor is in a to-be-burnt state, controlling the second processor to be disconnected from a second flash memory through a CPLD (complex programmable logic device), and controlling a first processor to be connected with the second flash memory, wherein the second flash memory is a flash memory of the second processor;
and burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
2. The method of claim 1, wherein the first processor comprises a first memory and the second processor comprises a second memory; the method further comprises the following steps:
The method comprises the steps of storing a first starting program and a second starting program into a first memory and a second memory in advance, wherein the first starting program is a starting program of a first processor, and the second starting program is a starting program of a second processor.
3. The method of claim 1, wherein the controlling the second processor to disconnect from the second flash memory and the first processor to connect to the second flash memory via the CPLD comprises:
the control register of the CPLD is set to 1 so that the second processor is disconnected from the second flash memory and the first processor is connected to the second flash memory.
4. the method according to any one of claims 1-3, wherein burning the pre-stored second boot program into the second flash memory comprises:
And controlling the second processor to reset through the CPLD.
5. A processor-based burning method is applied to a second processor in a processor-based burning system, and comprises the following steps:
when detecting that a first processor is in a state to be burned, controlling the first processor to be disconnected with a first flash memory through a CPLD, and controlling a second processor to be connected with the first flash memory, wherein the first flash memory is a flash memory of the first processor;
and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
6. The method of claim 5, wherein controlling the first processor to disconnect from the first flash memory and the second processor to connect to the first flash memory via the CPLD comprises:
And setting a control register of the CPLD to 2, so that the first chip selection end of the first processor is disconnected with the first flash memory, and the first chip selection end of the second processor is connected with the first flash memory.
7. The method according to any one of claims 5-6, wherein burning the pre-stored first boot program into the first flash memory comprises:
And controlling the first processor to reset through the CPLD.
8. A processor-based burning system, the system comprising: the system comprises a first processor, a second processor, a first flash memory, a second flash memory and a CPLD; the first processor is connected with the first flash memory, the second flash memory and the CPLD; the second processor is connected with the first flash memory, the second processor is connected with the second flash memory, and the second processor is connected with the CPLD;
The first processor is used for controlling the second processor to be disconnected from a second flash memory through a CPLD and controlling the first processor to be connected with the second flash memory when the second processor is detected to be in a to-be-burnt state, wherein the second flash memory is the flash memory of the second processor; and burning a pre-stored second starting program into a second flash memory, wherein the second starting program is a starting program of the second processor.
the second processor is used for controlling the first processor to be disconnected from the first flash memory through the CPLD and controlling the second processor to be connected with the first flash memory when the first processor is detected to be in a to-be-burned state, wherein the first flash memory is a flash memory of the first processor; and burning a pre-stored first starting program into a first flash memory, wherein the first starting program is a starting program of the first processor.
9. a computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of the method of any one of claims 1 to 4 or any one of claims 5 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4 or of any one of claims 5 to 7.
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