CN110543439B - Signal processing system - Google Patents
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- CN110543439B CN110543439B CN201910854297.0A CN201910854297A CN110543439B CN 110543439 B CN110543439 B CN 110543439B CN 201910854297 A CN201910854297 A CN 201910854297A CN 110543439 B CN110543439 B CN 110543439B
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Abstract
The invention discloses a signal processing system, comprising: an input interface, a field programmable gate array module, and at least two output interfaces; the field programmable gate array module receives an input signal of external equipment through an input interface; the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal in a preset format if the interface type is a preset type, and outputting the standard signal through the first output interface; and if the interface type is a non-preset type, outputting an input signal through the second output interface. According to the technical scheme, the input signals are selectively processed according to the interface types, the input signals of the interfaces of the preset type are output after being converted, the input signals of the interfaces of the non-preset type are directly output from different output interfaces, the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of signal processing, in particular to a signal processing system.
Background
In the process of collecting and integrating signals of different devices, the signals of the different devices are required to have the same format, so that the signals are convenient to identify and process. In practice, however, the formats of signals from different devices are often not identical. For example, when signals of the eye tracker and the motion capture device are input to the electroencephalograph for integration, the signals input by the eye tracker and the motion capture device have respective formats and time stamps, for example, the input signals may include a cyclic signal, a continuous clock signal with a fixed frequency, a continuous high-level signal, etc., and the input signals with different formats cannot be directly recognized and used by the electroencephalograph, but need to be converted into signals with standard formats before further processing.
The existing signal format conversion method converts all acquired signals, and cannot selectively process input signals, so that the delay of signal format conversion is high and the efficiency is low.
Disclosure of Invention
The invention provides a signal processing system for improving the efficiency of signal format conversion.
The embodiment of the invention provides a signal processing system, which comprises:
the system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interface; the field programmable gate array module receives an input signal of external equipment through the input interface;
the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal in a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; and if the interface type is a non-preset type, outputting the input signal through a second output interface.
The field programmable gate array module is specifically configured to detect whether the input signal matches a preset format, and if not, mark an interface type of the input interface as a preset type.
Further, the input interfaces are at least two, and the field programmable gate array module comprises:
an interface identifier identifying unit, configured to identify an interface identifier of an input interface corresponding to the input signal;
and the interface type identification unit is used for determining the interface type according to the mapping relation between the interface identifier and the interface type.
Further, the field programmable gate array module further includes:
a signal extraction unit for extracting a high level occurring for the first time in the input signal;
the signal adjusting unit is used for adjusting the duration time of the high level to be a preset duration time to obtain the standard signal;
and the first signal output unit is used for outputting the standard signal through a first output interface.
Further, the input signal includes at least two level signals, and the field programmable gate array module further includes:
a signal decoding unit, configured to decode the input signal into at least two parallel standard signals in a preset format;
and the second signal output unit is used for outputting parallel standard signals through the first output interface.
Further, the signal decoding unit is specifically configured to:
extracting a first occurrence of a high level in each level signal in the input signal;
and adjusting the duration time of each high level to be a preset duration time to obtain the standard signal.
The embodiment of the invention provides a signal processing system, which comprises: the system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interfaces; the field programmable gate array module receives an input signal of external equipment through an input interface; the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal in a preset format if the interface type is a preset type, and outputting the standard signal through the first output interface; and if the interface type is a non-preset type, outputting an input signal through the second output interface. According to the technical scheme, the input signals are selectively processed according to the interface types, the input signals of the interfaces of the preset type are output after being converted, the input signals of the interfaces of the non-preset type are directly output from different output interfaces, the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.
Drawings
Fig. 1 is a schematic diagram of a signal processing system according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a signal processing system according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a signal processing system according to a second embodiment of the present invention;
FIG. 4 is a diagram of an input signal according to a second embodiment of the present invention;
fig. 5 is a schematic diagram of an output signal in a second embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a schematic diagram of a signal processing system according to an embodiment of the present invention. The embodiment can be suitable for processing the input signal of the external equipment, and ensures that the input signal accords with the standard format for other equipment to directly identify and utilize. Specifically, as shown in fig. 1, the system includes: the field programmable gate array comprises an input interface 10, a field programmable gate array module 20 and at least two output interfaces 30, wherein the field programmable gate array module 20 is respectively connected with the input interface 10 and the output interfaces 30; the field programmable gate array module 20 receives an input signal of an external device through the input interface 10; the field programmable gate array module 20 is configured to detect an interface type of an input signal, and if the interface type is a preset type, convert the input signal into a standard signal with a preset format, and output the standard signal through the first output interface 31; if the interface type is a non-preset type, the input signal is output through the second output interface 32.
Specifically, the interface type is a preset type, which means that an input signal input by the interface does not conform to a preset format and is output after format conversion; the non-preset type means that the input signal input by the interface accords with a preset format and can be directly output. The first output interface 31 and the second output interface 32 may be one or a plurality of output interfaces. In the present embodiment, the first output interface 31 refers to an interface for outputting the converted standard signal, and the second output interface 32 refers to an interface for directly outputting the input signal input by an interface of a non-preset type.
In this embodiment, the first output interface 31 and the second output interface 32 can be defined flexibly. For example, in the case of not disassembling the device, it may be predefined by a soft definition manner, which output interfaces are the first output interfaces 31, and which output interfaces are the second output interfaces 32, which may be specifically defined according to actual requirements. In this case, the system further comprises an interface for upgrading the firmware.
Optionally, there are at least two input interfaces 10, and the system may be configured to process Trigger signals (Trigger signals) of the input interfaces 10 synchronously.
Optionally, the field programmable gate array module 20 is specifically configured to detect whether the input signal matches the preset format, and if not, mark the interface type of the input interface 10 as the preset type.
In particular, the interface type of the input interface 10 may be marked by the field programmable gate array module 20. For example, there are 5 input interfaces in the signal processing system, the input interface 1 receives an input signal provided by an external device, at this time, when the field programmable gate array module 20 detects that the input signal does not match the preset format, the input interface 101 is marked as a preset type, and for the input signal of the preset type interface, the input signal is converted into a standard signal of the preset format and output through the first output interface 31. For another example, when the input interface 2 receives an input signal provided by an external device, and the field programmable gate array module 20 detects that the input signal matches a preset format, the input interface 2 is marked as a non-preset type, and the input signal of the interface with the non-preset type is directly output through the second output interface 32.
Alternatively, the interface type of the input interface 10 may be preset. After the field programmable gate array module 20 detects the input signal, it identifies the interface type of the input interface 10 where the input signal is located, so as to perform signal processing. For example, the input interface 3 is a preset type interface, and when the field programmable gate array module 20 detects an input signal of the input interface 3, it converts the input signal into a standard signal and outputs the standard signal from the first output interface 31.
Optionally, in the case that the types of the external devices are less and the types of the common devices and the input signals are relatively fixed, the interface types may be preset, various input signals are input from the corresponding input interfaces 10, after the field programmable gate array module 20 receives the input signals, the format of the input signals does not need to be judged, the interface types can be determined by identifying the numbers and the identifiers of the interfaces, and accordingly, the signal processing is performed, so that the conversion efficiency is improved. Under the conditions that the types of the external devices are more, less frequently used and the types of the input signals are complex and changeable, the field programmable gate array module 20 marks the interface types of the input interface 10 according to the actually received input signals, if the actually received input signals are not matched with the preset format, the input signals are marked as the preset types and are subjected to format conversion, otherwise, the input signals are marked as the non-preset types, so that for various input signals, each signal which is not matched with the preset format can be identified, and the reliability is improved.
Fig. 2 is a schematic diagram of a signal processing system according to a first embodiment of the present invention. As shown in fig. 2, the input interface may be plural; a Field programmable gate array (Field-Programmable Gate Array, FPGA) module as a control module for signal processing; the output interfaces may be plural, wherein the parallels 1 to n are used for outputting individual signals, and the Serial 1-1 to 1-n may be used for outputting plural Parallel signals obtained after decoding one data packet. It should be noted that, in the case where there is only one input interface, the interface type is not preset, but the FPGA module identifies the interface type of the input interface after detecting the input signal each time.
The first embodiment of the invention provides a signal processing system. The interface type of the input signal is detected through the field programmable gate array module, the input signal of the interface of the preset type is converted into a standard signal of the preset format, the standard signal is output through the first output interface, and the input signal of the interface of the non-preset type is directly output through the second output interface, so that the delay of signal processing is reduced; the input signals are selectively processed according to the interface types, so that the input signals of the two types of interfaces are respectively processed, and the efficiency of signal format conversion is improved.
Example two
Fig. 3 is a schematic structural diagram of a signal processing system according to a second embodiment of the present invention. The present embodiment is optimized based on the above embodiments, and specifically describes an interface type for detecting an input signal and a conversion process of the input signal. Technical details which are not described in detail in this embodiment can be found in any of the above embodiments.
As shown in fig. 3, there are at least two input interfaces 10. The field programmable gate array module 20 includes: an interface identifier identifying unit 21, configured to identify an interface identifier of an input interface corresponding to the input signal; the interface type identifying unit 22 is configured to determine the interface type according to the mapping relationship between the interface identifier and the interface type.
Specifically, in this embodiment, the interface type of the input interface 10 is preset, and the mapping relationship data between the interface identifier and the interface type is stored in the system. After detecting the input signal, the interface identifier is identified by the interface identifier identifying unit 21, and the corresponding interface type can be determined by reading the mapping relationship data by the interface type identifying unit 22.
Further, the field programmable gate array module 20 further includes: a signal extraction unit 23 for extracting a high level occurring for the first time in the input signal; a signal adjustment unit 24, configured to adjust the duration of the high level to a preset duration, so as to obtain a standard signal; the first signal output unit 25 is configured to output a standard signal through the first output interface 31.
Specifically, the signal extraction unit 23 and the signal adjustment unit 24 are configured to convert an input signal into a standard signal conforming to a preset format. In this embodiment, the preset format may be that the high level appearing for the first time in the input signal lasts for 1 second, that is, only 1 second of the high level in the standard signal corresponds to the position of the high level appearing for the first time in the input signal, so as to realize conversion of the signal format, so as to meet the requirement of the unified time format. For example, after the input signals from different external devices are converted into standard signals, the position (or time) where the first high level appears in the signal source can be directly identified according to the standard signals, and corresponding data can be read.
Further, the input signal includes at least two level signals, and the field programmable gate array module 20 further includes: a signal decoding unit 26 for decoding the input signal into at least two parallel standard signals of a preset format; the second signal output unit 27 is configured to output parallel standard signals through the first output interface 31.
Specifically, the input signal is a data packet including at least two level signals, the signal decoding unit 26 is configured to decode the data packet into parallel standard signals in a preset format in the format conversion process, and the second signal output unit 27 is configured to output the parallel standard signals from the different first output interfaces 31 to obtain multiple output signals, where the decoding and the conversion are performed synchronously, so as to improve the format conversion efficiency.
Further, the signal decoding unit 26 is specifically configured to: extracting a first occurrence of a high level in each level signal in the input signal; and adjusting the duration time of each high level to be a preset duration time to obtain parallel standard signals. In this embodiment, the signal decoding unit 26 converts each level signal in the data packet to obtain parallel standard signals.
The signal processing procedure is described below by way of example. Table 1 is a mapping relation table of input signals and output signals. As shown in table 1, the input signals corresponding to different input interfaces may be different, and the corresponding output interfaces may be different, where the input signals of Parallel 1 to Parallel n are separate level signals, and the input signals of Serial 1 and Serial n are data packets, and in the process of converting the signals in the data packets into standard signals in a preset format, parallel signals are obtained by decoding the standard signals, and the Parallel signals are output in Parallel from multiple output interfaces. The rule of converting to the preset format is to collect the first occurrence of high level for 1 second.
Table 1 mapping relation table of input signal and output signal
It should be noted that, the preset format may be set according to actual requirements, and the signal processing system is used to process input signals provided by various external devices, output standard signals conforming to the preset format, and may be identified and processed by specific devices.
Fig. 4 is a schematic diagram of an input signal in a second embodiment of the invention. As shown in fig. 4, the input signals corresponding to the input interfaces Parallel 1 to Parallel n are all separate level signals, and the input signals corresponding to the Serial 1 and Serial n are data packets.
Fig. 5 is a schematic diagram of an output signal in a second embodiment of the invention. Taking the input signal of Parallel 1 in FIG. 4 as an example, the input signal is a cyclic signal with a high level of 1 second and a low level of 9 seconds, after conversion, the high level of 1 second only in the first second as shown in Parallel in FIG. 5 is obtained, which corresponds to the position of the high level appearing in the original input signal for the first time, so as to realize conversion of the signal format. The parallel signals shown in Serial 1-1 to 1-n in fig. 5 are obtained after conversion of the packet input signal shown in Serial 1 in fig. 4.
Optionally, the field programmable gate array module 20 is comprised of an FPGA minimum system. The FPGA minimum system comprises: chip, power supply, external clock, reset circuit, download and debug circuit and memory. The FPGA minimum system is configured such that input signals conforming to a preset format are directly output, input signals not conforming to the preset format are converted and output from a corresponding output interface, and at the same time, serial signals can be decoded into parallel signals of a plurality of channels.
The signal processing system provided by the second embodiment of the present invention is optimized based on the above embodiment, and the FPGA module detects the interface type of the input signal, so that the input signal can be rapidly judged and selected, the input signal input by the interface of the preset type is converted, the input signals input by other interfaces are directly output, the serial signal can be decoded into the parallel signal during the conversion process, the conversion and decoding can be realized by using fewer digital devices, and the efficiency of signal format conversion is improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (4)
1. A signal processing system, comprising: the system comprises an input interface, a field programmable gate array module and at least two output interfaces, wherein the field programmable gate array module is respectively connected with the input interface and the output interface; the field programmable gate array module receives an input signal of external equipment through the input interface; wherein the number of the input interfaces is at least two;
the field programmable gate array module is used for detecting the interface type of the input signal, converting the input signal into a standard signal in a preset format if the interface type is a preset type, and outputting the standard signal through a first output interface; if the interface type is a non-preset type, outputting the input signal through a second output interface;
wherein, the field programmable gate array module includes:
an interface identifier identifying unit, configured to identify an interface identifier of an input interface corresponding to the input signal;
an interface type identification unit, configured to determine the interface type according to a mapping relationship between the interface identifier and the interface type;
a signal extraction unit for extracting a high level occurring for the first time in the input signal;
the signal adjusting unit is used for adjusting the duration time of the high level to be a preset duration time to obtain the standard signal;
and the first signal output unit is used for outputting the standard signal through a first output interface.
2. The system of claim 1, wherein the field programmable gate array module is configured to detect whether the input signal matches a predetermined format, and if not, to mark an interface type of the input interface as a predetermined type.
3. The system of claim 1 or 2, wherein the input signal comprises at least two level signals, the field programmable gate array module further comprising:
a signal decoding unit, configured to decode the input signal into at least two parallel standard signals in a preset format;
and the second signal output unit is used for outputting parallel standard signals through the first output interface.
4. A system according to claim 3, characterized in that the signal decoding unit is specifically configured to:
extracting a first occurrence of a high level in each level signal in the input signal;
and adjusting the duration time of each high level to be a preset duration time to obtain parallel standard signals.
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| WO2016000376A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Signal processing method and signal processing apparatus based on pci-e interfaces |
| CN105809940A (en) * | 2016-03-08 | 2016-07-27 | 江苏港湾智广科技有限公司 | Communication signal processing system |
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| WO2016000376A1 (en) * | 2014-06-30 | 2016-01-07 | 中兴通讯股份有限公司 | Signal processing method and signal processing apparatus based on pci-e interfaces |
| CN105809940A (en) * | 2016-03-08 | 2016-07-27 | 江苏港湾智广科技有限公司 | Communication signal processing system |
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