CN110534644B - Preparation method of bidirectional-growth superlattice phase change unit and phase change memory - Google Patents

Preparation method of bidirectional-growth superlattice phase change unit and phase change memory Download PDF

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CN110534644B
CN110534644B CN201910816518.5A CN201910816518A CN110534644B CN 110534644 B CN110534644 B CN 110534644B CN 201910816518 A CN201910816518 A CN 201910816518A CN 110534644 B CN110534644 B CN 110534644B
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phase change
layer
substrate layer
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superlattice
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CN110534644A (en
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程晓敏
冯金龙
缪向水
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering

Abstract

The invention discloses a preparation method of a bidirectional-growth superlattice phase change unit and a phase change memory, wherein a superlattice phase change memory material is formed by alternately stacking a first phase change layer and a second phase change layer; the preparation method comprises the following steps: providing a first substrate layer, and depositing a first phase change layer on the first substrate layer; providing a second substrate layer, and synchronously and alternately depositing a second phase change layer and a first phase change layer on the second substrate layer and the first substrate layer on which the first phase change layer is deposited until the total amount of phase change material layers on the first substrate layer and the second substrate layer reaches the required number of layers; depositing a second phase change layer on the outermost layer of the first substrate layer or the second substrate layer; butting the phase change layers on the first substrate layer and the second substrate layer together by adopting a pressurizing and annealing assembly method; the invention alternately deposits the superlattice materials on the two substrates at the same time, and then assembles the phase change layers on the two substrates together, thereby greatly improving the growth rate of the superlattice film and the utilization rate of the used raw materials.

Description

Preparation method of bidirectional-growth superlattice phase change unit and phase change memory
Technical Field
The invention belongs to the technical field of phase change memories, and particularly relates to a preparation method of a bidirectional-growth superlattice phase change unit and a phase change memory.
Background
Phase change memory materials have attracted considerable attention because they can rapidly switch between a low resistance state and a high resistance state by applying an electric or optical pulse, the process of changing from the high resistance state to the low resistance state being referred to as the SET process and the reverse process being referred to as the RESET process. Phase change material based memory technology is considered to be one of the strong competitors to the next generation memory technology.
The phase change memory material used at present mainly comprises GeTe and Sb2Te3And a compound alloy material Ge composed of the two at a certain ratioxSb2yTex+3y(x and y are integers) and the like. However, a series of studies have shown that the Interface Phase Change Memory (iPCM) using superlattice phase change material as functional material has advantages of SET speed, RESET power consumption and cycle erase stability, which are far superior to those of phase change memory (Simpson R E, Fons P, Kozobov a V, et al].Nature nanotTechnozogy, 2011,6(8): 501). Superlattice materials are multi-layer films in which two different components alternately grow in thin layers of a few nanometers to a dozen nanometers and maintain strict periodicity, and are layered fine composites in fact in a specific form.
Although phase change memory devices using superlattice phase change memory materials as functional layers have many excellent properties, the complexity of the fabrication process has been determined by the structure of the superlattice in which two thin films are alternately grown. On one hand, the conventional growth process of the superlattice material needs to alternately grow layer by layer, and extremely long film growth time is consumed when a plurality of layers of films need to be stacked in the direction vertical to the substrate; on the other hand, after a certain component material with the thickness of several nanometers to tens of nanometers grows on the superlattice, the source or the target needs to be switched to grow another component (such as the target used by a magnetron sputtering method or the gas source used by a chemical vapor deposition method), and the more times of switching, the greater the waste of the material is caused; both of the above aspects will result in the increase of the cost required for growing the superlattice, and even though the superlattice phase-change memory material has many excellent properties at present, the superlattice phase-change memory material has the first driving force for industrial production, but the superlattice phase-change memory material cannot replace the dominant position of the traditional alloy compound phase-change memory material in the phase-change memory technology due to the cost problem.
Therefore, the development of a novel method for preparing a superlattice phase-change memory cell accelerates the preparation speed of the superlattice phase-change memory cell, reduces the loss of raw materials in the alternate growth process of the two materials, finally achieves the purpose of reducing the production cost of the superlattice phase-change memory material, and has important significance for the industrialization process.
Disclosure of Invention
Aiming at least one defect or improvement requirement in the prior art, the invention provides a preparation method of a bidirectional-growth superlattice phase change unit and a phase change memory, wherein phase change material layers are alternately grown on two substrates in a bidirectional way at the same time, and then the phase change material layers on the two substrates are assembled together to form a complete superlattice phase change film with the phase change layers being periodically and alternately arranged; the method can rapidly and bidirectionally grow the superlattice film, improve the growth rate of the superlattice film and the utilization rate of the used raw materials, and aims to solve the problems of long growth period and serious raw material waste of the phase change material layer in the existing preparation process.
To achieve the above object, according to one aspect of the present invention, there is provided a method for preparing a bidirectional growth superlattice phase change cell, comprising the steps of:
providing a first substrate layer, and depositing a first phase change layer on the first substrate layer;
providing a second substrate layer, and synchronously and alternately depositing a second phase change layer and a first phase change layer on the second substrate layer and the first substrate layer on which the first phase change layer is deposited until the total number of the phase change layers on the first substrate layer and the second substrate layer reaches the required number of layers;
depositing a second phase change layer on the outermost layer of the first substrate layer or the second substrate layer;
and butting the phase change layers on the first substrate layer and the second substrate layer together by adopting a pressurizing and annealing assembly method.
Preferably, the above preparation method, the pressing and annealing assembly process comprises the following steps:
applying pressure after the phase change material layers on the first substrate layer and the second substrate layer are butted, so that the phase change layers on the first substrate layer and the second substrate layer are closely butted together;
heating from room temperature to 200-350 ℃ at the heating rate of 5-50 ℃/min;
keeping the temperature at 200-350 ℃ and the heat preservation time at 0.5-2 h;
after the heat preservation is finished, the temperature is reduced to the room temperature at the cooling speed of 5-10 ℃/min.
Preferably, in the above preparation method, the preparation method of the first substrate layer includes: depositing an upper electrode layer on the surface of the insulating layer of the substrate; the upper electrode is a direct support layer of the first phase change layer;
the preparation method of the second substrate layer comprises the following steps:
sequentially depositing a lower electrode and an insulating layer on the surface of the substrate;
etching a through hole in the insulating layer, wherein the through hole penetrates through the insulating layer and is in contact with the lower electrode;
growing a heating layer inside the through hole; specifically, a heating layer is deposited on the insulating layer, then the heating layer on the surface of the insulating layer in the non-through hole area is removed, and the heating layer in the through hole is reserved; the plane formed by the heating layer and the insulating layer is a direct supporting layer of the second phase change layer.
Preferably, in the above preparation method, the substrate is made of Si, and the insulating material on the surface of the substrate is a thermally grown SiO layer2；
The materials of the upper electrode and the lower electrode are selected from Al, W, Ag, Cu, Au, Pt and Ti3W7Any one of the above;
the material of the insulating layer is selected from SiO2、SiC、(ZnS)x(SiO2)100-xAny one of the above; wherein x is an integer greater than 0 and less than 100;
the material of the heating layer is selected from W, TiN and Ti3W7Any one of them.
Preferably, in the above manufacturing method, the lattice mismatch ratio of the first phase change layer and the second phase change layer is between 0.1% and 10%.
Preferably, in the above preparation method, the number of superlattice cycles of the superlattice phase change unit is 5-100;
the deposition thickness ratio of the first phase change layer to the second phase change layer in a single superlattice period is 1: 10-10: 1, and the sum of the deposition thicknesses is 2-10 nm.
Preferably, In the above preparation method, the phase change materials of the first phase change layer and the second phase change layer are any two of simple Sb, Ge-Te binary compounds, Ge-Sb binary compounds, Sb-Te binary compounds, Bi-Te binary compounds, In-Se binary compounds, Ge-Sb-Te ternary compounds, Ge-Bi-Te ternary compounds, Ge-Sb-Bi-Te quaternary compounds or compounds obtained by doping elements thereof, which have different chemical formulas;
the doped element is at least one of C, Cu, N, O, Si, Sc, Ti, Ag and In.
Preferably, the above-mentioned production method,the first phase change layer and the second phase change layer are GeTe, GeSb and Sb2Te3、Bi2Te3、Ge2Sb2Te5、Ge1Sb2Te4Two of which are different.
Preferably, in the above preparation method, the deposition method of the phase change material layer is any one of a magnetron sputtering method, an atomic layer deposition method, a molecular beam epitaxy method, a pulsed laser deposition method, a physical vapor deposition method, a chemical vapor deposition method, a thermal evaporation method, and an electrochemical growth method.
Preferably, in the above preparation method, the deposition method of the phase change material layer in contact when the first substrate layer and the second substrate layer are butted should be an atomic layer deposition method or a molecular beam epitaxy method, so as to ensure that the surface of the butted phase change material layer has atomic-level flatness.
According to another aspect of the invention, the phase change memory is also provided, and the phase change memory comprises the superlattice phase change unit prepared by the preparation method.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) the invention provides a preparation method of a bidirectional-growth superlattice phase change unit and a phase change memory.A phase change material layer grows on two substrates in a bidirectional and alternate manner, and then the phase change material layers on the two substrates are assembled together to form a complete superlattice phase change film with the phase change layers arranged in a periodic and alternate manner; the method can finish the growth of two layers of component materials in the process of growing a layer of component materials in the traditional unidirectional superlattice, and the growth rate of the superlattice film is improved by nearly one time; meanwhile, the consumption of raw materials used in the growth process is greatly reduced, and the production cost of the superlattice thin film is reduced.
(2) The preparation method of the bidirectional-growth superlattice phase change unit and the phase change memory provided by the invention improve the growth rate of the superlattice and the utilization rate of raw materials required by growth, greatly reduce the cost required by growth of the superlattice material, and further effectively promote the application of the superlattice phase change memory material in the phase change memory on the aspect of industrial production.
(3) The preparation method of the bidirectional-growth superlattice phase change unit and the phase change memory are based on the existing CMOS processing technology, the technology is mature, and the process is simple and easy to implement.
Drawings
FIG. 1 is a schematic cross-sectional view of a stage in a process for fabricating a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 2 is a second schematic cross-sectional view of a second stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 3 is a third schematic cross-sectional view of a second stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 4 is a fourth schematic cross-sectional view of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention at a stage during its fabrication;
FIG. 5 is a schematic cross-sectional view of a fifth stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 6 is a sixth schematic cross-sectional view of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention at a stage during its fabrication;
FIG. 7 is a seventh cross-sectional schematic view of a stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 8 is an eighth schematic cross-sectional view of a stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 9 is a ninth schematic cross-sectional view of a stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
FIG. 10 is a tenth sectional schematic view of a stage in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention;
in all the figures, the same reference numerals denote the same features, in particular: 1. 1a, 1 b-substrate, 2a, 2 b-substrate thermally grown layer; 3-an electrode layer; 3 a-lower electrode, 3 b-upper electrode; 4-an insulating layer; 5, heating a layer; 6-a first phase change layer; 7-second phase change layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The preparation method of the bidirectional-growth superlattice phase change unit provided by the invention has the advantages that two substrate layers are utilized to alternately deposit two phase change materials at the same time, and finally, the superlattice thin film layers deposited on the two substrate layers are spliced together by pressurizing and annealing methods, so that the growth rate of the superlattice thin film and the utilization rate of raw materials for growth are improved.
Before depositing the phase-change material, preparing two substrate layers, wherein a first substrate layer comprises a substrate and an upper electrode deposited on the substrate; the second substrate layer comprises a substrate, and a lower electrode and an insulating layer which are sequentially deposited on the substrate; etching a through hole in the insulating layer, wherein the through hole penetrates through the insulating layer and is in contact with the surface of the lower electrode; and then depositing a heating layer on the insulating layer, removing the heating layer on the surface of the insulating layer in the non-through hole area, and keeping the heating layer inside the through hole. The substrate is typically a single crystal silicon and the thermally grown insulating material on the surface is typically amorphous SiO2(ii) a The thermal growth layer is mainly used for isolating the monocrystalline silicon substrate from the upper electrode and the lower electrode; the upper and lower electrodes may be made of Al, W, Ag, Cu, Au, Pt, or Ti3W7Any one of the above; the material of the insulating layer may be SiO2、SiC、(ZnS)x(SiO2)100-x(x is an integer greater than 0 and less than 100), or other dielectric materials suitable for use in memory; the material of the heating layer can be W, TiN or Ti3W7。
After the two substrate layers are prepared, a first phase change layer grows on the first substrate layer to complete an initialization process; then synchronously and alternately depositing a second phase change layer and a first phase change layer on the first substrate layer and the second substrate layer; and after the required number of the superlattice periods is reached, depositing a second phase change layer on the surface of any one substrate layer to ensure the periodicity of the superlattice alternately stacked and grown by the second phase change layer and the first phase change layer. And finally, butting the superlattice material layers of the two substrate layers, and combining the superlattice materials of the two parts together by a pressurizing and annealing method to obtain a complete superlattice phase change unit.
The superlattice phase change unit has a superlattice structure of [ AmBn]zWherein A represents the phase change material of the first phase change layer, and B represents the phase change material of the second phase change layer; m and n respectively represent the thicknesses of the two phase change material layers A, B, the unit default is nanometer, and z is the number of cycles of the superlattice; 1/10<m/n<10/1, and 2<m+n<10，5<z<100, m and n are real numbers, and z is an integer. Preferably, the lattice constant mismatch between the two phase change materials A, B should not be too large to ensure that a superlattice structure is more easily formed between the two crystal lattices. More preferably, the lattice mismatch between the two materials should be between 0.1% and 10%.
The two phase-change materials A, B are elementary substance or compound materials and any two of the elementary substance and compound doped materials with different chemical formulas; wherein the elementary substance material is Sb elementary substance; the compound material comprises: Ge-Te binary alloys, Ge-Sb binary alloys, Sb-Te binary alloys, Bi-Te binary alloys, In-Se binary alloys, and Ge-Sb-Te ternary alloys, Ge-Bi-Te ternary alloys, Ge-Sb-Bi-Te quaternary alloys; more preferably GeTe, GeSb, Sb2Te3、Bi2Te3、Ge2Sb2Te5、Ge1Sb2Te4Two of which are different. The doped element can be at least one of C, Cu, N, O, Si, Sc, Ti, Ag and In; proper doping can improve the stability of cyclic erasing and writing of the superlattice phase change unit and the SET speed, and reduce the RESET power consumption.
The deposition method can adopt any one of a magnetron sputtering method, an atomic layer deposition method, a molecular beam epitaxy method, a pulse laser deposition method, physical vapor deposition, a chemical vapor deposition method, a thermal evaporation method and an electrochemical growth method; taking the chemical vapor deposition method as an example, the chemical vapor deposition method can specifically change the gas source introduced into the cavity alternately, and form the first phase change layer or the second phase change layer alternately on a single substrate or a plurality of substrates; the thickness of each phase change film layer can be controlled by controlling the time of gas source introduction, and the period number of the multilayer film can be controlled by alternately changing the times of gas source introduction into the cavity.
The method of press and anneal assembly comprises three temperature control processes: the first process is a temperature rise process, and pressure is applied after the phase change layers of the first substrate layer and the second substrate layer are butted, so that the phase change layers on the first substrate layer and the second substrate layer are closely butted together; the heating rate is 5-50 ℃/min, and the temperature is raised to 200-350 ℃; and raising the temperature to provide enough kinetic energy for atoms of the phase change film layer to be freely diffused, so that the crystals are promoted to grow and fuse, and the crystals on the surfaces of the two substrate layers are grown together. The second process is a heat preservation process, the temperature is kept at the temperature (200-. The heat preservation is to provide sufficient migration time for atoms, and in the process, the atoms can move freely to form crystalline chemical bonds with adjacent atoms, so that sufficient crystal growth time is provided for the phase change film layers on the surfaces of the two substrate layers to be butted together. The third process is a cooling process, the cooling rate is 5-10 ℃/min, and the temperature is reduced to the room temperature; the cooling rate is slow so as to ensure that the atoms have enough time to relax in the cooling process.
The following describes the process for preparing the superlattice phase change cell based on bidirectional growth according to the present invention in detail with reference to the following embodiments and accompanying drawings.
FIGS. 1-10 are schematic illustrations of stages in the fabrication of a bi-directionally grown superlattice phase change memory cell in accordance with an embodiment of the present invention; the superlattice thin film phase change memory cell prepared in the embodiment is a phase change memoryIn the present embodiment, the two phase change materials are GeTe and Sb respectively2Te3M/n is 2/2, z is 12, and the preparation process is as follows:
(1) as shown in FIG. 1, a 500 μm thick (100) oriented silicon wafer was selected as a substrate 1, and a 1 μm thick SiO layer formed by a thermal growth method was formed on the surface of the Si substrate 12An insulating layer, i.e. a substrate, is thermally grown layer 2. Cutting a silicon wafer into the size of 1cm multiplied by 1cm, putting the silicon wafer into a beaker, injecting a proper amount of acetone, and ultrasonically cleaning for 10 minutes; after cleaning, cleaning the fabric for 10 minutes by using absolute ethyl alcohol, cleaning the fabric for ten minutes by using deionized water, and drying the fabric by using a nitrogen gun; and then forming an Al electrode layer 3 on the substrate thermal growth layer 2 by using a magnetron sputtering method.
(2) As shown in fig. 2, taking a substrate sheet (labeled as substrate layer ii) on which the Al electrode layer 3 has been formed in step (1), growing a layer of SiO on the Al electrode layer 3 (labeled as lower electrode 3a) by using a chemical vapor deposition method2As the insulating layer 4.
(3) As shown in fig. 3, a via hole having a diameter of 130nm is etched in the insulating layer 4 by using a photolithography and etching process, and the via hole penetrates through the insulating layer 4 and contacts the lower electrode 3 a.
(4) As shown in fig. 4, depositing a TiN layer on the surface of the substrate layer ii finally obtained in the step (3) by using a magnetron sputtering method to serve as a heating layer 5; due to the presence of the via hole, the TiN heating layer 5 will fall into the via hole into contact with the lower electrode 3 a.
(5) As shown in FIG. 5, excess TiN heating layer 5 on the insulating layer 4 is removed by Chemical Mechanical Polishing (CMP), SiO2Part of the TiN heating layer 5 in the through hole of the insulating layer 4 is reserved. The preparation of both substrate layers is now complete.
(6) As shown in fig. 6, one substrate (denoted as substrate layer i) on which the Al electrode layer 3 has been formed in step (1) is taken, and turned over so that the Si substrate (denoted as 1b) is on top and the Al electrode layer (denoted as upper electrode 3b) is on bottom. Depositing a first phase change layer 6, i.e. a superlattice component Sb, on the surface of the upper electrode 3b of the substrate layer I2Te3To complete the initialization process of bi-directionally growing the superlattice.
(7) As shown in fig. 7, the substrate layers i and ii are simultaneously placed in a chemical vapor deposition chamber, a gas source required for the growth of the superlattice composition GeTe of the second phase change layer 7 is introduced, and the second phase change layer 7 is simultaneously deposited on the surfaces of the substrate layers i and ii. The time for introducing the gas source required for GeTe growth is in linear relation with the thickness of the second phase change layer 7, and the introduction of the gas source is stopped when the thickness of the second phase change layer 7 meets the requirement.
(8) As shown in FIG. 8, the gas source for growing the second phase change layer 7 remained in the CVD chamber is purged, and the superlattice component Sb is introduced into the CVD chamber2Te3And simultaneously depositing a first phase change layer 6 on the surfaces of the substrate layers I and II by using a required gas source. Introduction of growing Sb2Te3The time of the required air source is in linear relation with the thickness of the first phase change layer 6, and the air source is stopped to be introduced when the thickness of the first phase change layer 6 meets the requirement.
Alternately carrying out the steps (7) and (8) until the growth of the z-1 layer (A + B) structure is completed; the z-1 th layer of the first phase change layer 6 can be formed by a molecular beam epitaxy method alone, so that the surface layer phase change material on the substrate layer I has atomic-level flatness when the substrate layer I and the substrate layer II are butted.
(9) As shown in fig. 9, after the superlattice growth is completed by z-1 cycles, a molecular beam epitaxy method is independently utilized to deposit and form a second phase change layer 7GeTe material with atomic-level flatness on the surface of the substrate layer ii, so as to ensure that the periodicity of the phase change materials A, B in the superlattice in an alternating arrangement and the surface layer phase change material on the substrate layer ii has atomic-level flatness when the substrate layer i and the substrate layer ii are butted.
(10) As shown in FIG. 10, the substrate layer II with the second phase change layer 7 separately grown in step (9) and the substrate layer I formed in the previous step of step (9) are butted, so that the GeTe material of the second phase change layer 7 on the surface of the substrate layer II and the Sb of the first phase change layer 6 on the surface of the substrate layer I are in contact with each other2Te3Contacting the materials and applying pressure, then gradually heating to 250 ℃, wherein the heating rate is 10 ℃/min; keeping the temperature at 250 ℃ for 1h, and reacting GeTe material with Sb under the action of pressurization and annealing2Te3The crystal lattice of the material being gradually coupled toTogether; and finally, cooling to room temperature at a cooling rate of 10 ℃/min to finally form a complete bidirectional superlattice phase change storage unit structure.
The embodiment also provides a phase change memory, which comprises a memory array consisting of a plurality of superlattice phase change units manufactured based on the bidirectional growth method, a control circuit, a word line decoder, a bit line decoder and other peripheral circuits; the word line decoder is electrically connected with a plurality of word lines arranged along the row direction of the memory array; the bit line decoder is electrically connected with a plurality of bit lines arranged along the column direction of the memory array; the control circuit can be realized by a general processor or a logic circuit commonly used in the field; other peripheral circuits include, but are not limited to, power supply circuits, sensing circuits, and the like.
Compared with the existing preparation process, the preparation method of the bidirectional-growth superlattice phase-change unit provided by the invention has the advantages that the phase-change material layers are alternately grown on the two substrates in a bidirectional mode, and then the phase-change material layers on the two substrates are assembled together to form the complete superlattice phase-change film with the phase-change layers arranged alternately in a periodic mode; the method can finish the growth of two layers of component materials in the process of growing a layer of component materials in the traditional unidirectional superlattice, and the growth rate of the superlattice film is improved by nearly one time; meanwhile, the consumption of raw materials used in the growth process is greatly reduced, the production cost of the superlattice film is reduced, and the application of the superlattice phase change storage material in a phase change memory is further promoted effectively on the aspect of industrial production.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method for preparing a bidirectional-growth superlattice phase change unit is characterized by comprising the following steps:
providing a first substrate layer, and depositing a first phase change layer on the first substrate layer;
providing a second substrate layer, and synchronously and alternately depositing a second phase change layer and a first phase change layer on the second substrate layer and the first substrate layer on which the first phase change layer is deposited until the total number of the phase change layers on the first substrate layer and the second substrate layer reaches the required number of layers;
depositing a second phase change layer on the outermost layer of the first substrate layer or the second substrate layer;
and butting the phase change layers on the first substrate layer and the second substrate layer together by adopting a pressurizing and annealing assembly method.
2. The method of claim 1, wherein the pressing and annealing assembly process comprises the steps of:
applying pressure after the phase change layers on the first substrate layer and the second substrate layer are butted, so that the phase change layers on the first substrate layer and the second substrate layer are closely butted together;
heating from room temperature to 200-350 ℃ at the heating rate of 5-50 ℃/min;
keeping the temperature at 200-350 ℃ and the heat preservation time at 0.5-2 h;
after the heat preservation is finished, the temperature is reduced to the room temperature at the cooling speed of 5-10 ℃/min.
3. The production method according to claim 1 or 2, wherein the production method of the first substrate layer includes: depositing an upper electrode on the surface of the first substrate; the upper electrode is a direct support layer of a first phase change layer deposited first on the first substrate layer;
the preparation method of the second substrate layer comprises the following steps:
sequentially depositing a lower electrode and an insulating layer on the surface of the second substrate;
etching a through hole in the insulating layer, wherein the through hole penetrates through the insulating layer;
depositing a heating layer inside the through hole to contact the lower electrode; the plane formed by the heating layer and the insulating layer is a direct support layer of a second phase change layer deposited first on the second substrate layer.
4. The method according to claim 3, wherein the upper and lower electrodes are made of a material selected from the group consisting of Al, W, Ag, Cu, Au, Pt and Ti3W7Any one of the above;
the material of the insulating layer is selected from SiO2、SiC、(ZnS)x(SiO2)100-xAny one of the above; wherein x is an integer greater than 0 and less than 100;
the material of the heating layer is selected from W, TiN and Ti3W7Any one of them.
5. The method of claim 1 or 4, wherein the first phase change layer and the second phase change layer have a lattice mismatch ratio of between 0.1% and 10%.
6. The method according to claim 1 or 4, wherein the number of superlattice periods of the superlattice phase change unit is 5-100;
the deposition thickness ratio of the first phase change layer to the second phase change layer in a single superlattice period is 1: 10-10: 1, and the sum of the deposition thicknesses is 2-10 nm.
7. The production method according to claim 1 or 4, wherein the phase change materials of the first phase change layer and the second phase change layer are selected from any two different In chemical formula from a group consisting of simple Sb, a Ge-Te binary compound, a Ge-Sb binary compound, a Sb-Te binary compound, a Bi-Te binary compound, an In-Se binary compound, a Ge-Sb-Te ternary compound, a Ge-Bi-Te ternary compound, a Ge-Sb-Bi-Te quaternary compound, and compounds formed by element doping thereof;
the doped element is at least one of C, Cu, N, O, Si, Sc, Ti, Ag and In.
8. The method of claim 7, wherein the phase change material of the first phase change layer and the second phase change layer is selected from GeTe, GeSb, Sb2Te3、Bi2Te3、Ge2Sb2Te5、Ge1Sb2Te4Two of which are different.
9. The production method according to claim 1 or 4, wherein the deposition method employs any one of a magnetron sputtering method, an atomic layer deposition method, a molecular beam epitaxy method, a pulsed laser deposition method, a thermal evaporation method, an electrochemical growth method;
and the deposition method of the phase change layer in contact with the first substrate layer and the second substrate layer when the first substrate layer and the second substrate layer are butted adopts an atomic layer deposition method or a molecular beam epitaxy method so as to ensure that the surface of the butted phase change layer has atomic-level flatness.
10. A phase change memory comprising the superlattice phase change cell prepared by the preparation method of any one of claims 1-9.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802088A (en) * 1995-09-28 1998-09-01 Nippondenso Co., Ltd. Stack type semiconductor laser device
CN1379436A (en) * 2001-03-30 2002-11-13 惠普公司 Substrate linkage using selenylation reaction
US20080296619A1 (en) * 2003-10-07 2008-12-04 Board Of Trustees Of The University Of Illinois Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors
US20140252304A1 (en) * 2013-03-11 2014-09-11 National Institute Of Advanced Industrial Science And Technology Phase-change memory and semiconductor recording/reproducing device
CN108899380A (en) * 2018-06-08 2018-11-27 清华大学 Infrared semiconductor avalanche probe and preparation method thereof
CN110155999A (en) * 2019-05-28 2019-08-23 淮阴师范学院 The transfer method and two-dimensional material of a kind of two-dimensional material and its application

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3541350B2 (en) * 1999-08-25 2004-07-07 富士通株式会社 Surface emitting laser and manufacturing method thereof
US8754321B2 (en) * 2009-11-30 2014-06-17 Purdue Research Foundation Laminated thin film metal-semiconductor multilayers for thermoelectrics

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802088A (en) * 1995-09-28 1998-09-01 Nippondenso Co., Ltd. Stack type semiconductor laser device
CN1379436A (en) * 2001-03-30 2002-11-13 惠普公司 Substrate linkage using selenylation reaction
US20080296619A1 (en) * 2003-10-07 2008-12-04 Board Of Trustees Of The University Of Illinois Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors
US20140252304A1 (en) * 2013-03-11 2014-09-11 National Institute Of Advanced Industrial Science And Technology Phase-change memory and semiconductor recording/reproducing device
CN108899380A (en) * 2018-06-08 2018-11-27 清华大学 Infrared semiconductor avalanche probe and preparation method thereof
CN110155999A (en) * 2019-05-28 2019-08-23 淮阴师范学院 The transfer method and two-dimensional material of a kind of two-dimensional material and its application

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
H Qian,et al..Low work function of crystalline GeTe/Sb2Te3 superlattice-like films induced by Te dangling bonds.《Journal of Physics D: Applied Physics》.2016,第49卷pp 495302. *

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