CN110534562A - Static random access memory - Google Patents
Static random access memory Download PDFInfo
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- CN110534562A CN110534562A CN201910820649.0A CN201910820649A CN110534562A CN 110534562 A CN110534562 A CN 110534562A CN 201910820649 A CN201910820649 A CN 201910820649A CN 110534562 A CN110534562 A CN 110534562A
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- 238000000605 extraction Methods 0.000 claims abstract description 40
- 230000015654 memory Effects 0.000 claims abstract description 39
- 238000003860 storage Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 239000007836 KH2PO4 Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002113 barium titanate Inorganic materials 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000402 monopotassium phosphate Inorganic materials 0.000 claims description 3
- 235000019796 monopotassium phosphate Nutrition 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- GNSKLFRGEWLPPA-UHFFFAOYSA-M potassium dihydrogen phosphate Chemical compound [K+].OP(O)([O-])=O GNSKLFRGEWLPPA-UHFFFAOYSA-M 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The invention discloses a kind of static random access memory, storage unit includes 6 fin formula field effect transistors；Each fin formula field effect transistor includes fin body, gate structure, source region and drain region；The extending direction of fin body and gate structure is vertical；Gate structure includes gate dielectric layer and grid conducting material layer, negative capacitance material layer is formed on the surface for extending to the grid conducting material layer outside fin body, the contact hole for drawing grid conducting material layer is formed in the top of negative capacitance material layer, is connected to the grid extraction electrode formed by front metal layer interconnection structure by the contact hole at the top of negative capacitance material layer；Negative capacitance material layer forms negative capacitance between grid conducting material layer and grid extraction electrode and is connected on the medium layer capacitance being made of semiconductor substrate, gate dielectric layer and grid conducting material layer.The present invention can reduce the subthreshold swing of the transistor of static random access memory, so as to reduce the operation voltage of memory, reduce energy consumption and calorific value.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of static random access memory (SRAM).
Background technique
For Static Random Access Memory since speed is fast, the excellent of storage inside data can be saved by not needing refresh circuit
Point, mainly as the cache between central processing unit (CPU) and main memory, but its power consumption is larger, and fever is high, and integrated level is low etc.
Disadvantage makes it be mainly used for critical system to improve efficiency.Evolution and fin field with integrated circuit fabrication process node
The maturation of effect transistor (FinFET) manufacturing technology, the size of the SRAM based on FinFET is smaller and smaller, but due to device Asia
The threshold value amplitude of oscillation (SS) room temperature physics limit value about 60mV/dec, SS indicate grid voltage when every subthreshold current for changing 10 times
Knots modification, the room temperature physics limit value of SS cause SRAM operation voltage to be difficult to decrease, and the high problem of energy consumption is urgently to be resolved.
As shown in Figure 1, being the circuit diagram of the storage unit of existing static random access memory, which is deposited
Reservoir is based on FinFET；As shown in Fig. 2, being the domain of existing static random access memory；Existing static random-access is deposited
Reservoir includes the array structure as made of the arrangement of multiple 101 ranks of storage unit.
Each storage unit 101 include the first transfer tube PG101, the second transfer tube PG102, trombone slide PL101 on first,
Trombone slide PL102, the lower trombone slide PD102 of the first lower trombone slide PD101 and second on second；The first transfer tube PG101, described second
Transfer tube PG102, the first lower trombone slide PD101 and the second lower trombone slide PD102 are NMOS tube, trombone slide on described first
Trombone slide PL102 is PMOS tube on PL101 and described second.
The NMOS tube and the PMOS tube all use fin formula field effect transistor.
As shown in Fig. 2, each fin formula field effect transistor includes fin body 104, gate structure, source region and drain region；It is described
Fin body 104 is made of patterned semiconductor substrate.
The fin body 104 is vertical with the extending direction of the gate structure, as shown in Fig. 2, the extension of the gate structure
Direction, that is, grid bar shaped 105 extending direction；On the extending direction along the gate structure, the gate structure is covered on institute
The two sides or the gate structure for stating fin body 104 are covered on two sides and the top surface of the fin body 104, by the grid
The side for the fin body 104 that pole structure is covered or top surface form channel；In the extending direction along the fin body 104
On, the source region and the drain region are formed in the two sides of the gate structure, and the source region is connected with the drain region by channel
It connects.
The gate structure includes gate dielectric layer and grid conducting material layer, and the grid conducting material layer can pass through top
Corresponding contact hole 108 is connected to the grid extraction electrode formed by front metal layer interconnection structure.
As shown in Fig. 2, in each storage unit 101, the grid extraction electrode of the first transfer tube PG101 and institute
The grid extraction electrode for stating the second transfer tube PG102 passes through respectively such as the corresponding contact hole of label 107c and 107d in Fig. 2
It is connected to the wordline WL being made of front metal layer (not shown), label 106a and 106b is also the label of corresponding contact hole,
The corresponding right oblique line graphics field of label 109 corresponds to contact hole and cuts off (CT cut) structure, and contact hole cutting 109 makes corresponding
It is disconnected between contact hole 106a and 107c and makes to disconnect between corresponding contact hole 106b and 107d.Shown in Fig. 2
Domain in, be not drawn into the domain of front metal layer.
The source region of the first transfer tube PG101 is connected to be made of front metal layer first by contact hole 106c
Line BL, the source region of the second transfer tube PG102 are connected to the second bit line being made of front metal layer by contact hole 106d
BLB, the second bit line BLB are the reverse phase bit line of the first bit line BL.As seen from Figure 2, in contact hole 106c and
The corresponding strip structure two sides 106d are both provided with corresponding contact hole cutting 109.
The drain region of the first transfer tube PG101, the drain region of trombone slide PL101, the first lower trombone slide on described first
The drain region of PD101, on described second the grid extraction electrode of trombone slide PL102 and the second lower trombone slide PD102 grid extraction electrode
It is all connected to the first memory node 107a.
The drain region of the second transfer tube PG102, the drain region of trombone slide PL102, the second lower trombone slide on described second
The drain region of PD102, on described first the grid extraction electrode of trombone slide PL101 and the first lower trombone slide PD101 grid extraction electrode
Be all connected to the second memory node 107b, the first memory node 107a and the second memory node 107b each other reverse phase and
Interlocking.
The source region of trombone slide PL102 is all connected to supply voltage in the source region of trombone slide PL101 and described second on described first
VCC。
The source region of described first lower trombone slide PD101 and the source region of the second lower trombone slide PD102 are all grounded VSS.
On the domain structure of each storage unit 101:
The fin body 104 of the fin body 104 of the first transfer tube PG101 and the first lower trombone slide PD101 are all by first
Fin body 104a composition.
The fin body 104 of trombone slide PL101 is made of Article 2 fin body 104b on described first.
The fin body 104 of trombone slide PL102 is made of Article 3 fin body 104c on described second.
The fin body 104 of the fin body 104 of the second transfer tube PG102 and the second lower trombone slide PD102 are all by Article 4
Fin body 104d composition.First fin body, the Article 2 fin body, the Article 3 fin body and institute are indicated in order to clearer
Article 4 fin body is stated, this four fin bodies are individually indicated with label 104a, 104b, 104c and 104d.
First fin body 104a, the Article 2 fin body 104b, the Article 3 fin body 104c and the Article 4
Fin body 104d is parallel to each other and arranges along the direction vertical with each fin body 104 is done.
On the domain structure of each storage unit 101:
The grid conducting material layer of the first transfer tube PG101, on described second trombone slide PL102 grid conducting material
The grid conducting material layer of layer and the second lower trombone slide PD102 all extend on first grid bar shaped 105a, and described second
The grid conducting material layer of the grid conducting material layer of upper trombone slide PL102 and the second lower trombone slide PD102 link together, institute
State the interruption of the grid conducting material layer of trombone slide PL102 on the grid conducting material layer and described second of the first transfer tube PG101
Open connection.
The grid conducting material layer of described first lower trombone slide PD101, on described first trombone slide PL101 grid conducting material
The grid conducting material layer of layer and the second transfer tube PG102 all extend on second grid bar shaped 105b, and described first
The grid conducting material layer of the grid conducting material layer of upper trombone slide PL101 and the first lower trombone slide PD101 link together, institute
State the interruption of the grid conducting material layer of trombone slide PL101 on the grid conducting material layer and described first of the second transfer tube PG102
Open connection.
The first grid bar shaped 105a is parallel with the second grid bar shaped 105b.
The first transfer tube PG101 and the first lower trombone slide PD101 share drain region, the second transfer tube PG102
Drain region is shared with the described second lower trombone slide PD102.
The drain region of described first lower trombone slide PD101, trombone slide on the drain region and described second of trombone slide PL101 on described first
It is linked together between the grid extraction electrode of PL102 by contact hole 106a and forms the first memory node 107a.
The drain region of described second lower trombone slide PD102, trombone slide on the drain region and described first of trombone slide PL102 on described second
It is linked together between the grid extraction electrode of PL101 by contact hole 106b and forms the second memory node 107b.
The first memory node 107a and the second memory node 107b be located at the first grid bar shaped 105a and
Between the second grid bar shaped 105b.
The first bit line BL and the second bit line BLB are parallel with the first grid bar shaped 105a, and described first
Bit line BL is located at the outside of the first grid bar shaped 105a, and the second bit line BLB is located at the second grid bar shaped 105b
Outside.
The structure of a storage unit 101 is described in detail in Fig. 2, it is each described for the entire array structure
The structure of storage unit 101 is identical, and domain structure is also identical or is mutually in mirror-image structure.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of static random access memories, can reduce static random and deposit
The subthreshold swing of the transistor of access to memory reduces energy consumption and calorific value so as to reduce the operation voltage of memory.
In order to solve the above technical problems, static random access memory provided by the invention includes by multiple memory cell rows
Array structure made of column arrangement.
Each storage unit includes the first transfer tube, the second transfer tube, trombone slide on first, on second under trombone slide, first
Trombone slide and the second lower trombone slide；First transfer tube, second transfer tube, the first lower trombone slide and the second lower trombone slide
It is all NMOS tube, trombone slide is all PMOS tube on trombone slide and described second on described first.
The NMOS tube and the PMOS tube all use fin formula field effect transistor.
Each fin formula field effect transistor includes fin body, gate structure, source region and drain region；The fin body is by patterned
The extending direction of semiconductor substrate composition, the fin body and the gate structure is vertical；In the extension side along the gate structure
Upwards, the gate structure is covered on the two sides of the fin body or the gate structure is covered on the two sides of the fin body
And top surface, the side of the fin body covered by the gate structure or top surface form channel；Along the fin
On the extending direction of body, the source region and the drain region are formed in the two sides of the gate structure, the source region and the drain region
It is connected by channel.
The gate structure includes gate dielectric layer and grid conducting material layer, is extending to the grid outside the fin body
Negative capacitance material layer is formed on the surface of pole conductive material layer, the contact hole for drawing the grid conducting material layer is formed in institute
The top for stating negative capacitance material layer is connected to by the contact hole at the top of the negative capacitance material layer and is mutually linked by front metal layer
The grid extraction electrode being configured to；Negative capacitance material layer shape between the grid conducting material layer and the grid extraction electrode
At negative capacitance and it is connected on the dielectric layer being made of the semiconductor substrate, the gate dielectric layer and the grid conducting material layer
On capacitor, to reduce the subthreshold swing of the fin formula field effect transistor.
A further improvement is that in each storage unit, the grid extraction electrode of first transfer tube and described
The grid extraction electrode of second transfer tube is all connected to the wordline being made of front metal layer, the source region of first transfer tube
The first bit line being made of front metal layer is connected to by contact hole, the source region of second transfer tube is connected by contact hole
To the second bit line being made of front metal layer, second bit line is the reverse phase bit line of first bit line.
The drain region of first transfer tube, the drain region of trombone slide on described first, the drain region of the first lower trombone slide, described the
The grid extraction electrode of the grid extraction electrode of trombone slide and the second lower trombone slide is all connected to the first memory node on two.
The drain region of second transfer tube, the drain region of trombone slide on described second, the drain region of the second lower trombone slide, described the
The grid extraction electrode of the grid extraction electrode of trombone slide and the first lower trombone slide is all connected to the second memory node on one, and described first
Memory node and second memory node reverse phase and interlocking each other.
The source region of trombone slide is all connected to supply voltage in the source region of trombone slide and described second on described first.
The source region of described first lower trombone slide and the source region of the second lower trombone slide are all grounded.
A further improvement is that on the domain structure of each storage unit:
The fin body of the fin body of first transfer tube and the first lower trombone slide is all made of first fin body.
The fin body of trombone slide is made of Article 2 fin body on described first.
The fin body of trombone slide is made of Article 3 fin body on described second.
The fin body of the fin body of second transfer tube and the second lower trombone slide is all made of Article 4 fin body.
First fin body, the Article 2 fin body, the Article 3 fin body and the Article 4 fin body are parallel to each other
And it is arranged along the direction vertical with each fin body is done.
A further improvement is that on the domain structure of each storage unit:
The grid conducting material layer of first transfer tube, on described second trombone slide grid conducting material layer and described
The grid conducting material layer of two lower trombone slides all extends in first grid bar shaped, and on described second trombone slide grid conducting material
The grid conducting material layer of layer and the described second lower trombone slide links together, the grid conducting material layer of first transfer tube and
It is disconnected between the grid conducting material layer of trombone slide on described second.
The grid conducting material layer of described first lower trombone slide, the grid conducting material layer of trombone slide and described the on described first
The grid conducting material layer of two transfer tubes all extends in second grid bar shaped, and on described first trombone slide grid conducting material
The grid conducting material layer of layer and the described first lower trombone slide links together, the grid conducting material layer of second transfer tube and
It is disconnected between the grid conducting material layer of trombone slide on described first.
The first grid bar shaped and the second grid parallel strip.
A further improvement is that first transfer tube and the first lower trombone slide share drain region, second transfer tube
Drain region is shared with the described second lower trombone slide.
The drain region of described first lower trombone slide, on described first on the drain region and described second of trombone slide trombone slide grid extraction electrode
Between linked together by contact hole and form first memory node.
The drain region of described second lower trombone slide, on described second on the drain region and described first of trombone slide trombone slide grid extraction electrode
Between linked together by contact hole and form second memory node.
First memory node and second memory node are located at the first grid bar shaped and the second grid
Between bar shaped.
A further improvement is that first bit line and second bit line all with the first grid parallel strip, institute
The outside that the first bit line is located at the first grid bar shaped is stated, second bit line is located at the outside of the second grid bar shaped.
A further improvement is that the material of the negative capacitance material layer includes ferroelectric material.
A further improvement is that ferroelectric material used by the negative capacitance material layer includes the material containing Zr, Ba or Sr.
A further improvement is that ferroelectric material used by the negative capacitance material layer include HfZrO2, BaTiO3,
KH2PO4 or NBT.
A further improvement is that being formed with the first boundary between the negative capacitance material layer and the grid conducting material layer
Face buffer layer is formed with second contact surface buffer layer between the corresponding contact hole of the negative capacitance material layer and top.
A further improvement is that the vertical view face structure of each negative capacitance material layer is rectangle, institute on domain structure
The length sides for stating negative capacitance material layer are parallel with the extending direction of the corresponding grid conducting material layer.
The width of the negative capacitance material layer is more than or equal to the width of the grid conducting material layer, in the Gate Electrode Conductive
In the width direction of material layer, the negative capacitance material layer extends to the outside of the grid conducting material layer.
Alternatively, the width of the negative capacitance material layer is less than the width of the grid conducting material layer.
A further improvement is that the material of the gate dielectric layer includes silica, silicon oxynitride or high dielectric constant material.
A further improvement is that the high dielectric constant material includes hafnium oxide.
A further improvement is that the material of the grid conducting material layer is polysilicon.
A further improvement is that the material of the grid conducting material layer is metal.
A further improvement is that the metal material of the grid conducting material layer includes Al or W.
A further improvement is that in the corresponding fin formula field effect transistor of the NMOS tube, the source region and the leakage
Qu Douwei N+ doping, the fin body are p-type doping.
In the corresponding fin formula field effect transistor of the PMOS tube, the source region and the drain region are all P+ doping, institute
Stating fin body is n-type doping.
The transistor of static random access memory of the invention all uses fin formula field effect transistor, fin body and grid knot
The extending direction of structure is vertical, and the present invention is formed with negative capacitance material on the surface for extending to the grid conducting material layer outside fin body
The bed of material, the contact hole for drawing grid conducting material layer are formed in the top of negative capacitance material layer and thereby the medium in gate structure
One negative capacitance of series connection, since negative capacitance has the function of voltage amplification, therefore can make external gate voltage on the basis of layer capacitance
It is transmitted to the increase of channel surface voltage, can make the variation of lesser external gate voltage that can generate the change of bigger subthreshold current
Change, so as to reduce subthreshold swing, and thereby the operation voltage of memory can be reduced, reduces energy consumption and calorific value.
In addition, negative capacitance material layer of the invention is arranged at the top of grid conducting material layer and is located at grid conducting material layer
The region of corresponding contact hole, thus negative capacitance material layer of the invention do not need to be arranged gate dielectric layer within the gate structure and
Between grid conducting material layer, has the characteristics that process structure is simple and will not adversely affect to gate structure, facilitate reality
Existing technique is integrated.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the circuit diagram of the storage unit of existing static random access memory；
Fig. 2 is the domain of existing static random access memory；
Fig. 3 is the circuit diagram of the storage unit of static random access memory of the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of fin formula field effect transistor used by the embodiment of the present invention；
Fig. 5 is the domain of static random access memory of the embodiment of the present invention.
Specific embodiment
As shown in figure 3, being the circuit diagram of the storage unit 1 of static random access memory of the embodiment of the present invention；Such as Fig. 4 institute
Show, is the structural schematic diagram of fin formula field effect transistor used by the embodiment of the present invention；As shown in figure 5, being implementation of the present invention
The domain of example static random access memory；Static random access memory of the embodiment of the present invention includes by multiple storage units 1
Array structure made of ranks arrangement.
Each storage unit 1 includes trombone slide PL1, the second pull-up on the first transfer tube PG1, the second transfer tube PG2, first
Pipe PL2, the lower trombone slide PD2 of the first lower trombone slide PD1 and second；The first transfer tube PG1, the second transfer tube PG2, described
Once the trombone slide PD1 and second lower trombone slide PD2 is NMOS tube, trombone slide PL2 on trombone slide PL1 and described second on described first
It is all PMOS tube.
The NMOS tube and the PMOS tube all use fin formula field effect transistor.
As shown in Fig. 2, each fin formula field effect transistor includes fin body 4, gate structure, source region 201 and drain region 202；
The fin body 4 is made of patterned semiconductor substrate.
The fin body 4 is vertical with the extending direction of the gate structure, as shown in figure 5, the extension side of the gate structure
To the extending direction of i.e. grid bar shaped 5, the cross-section structure of Fig. 4 is the cross-section structure of the extending direction along the fin body 4；Along institute
It states on the extending direction of gate structure, the gate structure is covered on the two sides of the fin body 4 or the gate structure covers
The two sides in the fin body 4 and top surface are covered, the side of the fin body 4 covered by the gate structure or top table
Face forms channel；On the extending direction along the fin body 4, the source region 201 and the drain region 202 are formed in the grid knot
The two sides of structure, the source region 201 are connected with the drain region 202 by channel.
The gate structure includes gate dielectric layer 203 and grid conducting material layer 204, is being extended to outside the fin body 4
The grid conducting material layer 204 surface on be formed with negative capacitance material layer 205, in Fig. 4, in order to indicate described well
Negative capacitance material layer 205 is located on the surface of the grid conducting material layer 204, and negative capacitance material layer 205 is also disposed in Fig. 4
In；Can be seen that from domain structure shown in fig. 5 is not all to be formed on the surface of all grid conducting material layers 204
Have the negative capacitance material layer 205, thus the domain structure of cross-section structure and Fig. 5 incorporated by reference to Fig. 4 come together to understand it is of the invention
The structure feature of negative capacitance material layer 205.
The contact hole 8 for drawing the grid conducting material layer 204 is formed in the top of the negative capacitance material layer 205, leads to
The contact hole 8 for crossing 205 top of negative capacitance material layer, which is connected to, draws electricity by the grid that 206 interconnection structure of front metal layer is formed
Pole individually indicates described negative with label 206 in Fig. 4 since in semiconductor integrated circuit, front metal layer generally includes multilayer
The front metal layer at corresponding 8 top of contact hole of capacitance material layer 205.
The negative capacitance material layer 205 forms negative between the grid conducting material layer 204 and the grid extraction electrode
Capacitor is simultaneously connected on the medium being made of the semiconductor substrate, the gate dielectric layer 203 and the grid conducting material layer 204
On layer capacitance, to reduce the subthreshold swing of the fin formula field effect transistor.
As shown in figure 5, in each storage unit 1, the grid extraction electrode of the first transfer tube PG1 and described
The grid extraction electrode of two transfer tube PG2 pass through respectively as the corresponding contact hole of label 7c and 7d in Fig. 5 be all connected to by
The wordline WL of front metal layer (not shown) composition；Label 6a and 6b is also the label of corresponding contact hole, the corresponding right side of label 9
Oblique line graphics field corresponds to contact hole and cuts off structure, and contact hole cutting 9 makes to disconnect between corresponding contact hole 6a and 7c
And make to disconnect between corresponding contact hole 6b and 7d.In domain shown in fig. 5, it is not drawn into the domain of front metal layer.
The source region 201 of the first transfer tube PG1 is connected to be made of front metal layer first by contact hole 6c
Line BL, the source region 201 of the second transfer tube PG2 are connected to the second bit line being made of front metal layer by contact hole 6d
BLB, the second bit line BLB are the reverse phase bit line of the first bit line BL.As seen from Figure 5, in contact hole 6c and 6d couples
The strip structure two sides answered are both provided with corresponding contact hole cutting 9.
The drain region 202 of the first transfer tube PG1, the drain region 202 of trombone slide PL1, the first lower trombone slide on described first
The drain region 202 of PD1, the grid extraction electrode of the grid extraction electrode of trombone slide PL2 and the second lower trombone slide PD2 all connect on described second
It is connected to the first memory node 7a.
The drain region 202 of the second transfer tube PG2, the drain region 202 of trombone slide PL2, the second lower trombone slide on described second
The drain region 202 of PD2, the grid extraction electrode of the grid extraction electrode of trombone slide PL1 and the first lower trombone slide PD1 all connect on described first
It is connected to the second memory node 7b, the first memory node 7a and the second memory node 7b reverse phase and interlocking each other.
The source region 201 of trombone slide PL2 is all connected to power supply electricity in the source region 201 of trombone slide PL1 and described second on described first
Press VCC.
The source region 201 of described first lower trombone slide PD1 and the source region 201 of the second lower trombone slide PD2 are all grounded VSS.
On the domain structure of each storage unit 1:
The fin body 4 of the fin body 4 of the first transfer tube PG1 and the first lower trombone slide PD1 are all by first fin body 4a group
At.
The fin body 4 of trombone slide PL1 is made of Article 2 fin body 4b on described first.
The fin body 4 of trombone slide PL2 is made of Article 3 fin body 4c on described second.
The fin body 4 of the fin body 4 of the second transfer tube PG2 and the second lower trombone slide PD2 are all by Article 4 fin body 4d group
At.First fin body, the Article 2 fin body, the Article 3 fin body and the Article 4 fin are indicated in order to clearer
Body, this four fin bodies are individually indicated with label 4a, 4b, 4c and 4d.
First fin body 4a, the Article 2 fin body 4b, the Article 3 fin body 4c and the Article 4 fin body 4d
Do the direction arrangement vertical with each fin body 4 in parallel to each other and edge.
On the domain structure of each storage unit 1:
The grid conducting material layer 204 of the first transfer tube PG1, on described second trombone slide PL2 grid conducting material
The grid conducting material layer 204 of layer 204 and the second lower trombone slide PD2 all extend on first grid bar shaped 5a, and described the
The grid conducting material layer 204 of the grid conducting material layer 204 of trombone slide PL2 and the second lower trombone slide PD2 are connected to one on two
It rises, the grid conducting material layer 204 of trombone slide PL2 on the grid conducting material layer 204 and described second of the first transfer tube PG1
Between disconnect.
The grid conducting material layer 204 of described first lower trombone slide PD1, on described first trombone slide PL1 grid conducting material
The grid conducting material layer 204 of 204 and the second transfer tube PG2 of layer all extends on second grid bar shaped 5b, and described the
The grid conducting material layer 204 of the grid conducting material layer 204 of trombone slide PL1 and the first lower trombone slide PD1 are connected to one on one
It rises, the grid conducting material layer 204 of trombone slide PL1 on the grid conducting material layer 204 and described first of the second transfer tube PG2
Between disconnect.
The first grid bar shaped 5a is parallel with the second grid bar shaped 5b.
The first transfer tube PG1 and the first lower trombone slide PD1 share drain region 202, the second transfer tube PG2 and institute
It states the second lower trombone slide PD2 and shares drain region 202.
The drain region 202 of described first lower trombone slide PD1, trombone slide on the drain region 202 and described second of trombone slide PL1 on described first
It is linked together between the grid extraction electrode of PL2 by contact hole 6a and forms the first memory node 7a.
The drain region 202 of described second lower trombone slide PD2, trombone slide on the drain region 202 and described first of trombone slide PL2 on described second
It is linked together between the grid extraction electrode of PL1 by contact hole 6b and forms the second memory node 7b.
The first memory node 7a and the second memory node 7b is located at the first grid bar shaped 5a and described
Between two grid bar shaped 5b.
The first bit line BL and the second bit line BLB are parallel with the first grid bar shaped 5a, and described first
Line BL is located at the outside of the first grid bar shaped 5a, and the second bit line BLB is located at the outside of the second grid bar shaped 5b.
The structure of a storage unit 1 is described in detail in Fig. 5, it is each described to deposit for the entire array structure
The structure of storage unit 1 is identical, and domain structure is also identical or is mutually in mirror-image structure.
The material of the negative capacitance material layer 205 includes ferroelectric material.Ferroelectricity used by the negative capacitance material layer 205
Material includes the material containing Zr, Ba or Sr.It is preferably selected as, ferroelectric material used by the negative capacitance material layer 205 includes
HfZrO2, BaTiO3, KH2PO4 or NBT.The shape between the negative capacitance material layer 205 and the grid conducting material layer 204
At there is the first interface buffer layer, second is formed between the corresponding contact hole 8 of the negative capacitance material layer 205 and top
Interface buffer layer.
On domain structure, the vertical view face structure of each negative capacitance material layer 205 is rectangle, the negative electricity capacity materials
The length sides of layer 205 are parallel with the extending direction of the corresponding grid conducting material layer 204.The negative capacitance material layer 205
Width be more than or equal to the grid conducting material layer 204 width, in the width direction of the grid conducting material layer 204
On, the negative capacitance material layer 205 extends to the outside of the grid conducting material layer 204.Also can in other embodiments are as follows:
The width of the negative capacitance material layer 205 is less than the width of the grid conducting material layer 204.
The material of the gate dielectric layer 203 includes silica, silicon oxynitride or high dielectric constant material.The high dielectric is normal
Number material includes hafnium oxide.
The material of the grid conducting material layer 204 is polysilicon.Also can in other embodiments are as follows: the Gate Electrode Conductive
The material of material layer 204 is metal.The metal material of the grid conducting material layer 204 includes Al or W.
Wherein, when the gate dielectric layer 203 is used using high dielectric constant material and the grid conducting material layer 204
When metal material, gate structure described in Zeus is HKMG.In the gate dielectric layer 203, in high dielectric constant material layer and half
Interfacial TCO layer is usually also formed between conductor substrate surface, in the high dielectric constant material layer and the grid conducting material layer
Work-function layer is further typically provided between 204 metal material, moreover it is possible to barrier layer be set as needed.
In the corresponding fin formula field effect transistor of the NMOS tube, the source region 201 and the drain region 202 are all mixed for N+
Miscellaneous, the fin body 4 is p-type doping.
In the corresponding fin formula field effect transistor of the PMOS tube, the source region 201 and the drain region 202 are all mixed for P+
Miscellaneous, the fin body 4 is n-type doping.
The transistor of static random access memory of the embodiment of the present invention all uses fin formula field effect transistor, 4 He of fin body
The extending direction of gate structure is vertical, and the present invention is formed on the surface for extending to the grid conducting material layer 204 outside fin body 4
There is negative capacitance material layer 205, the contact hole 8 for drawing grid conducting material layer 204 is formed in the top of negative capacitance material layer 205 simultaneously
To a negative capacitance of connecting on the basis of the medium layer capacitance of gate structure, since negative capacitance has the work of voltage amplification
With, therefore external gate voltage can be made to be transmitted to the increase of channel surface voltage, the variation of lesser external gate voltage can be enable to produce
The variation of raw bigger subthreshold current can finally break through the Asia of transistor in the prior art so as to reduce subthreshold swing
The limit that the threshold value amplitude of oscillation is 60mV/dec limits, and thereby can reduce the operation voltage of memory, reduces energy consumption and calorific value.
In addition, the setting of negative capacitance material layer 205 of the embodiment of the present invention is at 204 top of grid conducting material layer and is located at grid
The region of the corresponding contact hole 8 of pole conductive material layer 204, therefore the negative capacitance material layer 205 of the embodiment of the present invention does not need to set
It sets between gate dielectric layer 203 and grid conducting material layer 204 within the gate structure, has process structure simply and to grid knot
The characteristics of structure will not adversely affect facilitates and realizes that technique is integrated.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of static random access memory, it is characterised in that: static random access memory includes by multiple storage units
Array structure made of ranks arrangement；
Each storage unit includes the first transfer tube, the second transfer tube, trombone slide on first, trombone slide, the first lower trombone slide on second
With the second lower trombone slide；First transfer tube, second transfer tube, the first lower trombone slide and the second lower trombone slide are all
NMOS tube, trombone slide is all PMOS tube on trombone slide and described second on described first；
The NMOS tube and the PMOS tube all use fin formula field effect transistor；
Each fin formula field effect transistor includes fin body, gate structure, source region and drain region；The fin body is partly led by patterned
The extending direction of body substrate composition, the fin body and the gate structure is vertical；On the extending direction along the gate structure,
The gate structure is covered on the two sides of the fin body or the gate structure is covered on the two sides and top of the fin body
Portion surface, the side of the fin body covered by the gate structure or top surface form channel；Along the fin body
On extending direction, the source region and the drain region are formed in the two sides of the gate structure, and the source region and the drain region pass through
Channel is connected；
The gate structure includes gate dielectric layer and grid conducting material layer, is led in the grid extended to outside the fin body
Negative capacitance material layer is formed on the surface of material layer, the contact hole for drawing the grid conducting material layer is formed in described bear
The top of capacitance material layer is connected to by the contact hole at the top of the negative capacitance material layer by front metal layer interconnection structure shape
At grid extraction electrode；The negative capacitance material layer forms negative between the grid conducting material layer and the grid extraction electrode
Capacitor is simultaneously connected on the medium layer capacitance being made of the semiconductor substrate, the gate dielectric layer and the grid conducting material layer
On, to reduce the subthreshold swing of the fin formula field effect transistor.
2. static random access memory as described in claim 1, it is characterised in that: in each storage unit, described
The grid extraction electrode of one transfer tube and the grid extraction electrode of second transfer tube are all connected to by front metal layer
The wordline of composition, the source region of first transfer tube are connected to the first bit line being made of front metal layer, institute by contact hole
The source region for stating the second transfer tube is connected to the second bit line being made of front metal layer by contact hole, and second bit line is institute
State the reverse phase bit line of the first bit line；
The drain region of first transfer tube, the drain region of trombone slide on described first, the drain region of the first lower trombone slide, on described second
The grid extraction electrode of the grid extraction electrode of trombone slide and the second lower trombone slide is all connected to the first memory node；
The drain region of second transfer tube, the drain region of trombone slide on described second, the drain region of the second lower trombone slide, on described first
The grid extraction electrode of the grid extraction electrode of trombone slide and the first lower trombone slide is all connected to the second memory node, first storage
Node and second memory node reverse phase and interlocking each other；
The source region of trombone slide is all connected to supply voltage in the source region of trombone slide and described second on described first；
The source region of described first lower trombone slide and the source region of the second lower trombone slide are all grounded.
3. static random access memory as claimed in claim 2, which is characterized in that in the domain knot of each storage unit
On structure:
The fin body of the fin body of first transfer tube and the first lower trombone slide is all made of first fin body；
The fin body of trombone slide is made of Article 2 fin body on described first；
The fin body of trombone slide is made of Article 3 fin body on described second；
The fin body of the fin body of second transfer tube and the second lower trombone slide is all made of Article 4 fin body；
First fin body, the Article 2 fin body, the Article 3 fin body and the Article 4 fin body is parallel to each other and edge
Do the direction arrangement vertical with each fin body.
4. static random access memory as claimed in claim 3, which is characterized in that in the domain knot of each storage unit
On structure:
The grid conducting material layer of first transfer tube, on described second under the grid conducting material layer and described second of trombone slide
The grid conducting material layer of trombone slide all extends in first grid bar shaped, and on described second the grid conducting material layer of trombone slide and
The grid conducting material layer of described second lower trombone slide links together, the grid conducting material layer of first transfer tube and described
It is disconnected between the grid conducting material layer of trombone slide on second；
The grid conducting material layer of described first lower trombone slide, the grid conducting material layer and described second of trombone slide passes on described first
The grid conducting material layer of defeated pipe all extends in second grid bar shaped, and on described first the grid conducting material layer of trombone slide and
The grid conducting material layer of described first lower trombone slide links together, the grid conducting material layer of second transfer tube and described
It is disconnected between the grid conducting material layer of trombone slide on first；
The first grid bar shaped and the second grid parallel strip.
5. static random access memory as claimed in claim 4, it is characterised in that: first transfer tube and described first
Lower trombone slide shares drain region, and second transfer tube and the second lower trombone slide share drain region；
The drain region of described first lower trombone slide, on described first on the drain region and described second of trombone slide between the grid extraction electrode of trombone slide
It is linked together by contact hole and forms first memory node；
The drain region of described second lower trombone slide, on described second on the drain region and described first of trombone slide between the grid extraction electrode of trombone slide
It is linked together by contact hole and forms second memory node；
First memory node and second memory node are located at the first grid bar shaped and the second grid bar shaped
Between.
6. static random access memory as claimed in claim 5, it is characterised in that: first bit line and the second
For line all with the first grid parallel strip, first bit line is located at the outside of the first grid bar shaped, the second
Line is located at the outside of the second grid bar shaped.
7. static random access memory as described in claim 1, it is characterised in that: the material packet of the negative capacitance material layer
Include ferroelectric material.
8. static random access memory as claimed in claim 7, it is characterised in that: used by the negative capacitance material layer
Ferroelectric material includes the material containing Zr, Ba or Sr.
9. static random access memory as claimed in claim 8, it is characterised in that: used by the negative capacitance material layer
Ferroelectric material includes HfZrO2, BaTiO3, KH2PO4 or NBT.
10. static random access memory as described in claim 1, it is characterised in that: in the negative capacitance material layer and institute
It states and is formed with the first interface buffer layer between grid conducting material layer, described connect the negative capacitance material layer and top are corresponding
Second contact surface buffer layer is formed between contact hole.
11. static random access memory as described in claim 1, it is characterised in that: on domain structure, each negative electricity
The vertical view face structure of capacity materials layer is rectangle, the length sides of the negative capacitance material layer and the corresponding grid conducting material
The extending direction of layer is parallel；
The width of the negative capacitance material layer is more than or equal to the width of the grid conducting material layer, in the grid conducting material
In the width direction of layer, the negative capacitance material layer extends to the outside of the grid conducting material layer；
Alternatively, the width of the negative capacitance material layer is less than the width of the grid conducting material layer.
12. static random access memory as described in claim 1, it is characterised in that: the material of the gate dielectric layer includes
Silica, silicon oxynitride or high dielectric constant material；The high dielectric constant material includes hafnium oxide.
13. static random access memory as claimed in claim 10, it is characterised in that: the material of the grid conducting material layer
Material is polysilicon.
14. static random access memory as claimed in claim 10, it is characterised in that: the material of the grid conducting material layer
Material is metal.
15. static random access memory as described in claim 1, it is characterised in that: in the corresponding fin of the NMOS tube
In field effect transistor, the source region and the drain region are all N+ doping, and the fin body is p-type doping；
In the corresponding fin formula field effect transistor of the PMOS tube, the source region and the drain region are all P+ doping, the fin
Body is n-type doping.
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| US20180182860A1 (en) * | 2016-12-27 | 2018-06-28 | United Microelectronics Corp. | Multi-threshold voltage semiconductor device |
| WO2019065208A1 (en) * | 2017-09-29 | 2019-04-04 | 国立研究開発法人産業技術総合研究所 | Semiconductor device |
| US20190115444A1 (en) * | 2017-10-13 | 2019-04-18 | Globalfoundries Inc. | Negative capacitance integration through a gate contact |
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| CN102122660A (en) * | 2009-12-07 | 2011-07-13 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN106653756A (en) * | 2015-10-29 | 2017-05-10 | 台湾积体电路制造股份有限公司 | Static random access memory |
| US20180182860A1 (en) * | 2016-12-27 | 2018-06-28 | United Microelectronics Corp. | Multi-threshold voltage semiconductor device |
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