CN110526200B - Out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beam and preparation method thereof - Google Patents
Out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beam and preparation method thereof Download PDFInfo
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- CN110526200B CN110526200B CN201910683513.XA CN201910683513A CN110526200B CN 110526200 B CN110526200 B CN 110526200B CN 201910683513 A CN201910683513 A CN 201910683513A CN 110526200 B CN110526200 B CN 110526200B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/12—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by alteration of electrical resistance
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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Abstract
The invention discloses an out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beams and a preparation method thereof, wherein the chip comprises two symmetrically arranged mass blocks, the outer end surfaces of the two mass blocks are respectively connected with an outer frame of the chip, and the inner end surfaces are connected through two groups of sensitive beams; four sensitive Liang Zucheng Wheatstone full bridge circuits; the mass blocks are used for directly sensing out-of-plane acceleration signals, when the chip is subjected to acceleration in the Z direction, the two mass blocks move synchronously, and the two mass blocks and the sensitive beam fixed by the mass blocks also keep moving synchronously, so that pure axial deformation of the sensitive beam is met.
Description
[ technical field ] A method for producing a semiconductor device
The invention belongs to the field of measurement of micro-mechanical electronic sensors, and particularly relates to an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof.
[ background of the invention ]
With the continuous development of micromachining technology, products based on MEMS technology are more and more widely used in daily life, and MEMS sensors have become the dominant force of micro sensors due to their advantages of small size, light weight, low power consumption, high reliability, and easy integration, and are gradually replacing traditional mechanical sensors, and are widely used in consumer electronics, automotive industry, and even aerospace, machinery, chemical industry, and medicine.
Compared with a strain gauge type acceleration sensor, the working principle of the MEMS piezoresistive acceleration sensor is mainly different in the principle of resistance change: the shape of the metal wire or the metal foil in the strain gauge is changed when the strain gauge is stressed, so that the resistance value is slightly changed; when a force is applied to the silicon material, the shape of the silicon material changes, and more importantly, the material characteristics change, which causes a great change in the resistance value.
The sensitivity and the working bandwidth of the MEMS acceleration sensor are the most main working indexes of the MEMS acceleration sensor, the existing acceleration sensor has high transverse sensitivity due to structural design, process machining and other reasons, interference signals from all directions exist in practical application, the high transverse sensitivity influences the measurement precision of the sensor, and the reliability of a measurement result is reduced.
[ summary of the invention ]
The invention aims to overcome the defects of the prior art and provides an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof; the invention can ensure the pure axial deformation of the sensitive beam, and simultaneously improves the sensitivity of the sensor and reduces the cross sensitivity of the sensor through the structural design.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam comprises a mass block arranged inside a chip outer frame, wherein the mass block comprises a first mass block and a second mass block which have the same structure and are symmetrical relative to a transverse central line of the chip outer frame; the outer side surface of the first mass block and the outer side surface of the second mass block are fixedly connected with the outer frame of the chip through a support beam respectively; the inner side surfaces of the first mass block and the second mass block are connected through a sensitive beam;
the sensitive beams comprise a plurality of first sensitive beams and a plurality of second sensitive beams, the first sensitive beams are arranged in the middle parts of the two mass blocks, and the second sensitive beams are separately arranged on the side edge parts of the two mass blocks; the piezoresistors on the sensitive beam are connected through a metal lead to form a Wheatstone full-bridge circuit.
Preferably, the support beam is disposed at a center line of the first mass or the second mass in the z direction, and a plane of the support beam is parallel to a plane of the outer frame of the chip.
Preferably, each support beam is fixedly provided with a snake-shaped beam, each snake-shaped beam comprises a plurality of snake-shaped units, one end of each snake-shaped unit is connected with the outer frame of the chip, and the other end of each snake-shaped unit is fixedly connected with the outer side face of the first mass block or the outer side face of the second mass block; the snake-shaped unit is of a plane circuitous structure.
Preferably, the snake-shaped beam comprises two snake-shaped units, and the two snake-shaped units are symmetrically arranged relative to a vertical central line of the outer frame of the chip.
Preferably, the snake-shaped unit comprises a first plane and a second plane which are perpendicular to each other, the first plane is parallel to the short side of the chip outer frame, and the second plane is parallel to the long side of the chip outer frame; two ends of each first plane are respectively connected with a second plane.
Preferably, the inner side surfaces of the first mass block and the second mass block are respectively provided with a protrusion and a groove, and the protrusion and the groove on each mass block are arranged adjacently; the bulge of the first mass block is placed in the groove of the second mass block, and the bulge of the second mass block is placed in the groove of the first mass block; the bulges of the first mass block and the bulges of the second mass block are connected through four first sensitive beams.
Preferably, two second sensitive beams are arranged on the outer side of the bulge of the first mass block, and two second sensitive beams are arranged on the outer side of the bulge of the second mass block; the second sensitive beams on two sides are symmetrical relative to the vertical central line of the outer frame of the chip.
Preferably, the four first sensitive beams are symmetrical relative to the vertical central line of the chip outer frame.
Preferably, the out-of-plane piezoresistive accelerometer chip is made of an SOI (silicon on insulator) silicon chip.
A preparation method of the out-of-plane piezoresistive accelerometer chip with the pure axial deformation sensitive beam comprises the following steps:
1) Carrying out double-sided thermal oxidation on the SOI silicon wafer, and respectively forming a thermal oxidation silicon dioxide layer on the upper surface and the lower surface of the SOI silicon wafer, wherein the thermal oxidation silicon dioxide layer is the upper surface thermal oxidation silicon dioxide layer and the thermal oxidation silicon dioxide layer is the lower surface thermal oxidation silicon dioxide layer;
2) Removing the upper surface thermal oxidation silicon dioxide layer in the lightly doped region on the upper surface of the SOI by using a lightly doped plate through photoetching and reactive ion etching methods, and doping boron ions in the lightly doped region to form a lightly doped region;
3) Removing the upper surface thermal oxidation silicon dioxide layer in the heavily doped region by using a heavily doped plate through photoetching and reactive ion etching methods, and heavily doping in the heavily doped region to form an ohmic contact region;
4) Depositing a Ti/Al layer on the front surface of the SOI silicon wafer by a physical vapor deposition method, and photoetching through a metal bonding pad and a wire plate to form a metal lead and a bonding pad structure;
5) Depositing a silicon dioxide layer on the back surface of the lower surface thermal oxidation silicon dioxide layer by a vapor deposition method, wherein the lower surface thermal oxidation silicon dioxide layer and the silicon dioxide layer form a double mask layer;
6) Removing the double mask layers in the back deep etching area of the SOI silicon wafer by a reactive ion etching method to expose the substrate silicon in the deep etching area of the SOI silicon wafer; etching the substrate silicon by a deep reactive ion etching method to etch off a part of the lower part of the mass block;
7) Removing the double mask layers in the back etching areas of the supporting beam and the serpentine beam through photoetching; continuously etching by a deep reactive ion etching method to form a substrate layer structure of the mass block and the lower part of the serpentine beam;
8) Carrying out photoresist masking on the bottom glass plate through the movement gap layout, and carrying out wet etching through KOH to form an empty groove region on the bottom glass plate;
9) Etching the residual double mask layers on the lower surface of the SOI silicon wafer by an ion etching method to expose substrate silicon of the SOI silicon wafer; encapsulating the substrate silicon region on a bottom glass plate through anodic bonding;
10 Etching and removing a thermal oxidation silicon dioxide layer on the upper surface of the SOI silicon chip by a reactive ion etching method, coating a layer of photoresist, and then etching until the oxygen buried layer stops by an inductive coupling plasma etching method to form the upper part of the mass block; forming device layer portions of the support beam and the serpentine beam;
11 Removing the buried oxide layer at the upper area of the supporting beam by a reactive ion etching method, and then etching the buried oxide layer at the upper area of the serpentine beam by a reactive deep ion etching method, wherein the etching of the upper parts of the supporting beam and the serpentine beam is completed;
12 Spraying photoresist on the front side of the etched SOI silicon wafer for protection, removing the photoresist in a corresponding oxygen-buried layer area, etching the residual oxygen-buried layer on the front side of the SOI silicon wafer by using buffer solution, cleaning the front side of the SOI silicon wafer, naturally drying, and finally removing the photoresist on the front side of the SOI silicon wafer;
13 The SOI silicon chip is processed by adopting a low-temperature annealing process, and the MEMS triaxial piezoresistive accelerometer chip with pure axial deformation is manufactured.
Compared with the prior art, the invention has the following beneficial effects:
the invention discloses an out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beams, which comprises two symmetrically arranged mass blocks, wherein the outer end surfaces of the two mass blocks are respectively connected with an outer frame of the chip, and the inner end surfaces of the two mass blocks are connected through two groups of sensitive beams; piezoresistors on all the sensitive beams are connected through metal leads to form a Wheatstone full-bridge circuit; the sensitive beams are divided into two types, the first type is arranged in the middle position, the second type is arranged at the side position, and the left and right mass blocks can synchronously move under the action of an out-of-plane acceleration signal, so that the two types of sensitive beams have the same movement at any moment; because the acceleration acts on the middle position of the chip, the first sensitive beam at the middle position is subjected to the acceleration to generate tensile deformation, the second sensitive beam at the edge part is extruded to be extruded inwards, the deformation modes of the two groups of sensitive beams are opposite, the two groups of sensitive beams have the functions of stretching the sensitive beams and compressing the sensitive beams on the same structure, piezoresistors on the sensitive beams can form a Wheatstone full bridge, sensed acceleration signals are converted into corresponding electric signals to be output, and the sensitivity of the sensor is improved.
Furthermore, the two support beams are arranged at the position of the center line of the mass block in the z direction, so that the effect of connecting the mass block and the outer frame of the chip is achieved, and the connecting force between the mass block and the outer frame of the chip is uniform when the mass block is subjected to acceleration.
Furthermore, a circuitous snake-shaped beam structure is arranged on the supporting beam, a metal wire can be led out without increasing the rigidity of the supporting beam, the snake-shaped beam is in a circuitous structure, when the chip is deformed by acceleration perpendicular to the outer frame of the chip, the limitation force of the outer frame of the chip to the outer side of the mass block is reduced due to the circuitous structure, and meanwhile, the snake-shaped beam is arranged on the supporting beam, so that the mass block and the outer frame of the chip can be firmly connected, the sensitivity of the acceleration sensor is improved, the cross sensitivity of the sensor is reduced, and the connecting force of the mass block and the outer frame of the chip is ensured; the snake-shaped beam is provided with a plurality of snake-shaped units, so that the metal leads can be uniformly distributed and led out.
Furthermore, the two snake-shaped units are symmetrically arranged, so that the mass blocks and the sensitive beams on two sides of the vertical central line in the whole chip are uniformly stressed, the motion of the mass blocks is synchronous, and the design performance requirement of the sensor is met.
Furthermore, the inner side surfaces of the two mass blocks are connected to form a protrusion and groove matching structure, the two protrusions are connected through the two first sensitive beams, the outer end parts of the inner side surfaces of the two mass blocks are connected through the two second sensitive beams, the first sensitive beams are matched with the second sensitive beams, piezoresistors on all the sensitive beams are connected through metal leads to form a Wheatstone full-bridge circuit, the protrusion and groove matching structure and the sensitive beam positions are designed (one group is in the middle and the other group is on the outer side), so that when the chip is accelerated perpendicular to the outer frame of the chip, the deformation of the two sensitive beams is opposite to each other to be possible.
Furthermore, four sensitive beams are arranged for each type and are symmetrical relative to the vertical center line, the number of the sensitive beams is set according to the resistance value of the sensitive beams, and if the sensitive beams are Liang Taichang, the natural frequency of the sensitive beams is increased, but the sensitivity is reduced; but sensitivity Liang Re is too short, the natural frequency is reduced; therefore, two second sensitive beams are respectively arranged on one side, so that the sensitivity of the two second sensitive beams is improved while the inherent frequency is ensured to be unchanged; the design of dividing the sensitive beam into two parts or even more parts not only improves the sensitivity, but also ensures the natural frequency.
Furthermore, the acceleration sensor chip is made of an SOI (silicon on insulator) silicon chip, so that the size of each structure can be accurately and effectively controlled, and the sensor chip is ensured to have the advantages of low noise, high precision and the like.
The invention also discloses a preparation method of the out-of-plane piezoresistive accelerometer chip with the pure axial deformation sensitive beam, aiming at the special structure of the chip, the preparation method adopts methods such as a reactive ion etching method, a plasma enhanced chemical vapor deposition method, a deep reactive ion etching method and the like to prepare the chip in multiple steps; because the Z unit supporting beam is positioned in the middle of the thickness direction (direction) of the chip, the invention has great challenge to the processing of the MEMS process, the invention adopts double mask layers on the back surface, and carries out deep reactive ion etching in two steps to etch grooves with different depths on the back surface, so that the lower half structure of the Z supporting beam and the lower half structures of the mass block, the supporting beam and the hinge beam are simultaneously formed, and simultaneously, the device layer is etched on the front surface firstly, then the oxygen buried layer is etched, and finally the substrate layer on the upper part of the supporting beam in the Z direction is etched, thereby forming the integral structure of the supporting beam.
[ description of the drawings ]
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is an enlarged detail view of the area A of the present invention;
FIG. 3 is an enlarged detail view of the area B of the present invention;
FIG. 4 is a schematic diagram of the operation of the present invention;
FIG. 5 is a partial force diagram of the present invention;
FIG. 6 is a Wheatstone full bridge circuit diagram formed in accordance with the present invention;
FIG. 7 is a schematic diagram of the preparation process of the present invention;
wherein (a) is shown as step 1); (b) the figure is step 2); (c) the figure is step 3); FIG. 4 (d) shows a step; FIG. 5 (e) shows a step; (f) FIG. 6); (g) the figure is step 7); (h) FIG. 8); (i) FIG. 9); (j) FIG. 10); FIG. (k) is step 11); (l) FIG. 12);
FIG. 8 is a flow chart of a manufacturing process of the present invention;
wherein: 1-chip outer frame; 2-a support beam; 3-a mass block; 4-a sensitive beam; 5-a serpentine beam; 7-a thermal oxide silicon dioxide layer; 8-buried oxide layer; 9-a device layer; 10-substrate silicon; 11-a lightly doped region; 12-photoresist; a 13-ohmic contact region; 14-a metal lead; 15-pad structure; 16-a silicon dioxide layer; 17-bottom glass sheet; 18-Cr/Au layer; 19-a void region; 1-1-long side; 1-2-short side; 3-1-a first mass; 3-2-a second mass; 3-3-convex; 3-4-grooves; 4-1-a first sensitive beam; 4-2-second sensitive beam; 5-1-serpentine unit; 5-2-a first plane; 5-3-second plane; 3-3-1-first side; 3-3-2-second side; 3-3-3-third side; 3-3-4-common side; 3-4-1-a first sidewall; 3-4-2-second sidewall; 3-4-3-third sidewall; 7-1-upper surface thermal oxidation silicon dioxide layer; 7-2-lower surface thermal oxidation silica layer.
[ detailed description ] embodiments
The invention is described in further detail below with reference to the figures and the specific steps.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and encompass, for example, both fixed and removable connections; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The invention discloses an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam and a preparation method thereof; the chip of the sensor is made of an SOI (Silicon on Insulator) Silicon wafer.
Referring to fig. 1, the chip comprises two supporting beams 2, two mass blocks 3, a sensitive beam 4, two serpentine beams 5 and a chip outer frame 1; the chip outer frame 1 is a rectangular frame-shaped structure and comprises two long sides 1-1 and two short sides 1-2, two ends of each long side 1-1 are respectively connected with one short side 1-2 to finally form a rectangular frame-shaped structure, and the chip outer frame 1 is fixed on the bottom glass plate through a bonding process; in the coordinate system, the O is set as the origin, the long side direction of the chip frame 1 is the X direction, the short side direction of the chip frame 1 is the Y direction, and the whole chip is on the XY plane, and the Z direction is perpendicular to the XY plane.
Referring to fig. 2, the mass block 3 includes a first mass block 3-1 and a second mass block 3-2; the first mass block 3-1 and the second mass block 3-2 are symmetrical relative to the transverse center line of the chip and have the same structure; the outer side face of the first mass block 3-1 and the outer side face of the second mass block 3-2 are fixedly connected with the chip outer frame 1 through a support beam 2 respectively, one end of the support beam 2 is fixedly connected with the chip outer frame 1, the other end of the support beam is fixedly connected with the outer end part of the first mass block 3-1 or the second mass block 3-2, the support beam 2 is of a plane structure, the plane of the support beam is parallel to the XY plane, and the support beam 2 is arranged at the Z-direction central line of the first mass block 3-1 or the second mass block 3-2; each supporting beam 2 is fixedly provided with a snake-shaped beam 5, and the plane of the snake-shaped beam 5 is vertical to the plane of the supporting beam 2; one end of the snake-shaped beam 5 is connected with the outer side edge of the first mass block 3-1 or the second mass block 3-2, and the other end is connected with the outer frame 1 of the chip; the plane of the snake-shaped beam 5 is arranged between the first mass block 3-1 and the outer frame 1 of the chip in a winding way or between the second mass block 3-2 and the outer frame 1 of the chip in a winding way, the snake-shaped beam 5 comprises a plurality of snake-shaped units 5-1, the snake-shaped units 5-1 are arranged between the mass blocks and the outer frame 1 of the chip in an array way, each snake-shaped unit 5-1 comprises a first plane 5-2 and a second plane 5-3 which are perpendicular to each other, the first plane 5-2 is parallel to the short side 1-2, the second plane 5-3 is parallel to the long side 1-1, and two ends of each first plane 5-2 are respectively connected with one second plane 5-3; the snake-shaped beam 5 is used for leading out a lead, the rigidity of the supporting beam is not increased, the sensitivity of the acceleration sensor can be improved, and the cross sensitivity of the sensor can be reduced.
Referring to fig. 3, the first mass block 3-1 or the second mass block 3-2 has the same structure, the inner side edge of each mass block is provided with a protrusion 3-3 and a groove 3-4 which are adjacent to each other, the protrusion 3-3 is of a rectangular structure and comprises a first side surface 3-3-1, a second side surface 3-3-2, a third side surface 3-3-3 and a common side surface 3-3-4 which are sequentially connected; the groove 3-4 is of a rectangular structure, the shape of the groove is the same as that of the protrusion 3-3, but the length of each side edge is larger than that of the corresponding side edge of the protrusion 3-3, so that the protrusion 3-3 of the opposite mass block can be prevented from being in the groove and a certain gap is reserved; the side walls of the grooves 3-4 comprise a common side wall 3-3-4, a first side wall 3-4-1, a second side wall 3-4-2 and a third side wall 3-4-3 which are sequentially connected, and the common side wall 3-3-4 is a side wall shared by the protrusions 3-3 and the grooves 3-4; one end of the first side surface 3-3-1 is fixedly connected with the inner side surface of the mass block (the first mass block 3-1 or the second mass block 3-2), the other end of the first side surface 3-3-1 is fixedly connected with the second side surface 3-3-2, the other end of the second side surface 3-3-2 is fixedly connected with one end of the third side surface 3-3-3, and the other end of the third side surface 3-3-3 is fixedly connected with the common side surface 3-3-4, wherein the first side surface 3-3-1 and the third side surface 3-3-3 are both vertical to the inner side surface of the mass block (the first mass block 3-1 or the second mass block 3-2), and the second side surface 3-3-2 and the common side surface 3-3-4 are both parallel to the inner side surface of the mass block (the first mass block 3-1 or the second mass block 3-2); one end of the common side face 3-3-4 is fixedly connected with the third side face 3-3-3, the other end of the common side face is fixedly connected with the first side wall 3-4-1, the other end of the first side wall 3-4-1 is fixedly connected with the second side wall 3-4-2, the other end of the second side wall 3-4-2 is fixedly connected with the third side wall 3-4-3, and the other end of the third side wall 3-4-3 is fixedly connected with the inner side face of the mass block (the first mass block 3-1 or the second mass block 3-2); the first side wall 3-4-1 and the third side wall 3-4-3 are both perpendicular to the inner side of the mass (first mass 3-1 or second mass 3-2), and the inner side of the second side wall 3-4-2 is parallel to the inner side of the mass (first mass 3-1 or second mass 3-2).
Referring to fig. 4 and 5, the first mass block 3-1 and the second mass block are symmetrically arranged in the outer frame 1 of the chip, the protrusion 3-3 of the first mass block 3-1 is placed in the groove 3-4 of the second mass block 3-2, and the protrusion 3-3 of the second mass block 3-2 is placed in the groove 3-4 of the first mass block 3-1; the common side 3-3-4 of the bulge 3-3 of the first mass block 3-1 and the common side 3-3-4 of the bulge 3-3 of the second mass block 3-2 are connected through four first sensitive beams 4-1; the inner side surfaces of the mass blocks at the outer sides of the two bulges 3-3 are respectively connected through two second sensitive beams 4-2; the four first sensitive beams 4-1 are in a group and are symmetrical relative to the vertical central line of the chip outer frame 1, and the four second sensitive beams 4-2 are in a group and are symmetrical relative to the vertical central line of the chip outer frame 1; the distance between the two mass blocks is the length of the sensitive beam and is used for directly sensing an external acceleration signal; referring to fig. 6, eight sensing beams are distributed on the end portion of the inner side face of the mass block, piezoresistors on the sensing beams form a wheatstone full-bridge circuit, and when the resistance values of four piezoresistors in the eight sensing beams are reduced, the other four piezoresistors correspondingly increase, and sensed acceleration signals are converted into corresponding electric signals to be output. Due to the design of the special end structures of the two mass blocks, when the two mass blocks are subjected to Z-direction acceleration, the protrusions of the two mass blocks are downward relative to the plane at the same time, the distance between the common side surfaces 3-3-4 of the two protrusions is increased, and therefore the two first sensitive beams 4-1 are subjected to tensile force; because the middle is sunken, the distance between the outer sides of the two mass blocks is reduced, and the second sensitive beam 4-2 farther away from the middle is subjected to compressive force, so that the function of stretching the sensitive beam and compressing the sensitive beam is realized on the same chip, and the sensed acceleration signal is converted into a corresponding electric signal to be output.
The dimensions of this example are as follows:
the overall dimensions of the sensor chip are: length × width × thickness =6650 μm × 2200 μm × 510 μm;
the support beam 2 has the following dimensions: length × width × thickness =825 μm × 50 μm × 510 μm;
the dimensions of the mass 3 (first mass 3-1 or second mass 3-2) are: length × width × thickness =2730 μm × 1700 μm × 510 μm;
the working principle of the sensor chip is as follows:
according to Newton's second law F = ma, when the sensor chip is subjected to an out-of-plane acceleration a, two mass blocks 3 in the sensor rotate slightly due to inertia to cause deformation of the supporting beam 2 and further cause deformation of the sensitive beam 4, and according to the piezoresistive effect of silicon, the piezoresistor on the sensitive beam 4 changes resistance value under the action of stress, and the relationship between the resistance value change rate and the stress applied to the piezoresistor is as follows:
wherein: r is the initial resistance value of the piezoresistor;
pi is the piezoresistive coefficient of the piezoresistor;
sigma is the stress of the piezoresistor;
and deltaR is the resistance change of the piezoresistor.
Meanwhile, a Wheatstone bridge formed by four piezoresistors (namely, a sensitive beam, wherein the middle two are in one group, and the side two are in one group) loses balance due to different resistance changes, and outputs an electric signal in direct proportion to external acceleration a, so that the acceleration is sensed and measured, and the relationship between the sensitivity S of the sensor and the out-of-plane acceleration a is as follows:
wherein: u shape out Is the output voltage of the Wheatstone bridge;
e is the Young's modulus of silicon;
pi is a piezoresistive coefficient;
U apply a supply voltage for the wheatstone bridge;
epsilon is the strain of the piezoresistive micro-beam;
π 44 is the shear piezoresistive coefficient;
l is the length of the sensitive beam;
Δ l — axial deformation of the sensitive beam;
the technical indexes of the chip prepared in this example are as follows:
measuring range: 0 to 100g;
sensitivity: more than 1.5mV/g/3V;
natural frequency: > 11kHz;
working temperature: -40 ℃ to 125 ℃.
Referring to fig. 7 and 8, letters in the block diagram of fig. 8 represent the order of fig. 7, and the method for manufacturing a chip of the present invention includes the steps of:
1) Referring to a diagram (a) in fig. 7, raw materials are selected, an N-type (100) crystal face double-side polishing SOI silicon wafer is used, and the SOI silicon wafer comprises a substrate silicon 10, an oxygen buried layer 8 and a device layer 9 which are stacked in sequence from bottom to top; the material of the bottom glass plate 17 is BF33 glass; cleaning an SOI silicon wafer, carrying out double-sided thermal oxidation at 900-1200 ℃, and respectively obtaining a thermal oxidation silicon dioxide layer 7 on the upper surface and the lower surface of the silicon wafer, wherein the thermal oxidation silicon dioxide layer 7-1 on the upper surface and the thermal oxidation silicon dioxide layer 7-2 on the lower surface are used as a following lightly doped mask layer, and the ion implantation uniformity is improved.
2) Referring to a diagram (b) in fig. 7, by using a lightly doped plate, performing first photolithography to pattern the front surface of the upper surface thermal oxide silicon dioxide layer 7-1, removing the thermal oxide silicon dioxide layer 7 in the front lightly doped region 11 by using a Reactive Ion Etching (RIE) process, using the thermal oxide silicon dioxide layer 7 in the remaining region as a mask, then performing boron ion light doping, forming the lightly doped region 11 in the device layer 9, where the lightly doped region 11 is the above-mentioned sensitive resistor, and each sensitive resistor is fixedly arranged on one sensitive beam, and preparing the sensitive resistors on all the sensitive beams through this step; then, a well push diffusion annealing process of redistribution is performed to ensure that the impurity concentration in the entire SOI device layer 9 is uniformly distributed.
3) Referring to fig. 7 (c), a layer of photoresist 12 is coated on the front surface in order to protect the lightly doped region 11 from being affected in the next heavily doped step; patterning a silicon dioxide layer and removing the upper surface thermal oxidation silicon dioxide layer 7-1 and the photoresist 12 in the front heavily doped region by utilizing a heavily doped plate, a second photoetching and Reactive Ion Etching (RIE) process, taking the photoresist 12 in the rest regions as a mask, and then carrying out boron ion heavily doping to form a low-resistance ohmic contact region 13 in the device layer 9; and performing redistribution diffusion annealing, and then performing redistribution well-push diffusion annealing to uniformly distribute the impurity concentration of the sensitive resistor and the ohmic contact region 13 so as to ensure that stable contact is formed between the metal lead 16 and the piezoresistor on the sensitive beam in the next step.
4) Referring to fig. 7 (d), a Ti/Al layer is formed on the entire front surface of the SOI wafer by using a Physical Vapor Deposition (PVD) technique, and then a third photolithography is performed on the metal pad and the wire mask, and then the metal layer in the other region except the metal lead is removed by etching to form the metal lead 14 and the pad structure 15, and an alloying process is performed at a high temperature.
5) Referring to fig. 7 (e), a silicon dioxide layer 16 is formed on the back surface of the SOI silicon wafer by using a PECVD process, and the silicon dioxide layer 16 is disposed on the back surface of the lower thermal oxide silicon dioxide layer 7-2, while the lower thermal oxide silicon dioxide layer 7-2 and the silicon dioxide layer 16 are combined to serve as a dual mask layer for the subsequent back surface etching.
6) Referring to the diagram (f) in fig. 7, the back surface is etched for the first time, the etching area is etched on the back surface of the SOI silicon wafer by photoetching for the fourth time, the RIE technology is used for removing the lower surface thermal oxidation silicon dioxide layer 7-2 and the silicon dioxide layer 16 in the back surface deep etching area, and the lower surface thermal oxidation silicon dioxide layer 7-2 and the silicon dioxide layer 16 in the rest area are used as masks; in the following Etching step, in order to ensure that the formed support beam 2, the hinge beam 3 and the mass block 3 have good edge verticality and depth-to-width ratio, deep Reactive Ion Etching (DRIE) is used for Etching; by which a portion of the lower part of the first mass 3-1 and the second mass 3-2 is etched away.
7) Referring to the diagram (g) in fig. 7, the back side is etched for the second time, the etching area is etched on the back side of the SOI silicon wafer by the fifth photoetching, the lower surface thermal oxidation silicon dioxide layer 7-2 and the silicon dioxide layer 16 which are used as mask layers in the back side etching area of the support beam 2 and the serpentine beam 5 in the measurement unit are removed, and the mask layers in the other areas are used as masks; the substrate silicon 10 is etched using the DRIE process to form the lower portions of the support beams 2 and the base layer structure of the proof mass 3.
8) Referring to the diagram (h) in fig. 7, by using the movement gap layout and the sixth photolithography, a photoresist mask is performed on the bottom glass plate 17, and wet etching is performed by using KOH to form an empty slot area 19, so as to ensure that the acceleration sensor can normally move in a working state; the empty groove area 19 is used for matching a support beam, a sensitive beam and a mass block area in the acceleration chip; a Cr/Au layer 18 is sputtered on the empty trench area 19 in the bottom glass plate 17 to prevent electrostatic adsorption.
9) Referring to fig. 7 (i), the lower thermal silicon dioxide layer 7-2 and the silicon dioxide layer 16, which are used as masks on the back side of the SOI silicon wafer, are etched by RIE process to expose the substrate silicon 10 on the back side of the SOI silicon wafer; the substrate silicon 10 area in the chip is then encapsulated on the bottom glass plate 17 by anodic bonding.
10 See (j) in fig. 7, the seventh photolithography, using the front first etching plate to etch the front etching area, using a Reactive Ion Etching (RIE) process to remove the upper surface thermal oxide silicon dioxide layer 7-1 in the front etching area, then coating a layer of photoresist to protect the metal lead 14 and the pad structure 15, etching to the buried oxide layer 8 by using an Inductively Coupled Plasma (ICP) etching technique, forming the sensitive beam 4 and the upper half of all the proof masses, forming the support beam 2, and the device layer portion of the serpentine beam 5.
11 See (k) in fig. 7, the eighth lithography is performed to lithographically etch the area of the front side support beam 2 using the front side second etching plate, and the buried oxide layer 10 in the area of the support beam 2 is removed using a Reactive Ion Etching (RIE) process without removing the photoresist, which serves to protect the metal wire 14 and the pad structure 15. In the next Etching step, in order to ensure that the formed serpentine beam 7 has good edge verticality and depth-to-width ratio, deep Reactive Ion Etching (DRIE) is used for Etching to etch away the buried oxide layer 8 in the upper region of the serpentine beam 5; the upper part of the support beam 2 and the serpentine beam 5 is now etched.
12 Referring to (l) in fig. 7, the front side of the etched SOI silicon wafer is sprayed with photoresist for protection, then the tenth lithography is performed, the photoresist in the corresponding buried oxide layer 8 region is removed by using the third etching plate on the front side, then the buried oxide layer 8 is etched from the front side by using buffer HF acid, and the buried oxide layer 8 is naturally dried after being rinsed by using deionized water and acetone respectively, and finally the photoresist on the front side is removed.
13 To further relieve and relieve residual stress of the integrated sensor chip during processing (including: mechanical stress, film internal stress, thermal stress, etc.), and a low temperature annealing process is employed.
And finishing the preparation of the out-of-plane piezoresistive accelerometer chip with the pure axial deformation sensitive beam.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. An out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam is characterized by comprising a mass block (3) arranged inside a chip outer frame (1), wherein the mass block (3) comprises a first mass block (3-1) and a second mass block (3-2) which have the same structure and are symmetrical relative to a transverse central line of the chip outer frame (1); the outer side surface of the first mass block (3-1) and the outer side surface of the second mass block (3-2) are respectively fixedly connected with the outer frame (1) of the chip through a supporting beam (2); the inner side surfaces of the first mass block (3-1) and the second mass block (3-2) are connected through a sensitive beam (4);
the sensitive beams (4) comprise a plurality of first sensitive beams (4-1) and a plurality of second sensitive beams (4-2), the first sensitive beams (4-1) are arranged at the middle parts of the two mass blocks, and the second sensitive beams (4-2) are separately arranged at the side edge parts of the two mass blocks; piezoresistors on the sensitive beam (4) are connected through a metal lead to form a Wheatstone full-bridge circuit;
the inner side surfaces of the first mass block (3-1) and the second mass block (3-2) are respectively provided with a bulge (3-3) and a groove (3-4), and the bulge (3-3) and the groove (3-4) on each mass block are adjacently arranged; the bulge (3-3) of the first mass block (3-1) is placed in the groove (3-4) of the second mass block (3-2), and the bulge (3-3) of the second mass block (3-2) is placed in the groove (3-4) of the first mass block (3-1); the bulges (3-3) of the first mass block (3-1) and the bulges (3-3) of the second mass block (3-2) are connected through four first sensitive beams (4-1);
two second sensitive beams (4-2) are arranged on the outer side of the bulge (3-3) of the first mass block (3-1), and two second sensitive beams (4-2) are arranged on the outer side of the bulge (3-3) of the second mass block (3-2); the second sensitive beams (4-2) on the two sides are symmetrical relative to the vertical central line of the chip outer frame (1).
2. An out-of-plane piezoresistive accelerometer chip with purely axial deformation sensitive beams according to claim 1, characterized in that the supporting beams (2) are arranged at the Z-directional centre line of the first mass (3-1) or the second mass (3-2); one end of the supporting beam (2) is fixedly connected with the outer frame (1) of the chip, the other end of the supporting beam is fixedly connected with the outer end part of the first mass block (3-1) or the second mass block (3-2), and the supporting beam (2) is of a plane structure; the plane of the supporting beam (2) is parallel to the plane of the chip outer frame (1);
the entire chip is in the XY plane, with the Z direction perpendicular to the XY plane.
3. An out-of-plane piezoresistive accelerometer chip with pure axial deformation sensitive beams according to claim 2, wherein each supporting beam (2) is fixedly provided with a serpentine beam (5), the serpentine beam (5) comprises a plurality of serpentine units (5-1), one end of each serpentine unit (5-1) is connected with the outer frame (1) of the chip, and the other end of each serpentine unit (5-1) is fixedly connected with the outer side surface of the first mass block (3-1) or the outer side surface of the second mass block (3-2); the snake-shaped unit (5-1) is of a plane circuitous structure.
4. An out-of-plane piezoresistive accelerometer chip with purely axially deformation sensitive beams according to claim 3, characterized in that the serpentine beam (5) comprises two serpentine cells (5-1), the two serpentine cells (5-1) being arranged symmetrically with respect to the vertical centre line of the outer frame (1) of the chip.
5. An out-of-plane piezoresistive accelerometer chip with purely axially deformation sensitive beams according to claim 3, characterized in that the serpentine shaped unit (5-1) comprises a first plane (5-2) and a second plane (5-3) perpendicular to each other, the first plane (5-2) being parallel to the short side (1-2) of the outer frame (1) of the chip, the second plane (5-3) being parallel to the long side (1-1) of the outer frame (1) of the chip; two ends of each first plane (5-2) are respectively connected with a second plane (5-3).
6. An out-of-plane piezoresistive accelerometer chip with purely axial deformation sensitive beams according to claim 1, characterized in that the four first sensitive beams (4-1) are symmetrical with respect to the vertical center line of the outer frame (1) of the chip.
7. An out-of-plane piezoresistive accelerometer chip with purely axially deformable sensitive beams according to claim 1, wherein the out-of-plane piezoresistive accelerometer chip is made from a silicon-on-SOI wafer.
8. A method for preparing an out-of-plane piezoresistive accelerometer chip with a pure axial deformation sensitive beam according to claim 3, comprising the following steps:
1) Carrying out double-sided thermal oxidation on the SOI silicon wafer, and respectively forming a thermal oxidation silicon dioxide layer (7) on the upper surface and the lower surface of the SOI silicon wafer, namely an upper surface thermal oxidation silicon dioxide layer (7-1) and a lower surface thermal oxidation silicon dioxide layer (7-2);
2) Removing the upper surface thermal oxygen silicon dioxide layer (7-1) in the lightly doped region on the upper surface of the SOI silicon chip by using a lightly doped plate through photoetching and reactive ion etching methods, and doping boron ions in the lightly doped region to form a lightly doped region (11);
3) Removing the upper surface thermal oxidation silicon dioxide layer (7-1) in the heavily doped region by using a heavily doped plate through photoetching and reactive ion etching methods, and heavily doping in the heavily doped region to form an ohmic contact region (13);
4) Depositing a Ti/Al layer on the front surface of the SOI silicon wafer by a physical vapor deposition method, and photoetching through a metal bonding pad and a wire plate to form a metal lead (14) and a bonding pad structure (15);
5) Depositing a silicon dioxide layer (16) on the back surface of the lower surface thermal oxidation silicon dioxide layer (7-2) by a vapor deposition method, and forming a double mask layer on the lower surface thermal oxidation silicon dioxide layer (7-2) and the silicon dioxide layer (16);
6) Removing the double mask layers in the back deep etching area of the SOI silicon wafer by a reactive ion etching method to expose the substrate silicon (10) in the deep etching area of the SOI silicon wafer; etching the substrate silicon (10) by a deep reactive ion etching method to etch away a portion of the lower portion of the proof mass (3);
7) Removing the double mask layers in the back etching areas of the support beam (2) and the serpentine beam (5) through photoetching; continuously etching by a deep reactive ion etching method to form a substrate layer structure of the mass block (3) and the lower part of the serpentine beam (5);
8) Carrying out photoresist masking on the bottom glass plate (17) through the movement gap layout, and carrying out wet etching through KOH to form a hollow groove area (19) on the bottom glass plate (17);
9) Etching the residual double mask layers on the lower surface of the SOI silicon wafer by an ion etching method to expose the substrate silicon (10) of the SOI silicon wafer; encapsulating the substrate silicon (10) region on the bottom glass plate (17) by anodic bonding;
10 Etching and removing the thermal oxygen silicon dioxide layer (7-1) on the upper surface of the SOI silicon wafer by a reactive ion etching method, coating a layer of photoresist, and etching until the oxygen burying layer (8) stops by an inductive coupling plasma etching method to form the upper part of the mass block (3); forming a device layer portion of the support beam (2) and the serpentine beam (5);
11 Removing the buried oxide layer (8) at the upper area of the supporting beam (2) by a reactive ion etching method, and then etching the buried oxide layer (8) at the upper area of the serpentine beam (5) by a reactive deep ion etching method, wherein the etching of the upper parts of the supporting beam (2) and the serpentine beam (5) is completed;
12 Spraying photoresist on the front side of the etched SOI silicon wafer for protection, removing the photoresist in a corresponding oxygen burying layer (8) area, etching the residual oxygen burying layer (8) on the front side of the SOI silicon wafer by using buffer solution, cleaning the front side of the SOI silicon wafer, naturally drying, and finally removing the photoresist on the front side of the SOI silicon wafer;
13 The SOI silicon chip is processed by adopting a low-temperature annealing process, and the MEMS triaxial piezoresistive accelerometer chip with pure axial deformation is manufactured.
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