CN110515861A - Handle the storage device and method thereof of flash command - Google Patents
Handle the storage device and method thereof of flash command Download PDFInfo
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- CN110515861A CN110515861A CN201810488347.3A CN201810488347A CN110515861A CN 110515861 A CN110515861 A CN 110515861A CN 201810488347 A CN201810488347 A CN 201810488347A CN 110515861 A CN110515861 A CN 110515861A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/063—Address space extension for I/O modules, e.g. memory mapped I/O
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
Abstract
A kind of method that the application provides solid storage device and is written to data, wherein this method comprises the following steps: in response to having received flash command, obtaining current time to generate the timestamp for being associated with the flash command；Access cache descriptor；Obtain the time stamp data in buffer descriptor；By non-easily the making property memory of the data write-in of cache unit indicated by buffer descriptor of the timestamp of buffer descriptor earlier than the timestamp of the flash command.
Description
Technical field
This application involves storage equipment, more particularly to storage equipment utilization caching to write with a brush dipped in Chinese ink (Flush) order to handle.
Background technique
Fig. 1 illustrates the block diagram of solid storage device.Solid storage device 102 is coupled with host, for mentioning for host
For storage capacity.Host can be coupled in several ways between solid storage device 102, and coupled modes include but is not limited to
For example, by SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI
(Small Computer System Interface, small computer system interface), SAS (Serial Attached
SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics), USB
(Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect
Express, PCIe, high speed peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber it is logical
Road, cordless communication network etc. connect host and solid storage device 102.Host, which can be, to be set through the above way with storage
The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange
Machine, router, cellular phone, personal digital assistant etc..Solid storage device 102 includes interface 103, control unit 104, one
Or multiple NVM chips 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 is used to control the data transmission between interface 103, NVM chip 105 and DRAM 110, also
For storing and managing main frame logical address is to the mapping of flash memory physical address, erasure balance, bad block management etc..Control unit
104 can be realized by the various ways of software, hardware, firmware or combinations thereof, for example, control unit 104 can be FPGA
(Field-programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 also may include place
Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders.Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110.In
DRAM can store the data of the I/O command of FTL table and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chip 105, and sent out in a manner of the interface protocol to follow NVM chip 105 to NVM chip 105
It orders out, to operate NVM chip 105, and receives the command execution results exported from NVM chip 105.Known NVM chip connects
Mouth agreement includes " Toggle ", " ONFI " etc..
In existing solid storage device, come using FTL (Flash Translation Layer, flash translation layer (FTL))
Safeguard the map information from logical address to physical address.Logical address constitutes what the upper layer software (applications)s such as operating system were perceived
The memory space of solid storage device.Physical address is the address for accessing the physical memory cell of solid storage device.In
Also implement address of cache using intermediate address form in the related technology.Such as logical address is mapped as intermediate address, in turn
Intermediate address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL table.FTL table is that solid-state is deposited
Store up the important metadata in equipment.The data item of usual FTL table has recorded the ground in solid storage device as unit of data page
Location mapping relations.
It is also defined in NVMe agreement and writes with a brush dipped in Chinese ink (Flush) order.By Flush order, instruction storage equipment will be prior to
All orders data to be written (and its metadata) that Flush order receives all are saved in non-volatile memory medium.
Solid storage device improves performance using caching.For write order, caching is written into the data of write order instruction
Afterwards, i.e., the processing of instruction write order is completed.Due to the presence of caching, when handling Flush order, the data in caching are written
Non-volatile memory medium, this process occupy the too long time.It needs to reduce or avoid to undergo host because of Flush order
By in caching data be written non-volatile memory medium process caused by performance shake.
Summary of the invention
The solid storage device of the application and the solving for method for being written to data are caused because of Flush order
The performance jitter problem generated when data is written in solid storage device.
According to a first aspect of the present application, the application provides a kind of method to solid storage device write-in data, wherein
Include the following steps: to obtain current time in response to having received flash command to generate the time for being associated with the flash command
Stamp；Access cache descriptor；Obtain the time stamp data in buffer descriptor；By the timestamp of buffer descriptor earlier than the brush
Non- easily the making property memory of the data write-in of cache unit indicated by the buffer descriptor of the timestamp of write order.
A kind of method to solid storage device write-in data according to a first aspect of the present application, wherein in timestamp
Non- easily making property is all written in the data of cache unit indicated by all buffer descriptors earlier than the timestamp of the flash command
When memory, indicate that the flash command processing is completed.
A kind of method to solid storage device write-in data according to a first aspect of the present application, wherein the caching
It include the index of distributed cache unit, the timestamp for indicating the distributed cache unit write time and institute in descriptor
The address of data in the cache unit of distribution.
A kind of method to solid storage device write-in data according to a first aspect of the present application, wherein described
The address of data is the logical address or physical address of non-easily making property memory.
A kind of method to solid storage device write-in data according to a first aspect of the present application, wherein when received
When being write order, the cache unit and buffer descriptor of dynamic RAM are distributed for write order.
A kind of method to solid storage device write-in data according to a first aspect of the present application, wherein brushed receiving
After write order, setting flag is to have indicated that flash command is to be processed；After the completion of flash command processing, set mark is removed
Note.
According to a second aspect of the present application, the application also provides a kind of method to solid storage device write-in data,
In, include the following steps: that the cache unit in response to dynamic RAM is written into data, poll buffer descriptor；According to
Buffer descriptor, by non-easily the making property memory of data write-in in cache unit.
A kind of method to solid storage device write-in data according to a second aspect of the present application, wherein in response to slow
Non- easily the making property memory of data write-in in memory cell, discharges the cache unit.
According to the third aspect of the application, the application also provides a kind of method to solid storage device write-in data,
In, include the following steps: to identify whether the write order has hit cache unit in response to having received write order；If described write
Hit cache unit, judge the hit cache unit whether the influence by flash command；If what is be hit is slow
Memory cell is influenced by flash command, then write order described in temporal cache is to reprocess institute after the completion of flash command processing
State write order or the cache unit that by flash command is not influenced new for write order distribution.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein if described write
Order miss cache unit is then the cache unit of write order distribution free time, and the corresponding data of write order is stored
In cache unit.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein by writing
Whether whether the order logical address to be accessed and the logical address that is recorded of buffer descriptor unanimously identify the write order
Cache unit is hit.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein if being hit
Cache unit do not influenced by flash command, then be stored in write order is to be written in the cache unit being hit, and refer to
Show that write order processing is completed.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein do not have currently
Although having pending flash command or currently having pending flash command, the time of the pending flash command
When stamp is less than the timestamp for the cache unit being hit, judge that the cache unit being hit is not influenced by flash command.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein have currently
The timestamp of pending flash command and the pending flash command is not less than the timestamp for the cache unit being hit
When, judge that the cache unit being hit is influenced by flash command.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein delay temporarily
During depositing the write order, continues to order and handled.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein be write order
The new cache unit not influenced by flash command of distribution is any not occupied when currently without pending flash command
Although cache unit currently has pending flash command, the timestamp of the pending flash command is less than
The unappropriated cache unit of the timestamp of cache unit.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein be write order
It is also the new cache unit not influenced by flash command after the new cache unit not influenced by flash command of distribution
Distribute buffer descriptor.
According to a kind of method to solid storage device write-in data of the third aspect of the application, wherein the caching
It include the index of distributed cache unit, the timestamp for indicating the distributed cache unit write time and institute in descriptor
The address of data in the cache unit of distribution.
To the method for solid storage device write-in data according to one kind of the third aspect of the application, wherein In
After the corresponding data of said write order are stored in cache unit, instruction said write order is completed.
According to the fourth aspect of the application, the application also provides a kind of solid storage device, including dynamic RAM,
Controller and nonvolatile memory, wherein controller execute as above one of described in method.
According to the fourth aspect of the application, the application also provides a kind of program comprising program code, when being loaded into CPU simultaneously
When executing in CPU, program makes CPU execute method one of as described above.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application can also be obtained according to these attached drawings other for those of ordinary skill in the art
Attached drawing.
Fig. 1 is the structural schematic diagram of the solid storage device of the prior art；
Fig. 2 is the structural schematic diagram according to the solid storage device of the embodiment of the present application；
Fig. 3 is the buffer descriptor according to the embodiment of the present application；
Fig. 4 A-4C is the schematic diagram according to the processing Flush order of the embodiment of the present application；
Fig. 5 A-5D is the schematic diagram according to the processing Flush order of the another embodiment of the application；
Fig. 6 is the flow chart using caching process Flush order according to the embodiment of the present application；
Fig. 7 is the flow chart using caching process Flush order according to the another embodiment of the application.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, those skilled in the art's every other embodiment obtained without making creative work, all
Belong to the scope of protection of the invention.
Fig. 2 illustrates the block diagram of the solid storage device according to the embodiment of the present application.The control unit of solid storage device
Including host interface 210, CPU 220, address conversioning unit 230 and Media Interface Connector 240 for accessing NVM chip 105.Control
Component is additionally coupled to external memory (for example, DRAM) 260.
Buffer descriptor is stored in the memory of control unit.The one or more of buffer descriptor has recorded corresponding
The storage device address of the data of address of the cache unit 265 in DRAM 260 and occupancy cache unit is (for example, storage equipment
The logical address or physical address that can be accessible to hosts).
Host interface 210 is used for host exchange command and data.For example, host and storage equipment pass through NVMe/PCIe
Protocol communication, host interface 210 handle PCIe protocol data packet, extract NVMe protocol command, and return to NVMe association to host
Discuss the processing result of order.
CPU 220 is coupled to host interface 210, the I/O command of storage equipment is sent to for receiving host, and utilize one
The received I/O command to service of a or multiple cache units 265.If host uses logical address access storage equipment, CPU
220 go back access address converting unit 230 so that logical address is converted to physical address.CPU 220 is also by received I/O command (IO
Order form may change in processing treatment process, be referred to as I/O command here in order to be concise in expression) it is sent to Jie
Matter interface 240 accesses one or more NVM chip according to I/O command by Media Interface Connector 240.
Fig. 3 illustrates the buffer descriptor according to the embodiment of the present application.
Each buffer descriptor is for describing with its corresponding cache unit.Buffer descriptor has recorded corresponding slow
Index (cache unit of Fig. 3 indexes), timestamp and the logical address (LBA) of memory cell.Cache unit index instruction caching is single
Position of the member in DRAM 260.Timestamp records the cache unit assigned time, and logical address (LBA) records the caching list
The logical address that the I/O command that member is assigned to is accessed.It is to be appreciated that when host is using physical address access storage equipment,
The logical address field of cache unit descriptor is replaced by recording physical address.
Fig. 4 A-4C illustrates the schematic diagram that Flush order is handled according to the embodiment of the present application.
Fig. 4 A illustrates the I/O command received in chronological order in command queue.Most write order (IO is received early in the T1 moment
W1), write order (IO W2) next is received at the T2 moment, Flush order is then received, next at T3 moment and T4 moment
It is subsequently received write order (IO W3) and write order (IO W4).In Fig. 4 A, arrow indicates the direction of time passage.Receive Flush
At the time of order between T3 moment and T4 moment.
Before Fig. 4 B illustrates processing Flush order, the state of cache unit.It is set according to the storage of the embodiment of the present application
It is standby, after receiving Flush order, do not stop the reception and processing to other I/O commands.Thus while write order (IO W3) it
Before have received Flush order, processing is still had begun to write order (IO W3) and write order (IO W4), for write order (IO
W3 it) is assigned with cache unit (being indicated by ID3), and write order (IO W3) data to be written are already stored at caching list
In member, it is assigned with cache unit (being indicated by ID4) for write order (IO W4), but the data to be written are not yet for write order (IO W4)
It is written into cache unit.
After Fig. 4 C illustrates processing Flush order, the state of cache unit.It, will be prior in response to receiving Flush order
Receiving Flush order and received all I/O commands, (referring to Fig. 4 A, write order (IO W1) will be write with write order (IO W2's))
The data entered are written to non-volatile memory medium (for example, NVM chip 105, referring also to Fig. 2).Next it can be indicated to host
Flush order has been processed into.And whether write order (IO W3) is written into write order (IO W4) data to be written at this time
Non-volatile memory medium is not by the semantic constraint of the Flush order.
Fig. 5 A-5D illustrates the schematic diagram according to the another embodiment processing Flush order of the application.
Fig. 5 A is identical as Fig. 4 A, illustrates the I/O command received in chronological order in command queue.Most received early in the T1 moment
To write order (IO W1), write order (IO W2) next is received at the T2 moment, Flush order is then received, next in T3
Moment and T4 moment are subsequently received write order (IO W3) and write order (IO W4).In Fig. 5 A, arrow indicates the side of time passage
To.At the time of receiving Flush order between T3 moment and T4 moment.
Before Fig. 5 B illustrates processing Flush order, the state of cache unit.It is set according to the storage of the embodiment of the present application
It is standby, after receiving Flush order, do not stop the reception and processing to other I/O commands.Thus while write order (IO W3) it
Before have received Flush order, processing is still had begun to write order (IO W3) and write order (IO W4), for write order (IO
W3 it) is assigned with cache unit (being indicated by ID3), and write order (IO W3) data to be written are not yet stored in caching list
In member.And before Flush order starts to process, cache unit not yet is distributed to write order (IO W4).
Fig. 5 C illustrates certain moment in processing Flush command procedure, the state of cache unit.In response to receiving Flush
Order, will prior to receive Flush order and received all I/O commands (referring to Fig. 5 A, write order (IO W1) and write order
(IO W2)) the data to be written be written to non-volatile memory medium (for example, NVM chip 105, referring also to Fig. 2).In Fig. 5 C
At the time of displaying, write order (IO W1) data to be written have been written to non-volatile memory medium, and write order (IO W2)
The data to be written not yet are written into non-volatile memory medium.Write order (IO W3) data to be written are still still not written
Enter cache unit.And cache unit not yet still is distributed to write order (IO W4).
After Fig. 5 D illustrates processing Flush order, the state of cache unit.It is received prior to receiving Flush order
(referring to Fig. 5 A, the data of write order (IO W1) and write order (IO W2)) to be written have been written into non-all I/O commands
Volatile storage media (for example, NVM chip 105, referring also to Fig. 2).Since write order (IO W1) has been processed into, occupy
Cache unit is released, which can be assigned to other write orders.The cache unit that write order (IO W2) occupies is not yet
It is released.
Next it can indicate that Flush order has been processed into host.And write order (IO W3) and write order at this time
Whether (IO W4) data to be written are written into non-volatile memory medium not by the semantic constraint of the Flush order.As act
Example, referring to Fig. 5 D, write order (IO W3) data to be written still not yet are written into cache unit.It and is write order (IO
W4) it is assigned with cache unit (ID 4).
Fig. 6 is the flow chart using caching process Flush order according to the embodiment of the present application.
The process flow shown according to the embodiment of Fig. 6 is controlled by the CPU 220 of such as Fig. 2, and Collaborative Control component
104 other parts are completed jointly.
In response to the I/O command (610) obtained from host interface, the type of I/O command is identified, be to write life to distinguish I/O command
Enable (620) or Flush order (670).It for write order, is cached for write order distribution, for example, what distribution was still not used by
Cache unit and buffer descriptor.Recorded in buffer descriptor the cache unit of distribution address, instruction current time when
Between stab, and obtain the write order data to be written from host, the data that will be written are stored in the cache unit of distribution
(630).Although so far the corresponding data of write order are not yet written into NVM chip, it can indicate that the write order has been handled to host
At (640).
Another task run in CPU, for the data-moving of cache unit will to be written to NVM chip (650).Example
Such as, data are written into response to cache unit, that is, start the process by the data-moving of cache unit to NVM chip.As again
One example, each buffer descriptor of poll, with will alternately have been written to data cache unit data-moving to NVM core
Piece.Optionally, it is shifted to NVM chip in response to the data in cache unit, discharges the cache unit, thus the cache unit
In timestamp be updated (or remove) and the cache unit and can be assigned to other write orders.
For the I/O command obtained from host interface, for example Flush order obtains current time to generate and is associated with this
The timestamp (680) of Flush order.Time by accessing each buffer descriptor, with recognition time stamp earlier than the Flush order
Whether the data of cache unit indicated by each buffer descriptor of stamp have all been shifted to NVM chip (660).If timestamp
The data of cache unit indicated by each buffer descriptor earlier than the timestamp of the Flush order have all been shifted to NVM core
Piece then indicates that the Flush command process completes (690) to host.
If the data of cache unit indicated by each buffer descriptor of the timestamp earlier than the timestamp of the Flush order
It has not all been shifted to NVM chip, it is for the Flush order, then each earlier than the timestamp of the Flush order to timestamp
After the data of cache unit indicated by buffer descriptor have all been shifted to NVM chip (660), then should to host instruction
Flush command process completes (690).It is to be appreciated that in each caching of the waiting time stamp earlier than the timestamp of the Flush order
During the data of cache unit indicated by descriptor have all been shifted to NVM chip, process shown in fig. 6 can be continued to execute,
I/O command is obtained from host interface and is handled.
As an example, if having received Flush order, setting flag is to be processed to have indicated Flush order.And each
After I/O command is obtained from host interface, if discovery indicates the label to be processed with the presence of Flush order, accesses each caching and describe
Symbol, the data with cache unit indicated by each buffer descriptor of the recognition time stamp earlier than the timestamp of the Flush order are
It is no to be all shifted to NVM chip.If identifying, Flush order is had been processed into, also removes set label.
Referring to Fig. 6, as an example, hold the task of the data-moving that cache unit is written to NVM chip is continual
Row, and not in response to identifying caching indicated by each buffer descriptor of the timestamp earlier than the timestamp of the Flush order
The data of unit have not all been shifted to NVM chip and have been performed.But depending on to the processing of Flush order will cache
The data-moving of the cache unit for being associated with Flush order in unit is to NVM chip.Optionally, in response to Flush to be handled
Order, priority processing will be associated with the data-moving of the cache unit of Flush order to the task of NVM chip, this will be written
The data of a little cache units move NVM chip as early as possible.
Fig. 7 is the flow chart using caching process Flush order according to the another embodiment of the application.
On the basis of flow chart shown in Fig. 6, IO write order life is further processed according to the flow chart of the embodiment of Fig. 7
The situation of middle cache unit.
In response to having received write order (720), recorded by the write order logical address to be accessed and buffer descriptor
Whether logical address unanimously identifies whether write order has hit cache unit (730).
It is corresponding in the cache unit for the idle cache unit of write order distribution if write order miss cache unit
The timestamp of record instruction current time in cache entries, and the corresponding data of write order are stored in cache unit (740).With
And (770) are completed to host instruction write order processing.
If write order has hit cache unit, further identify whether the cache unit being hit is by Flush order
It influences and its data needs to be written into the cache unit (750) of NVM chip.If the cache unit being hit is not by Flush order
Influence (currently without pending Flush order, or currently has pending Flush order, but pending Flush order
Timestamp be less than be hit the timestamp of cache unit), then write order data to be written are stored in the caching being hit
Unit (760), and (770) are completed to host instruction write order processing.If the cache unit being hit is influenced by Flush order
(currently there is pending Flush order, and the timestamp of pending Flush order is not less than the time for being hit cache unit
Stamp) (750), then the temporal cache write order (780) after the completion of Flush order is processed to reprocess the write order.Facing
When cache the write order during, also obtain other I/O commands from host interface and handled, to avoid due to executing Flush order
Cause the performance shake of storage equipment.
Optionally, if the cache unit being hit is influenced by Flush order, for write order distribute new cache unit with
Buffer descriptor records the address of the cache unit of distribution in buffer descriptor, indicates the timestamp of current time, Yi Jicong
Host obtains the write order data to be written, and the data that will be written are stored in the cache unit of distribution, next to host
Indicate that write order processing is completed.
The embodiment of the present application also provides a kind of program including program code, when being loaded into host and execute on host
When, described program makes the processor of host execute one of the method provided above according to the embodiment of the present application.
It should be understood that the combination of the frame of each frame and block diagram and flow chart of block diagram and flow chart can be respectively by including
The various devices of computer program instructions are implemented.These computer program instructions can be loaded into general purpose computer, dedicated meter
To generate machine on calculation machine or other programmable datas control equipment, to control equipment in computer or other programmable datas
The instruction of upper execution creates for realizing the device for the function of specifying in one or more flow chart box.
These computer program instructions, which can also be stored in, can guide computer or other programmable datas to control equipment
Computer-readable memory in working in a specific way, so as to using being stored in computer-readable memory
Instruction to manufacture including the product for realizing the computer-readable instruction of specified function in one or more flow chart box.
Computer program instructions can also be loaded into computer or other programmable datas control equipment on so that computer or its
A series of operation operation is executed in his programmable data control equipment, to generate computer implemented process, and then is being counted
The instruction executed on calculation machine or other programmable datas control equipment provides for realizing institute in one or more flow chart box
The operation of specified function.
Thus, the frame of block diagram and flow chart is supported for executing the combination of the device of specified function, for executing specified function
The combination of the operation of energy and the combination of the program instruction means for executing specified function.It should also be understood that block diagram and flow chart
Each frame and the combination of frame of block diagram and flow chart can be by executing specified functions or operations, hardware based dedicated meters
Calculation machine system is realized, or is realized by the combination of specialized hardware and computer instruction.
Although the example of present invention reference is described, it is intended merely to the purpose explained rather than the limit to the application
System, the change to embodiment, increase and/or deletion can be made without departing from scope of the present application.
In the field benefited involved in these embodiments, from the description above with the introduction presented in associated attached drawing
Technical staff will be recognized the application recorded here it is many modification and other embodiments.It should therefore be understood that this Shen
It please be not limited to disclosed specific embodiment, it is intended to will modify and other embodiments include in the scope of the appended claims
It is interior.Although using specific term herein, them are only used on general significance and describing significance and not is
The purpose of limitation and use.
Claims (10)
1. a kind of method to solid storage device write-in data, which comprises the steps of:
In response to having received flash command, current time is obtained to generate the timestamp for being associated with the flash command；
Access cache descriptor；
Obtain the time stamp data in buffer descriptor；
By cache unit indicated by buffer descriptor of the timestamp of buffer descriptor earlier than the timestamp of the flash command
Non- easily the making property memory of data write-in.
2. as described in claim 1 to the method for solid storage device write-in data, which is characterized in that in timestamp earlier than institute
Non- easily making property memory is all written in the data for stating cache unit indicated by all buffer descriptors of the timestamp of flash command
When, indicate that the flash command processing is completed.
3. as claimed in claim 1 or 2 to the method for solid storage device write-in data, which is characterized in that the caching is retouched
The index in symbol including distributed cache unit is stated, the timestamp of distributed cache unit write time is indicated and divides
The address of data in the cache unit matched.
4. the method to solid storage device write-in data as described in one of claim 1-3, which is characterized in that when received
When being write order, the cache unit and buffer descriptor of dynamic RAM are distributed for write order.
5. the method to solid storage device write-in data as described in one of claim 1-4, which is characterized in that
After receiving flash command, setting flag is to have indicated that flash command is to be processed；
After the completion of flash command processing, set label is removed.
6. a kind of method to solid storage device write-in data, which comprises the steps of:
In response to having received write order, identify whether the write order has hit cache unit；
If the write order has hit cache unit, judge the hit cache unit whether the influence by flash command；
If the cache unit being hit is influenced by flash command, write order described in temporal cache is with to the flash command
The write order or the cache unit that by flash command is not influenced new for write order distribution are reprocessed after the completion of reason.
7. as claimed in claim 6 to the method for solid storage device write-in data, which is characterized in that if the write order is not
Cache unit is hit, then the cache unit idle for write order distribution, and the corresponding data of write order are stored in caching
In unit.
8. the method to solid storage device write-in data as claimed in claims 6 or 7, which is characterized in that if be hit
Cache unit is not influenced by flash command, then is stored in write order is to be written in the cache unit being hit, and indicate
Write order processing is completed.
9. as claimed in claim 8 to the method for solid storage device write-in data, which is characterized in that currently without wait hold
Although capable flash command currently has pending flash command, the timestamp of the pending flash command is less than
When the timestamp for the cache unit being hit, judge that the cache unit being hit is not influenced by flash command.
10. a kind of solid storage device, including dynamic RAM, controller and nonvolatile memory, wherein controller
Execute method described in one of -9 according to claim 1.
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| CN202210225337.7A CN114610654A (en) | 2018-05-21 | 2018-05-21 | Solid-state storage device and method for writing data into solid-state storage device |
| CN201810488347.3A CN110515861B (en) | 2018-05-21 | 2018-05-21 | Memory device for processing flash command and method thereof |
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| CN112988623A (en) * | 2019-12-17 | 2021-06-18 | 北京忆芯科技有限公司 | Method and storage device for accelerating SGL (secure gateway) processing |
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| CN114281245A (en) | 2021-11-26 | 2022-04-05 | 三星（中国）半导体有限公司 | Synchronous writing method and device, storage system and electronic equipment |
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| CN114610654A (en) | 2022-06-10 |
| CN110515861B (en) | 2022-08-05 |
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