CN110493604A - A method of 8K HEVC real-time coding is realized based on GPU cluster - Google Patents
A method of 8K HEVC real-time coding is realized based on GPU cluster Download PDFInfo
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Abstract
The invention discloses a kind of methods for realizing 8K HEVC real-time coding based on GPU cluster, are related to technical field of video coding, and the present invention includes according to efficient video coding standard, and by 8K image, spatially position height is divided into N number of slice sequence；Cluster is formed by N NVIDIA GPU, N number of slice sequence is respectively corresponded into N GPU of feeding and is encoded, the corresponding coded data of N number of slice sequence is obtained；It modifies adjustment to the coded data of N number of slice sequence, lose pps and slice information of sequence parameter set sps, picture parameter set of each coded data, total sequence parameter set sps and total picture parameter set pps is generated according to whole frame totality coding parameter, the coded data of N number of slice sequence adjusted is spliced in order, obtain final code stream, complete 8K HEVC real-time coding, the present invention forms cluster using more GPU, then by way of splicing code stream, standard code stream is obtained, the 8K HEVC coding of real-time high-efficiency can be reached.
Description
Technical field
The present invention relates to technical field of video coding, realize that 8K HEVC is real based on GPU cluster more particularly to one kind
When the method that encodes.
Background technique
8K video has mass data, and the video compress that must carry out high compression ratio to it during transimission and storage is compiled
Code, and the mainstream format of 8K Video coding is HEVC (H.265), the mass data of 8K makes 8K HEVC real-time coding very tired
It is difficult.The encoder situation of HEVC mainstream is as follows on the market at present:
1, CPU encoder: common CPU encoder, such as x265 realize that 4K real-time coding is all highly difficult, and 8K is in real time less
It may accomplish；
2, FPGA encoder: using NGCodec as representative, ability is limited to 4K HEVC real-time coding, and general cloth is beyond the clouds
On FPGA accelerator card, expensive；
3, ASIC encoder: using companies such as Socionext as representative, common HEVC ASIC encoder on the market at present
Ability encodes level in real time in 4K, and few top ASIC encoder is able to achieve HEVC 8K real-time coding, but price is very
It is high；
4, NVENC encoder: NVENC is also the ASIC encoder being integrated in above NVIDIA GPU in fact, but because
For NVIDIA GPU compared to other ASIC encoders for, be very easy to obtain and be easy use, so individually column at one kind
Encoder, the code capacity of NVENC are also horizontal in real time in 4K HEVC；
In conclusion the feasible program of 8K HEVC real-time coding is rare and expensive on the market at present.
Summary of the invention
It is an object of the invention to: it is not easy to obtain to solve to be directed to the progress real-time coding of 8K video at present there are hardware,
And problem at high price, the present invention provides a kind of method for realizing 8K HEVC real-time coding based on GPU cluster, based on logical
NVENC encoder is created using NVIDIA GPU in conjunction with multiple NVIDIA GPU with x86 server, multiple GPU are worked together,
It realizes 8K HEVC real-time coding, is based on general x86 framework, hardware device is easily obtained, has both solved professional coders hardware and set
It is standby to be difficult to the problem of obtaining, and overall cost is significantly reduced, break the price fixing of professional coders.
The present invention specifically uses following technical scheme to achieve the goals above:
A method of 8K HEVC real-time coding being realized based on GPU cluster, the method is based on x86 server, including such as
Lower step:
S1: according to efficient video coding standard, by 8K image, spatially position height is divided into N number of slice sequence；
S2: forming cluster by N NVIDIA GPU, and N number of slice sequence is respectively corresponded N GPU of feeding and is encoded,
Obtain the corresponding coded data of N number of slice sequence；
S3: it modifies adjustment to the coded data of N number of slice sequence obtained in S2, loses each coded data
Pps and slice sequence parameter set sps, picture parameter set information generate total sequence parameter set according to whole frame totality coding parameter
Sps and total picture parameter set pps splices the coded data of N number of slice sequence adjusted in order, obtains final
Code stream completes 8K HEVC real-time coding.
Further, the efficient video coding standard of foundation is ITU-RBT.2073 in the S1.
Further, every NVIDIA GPU uses Turing framework, and every NVIDIA GPU is respectively created
NVENC stone encoder.
Further, it in the S2, is encoded according to the NVENC stone of the size of the obtained slice sequence of S1 setting creation
Code rate parameter is arranged to each slice sequence according to overall code rate in device breadth, and N number of NVENC stone encoder encodes corresponding simultaneously
Slice sequence, obtain corresponding coded data.
Further, the S3 specifically:
S3.1: for a frame 8K data, standard parsing, note are carried out according to the sequence parameter set sps of first slice sequence
The ratio parsed before parsing pic_width_in_luma_samples and pic_height_in_luma_samples parameter
Spy's stream is N, parses residue after pic_width_in_luma_samples and pic_height_in_luma_samples parameter
Bit stream be M；
The overall wide height of the frame is successively subjected to exp-Golomb coding again, note code stream is X, and N, X and M are successively spelled
It connects, as overall sequence parameter set sps, the picture parameter set pps of first slice sequence is left, as total picture parameter set
pps；
S3.2: successively parsing the slice head information of remaining slice sequence, modifies the macro block starting of an every slice information
Location parameter first_slice_segment_in_pic_flag and slice_segment_address, wherein first_
It is current slice sequence in 8k number that slice_segment_in_pic_flag, which is set as 0, slice_segment_address,
Modified parameter set is pressed HEVC standard, re-generates new slice head information by the initial position in；
S3.3: the new slice head information of every slice sequence is closed with corresponding slice subsequent coded data
And obtain the newly encoded data of every slice sequence；
S3.4: the picture parameter set pps of overall sequence parameter set sps and first slice sequence in S3.1 are written
Then total code stream is sequentially added into the newly encoded data in the region every slice obtained in S3.3, obtain a frame 8K image most
Whole code stream；
S3.5: loop iteration S3.1 to S3.4, until entire sequential coding is completed, the HEVC code stream of entire sequence is obtained,
Complete 8K HEVC real-time coding.
Beneficial effects of the present invention are as follows:
1, by 8K image, spatially position by multiple slice sequences are highly divided into utilizes the hard of multiple video cards to the present invention
Unified coding code rate and code rate control parameter and GOP parameter is arranged to each encoder, to the slice sequence of every frame in encoder
Column are encoded to obtain the coded data of each slice sequence respectively, then will be at the coded data of each slice sequence
Reason, additional addition generates sps and pps information, to obtain the code stream for meeting HEVC standard, realizes the height for meeting HEVC standard
Efficiency encodes 8K sequence.
Detailed description of the invention
Fig. 1 is the method flow schematic diagram of the specific embodiment of the invention.
Fig. 2 is that the 8K image of the specific embodiment of the invention divides schematic diagram.
Fig. 3 is the method application schematic diagram of the specific embodiment of the invention.
Specific embodiment
In order to which those skilled in the art better understand the present invention, with reference to the accompanying drawing with following embodiment to the present invention
It is described in further detail.
Embodiment 1
As shown in figures 1 and 3, the present embodiment provides it is a kind of based on GPU cluster realize 8K HEVC real-time coding method,
The method is based on x86 server, includes the following steps:
S1: according to efficient video coding standard ITU-RBT.2073, by 8K image spatially position height be divided into it is N number of
Slice sequence, as shown in Fig. 2, the image of 8K 7680*4320 breadth is divided into 4 slice sequences by the present embodiment, respectively
7680x1088, 7680x1088,7680x1088,7680x1056；
S2: forming cluster by 4 NVIDIA GPU, and 4 slice sequences are respectively corresponded 4 GPU of feeding and are encoded,
Obtain the corresponding coded data of 4 slice sequences, wherein every NVIDIA GPU uses Turing framework, and every
NVENC stone encoder is respectively created in NVIDIA GPU, according to the NVENC of the size of the obtained slice sequence of S1 setting creation
Code rate parameter is arranged to each slice sequence according to overall code rate in stone encoder breadth, and code rate, breadth parameter are according to slice
Sequence accounts for overview image size and carries out etc. than modification, and such as overall code rate is 1, then the slice sequence that height is 1088, and code rate is
1088/4320, GOP parameter will seek unification setting according to total code stream, and 4 NVENC stone encoders encode corresponding slice simultaneously
Sequence obtains corresponding coded data；
S3: it modifies adjustment to the coded data of N number of slice sequence obtained in S2, loses each coded data
Pps and slice sequence parameter set sps, picture parameter set information generate total sequence parameter set according to whole frame totality coding parameter
Sps and total picture parameter set pps splices the coded data of N number of slice sequence adjusted in order, obtains final
Code stream completes 8K HEVC real-time coding, specifically:
S3.1: carrying out standard parsing according to the sequence parameter set sps of first slice sequence for a frame 8K data,
Having parsed before note parsing pic_width_in_luma_samples and pic_height_in_luma_samples parameter
Bit stream is N, is remained after parsing pic_width_in_luma_samples and pic_height_in_luma_samples parameter
Remaining bit stream is M；
The overall wide height of the frame is successively subjected to exp-Golomb coding again, note code stream is X, and N, X and M are successively spelled
It connects, as overall sequence parameter set sps, the picture parameter set pps of first slice sequence is left, as total picture parameter set
pps；
S3.2: successively parsing the slice head information of remaining slice sequence, modifies the macro block starting of an every slice information
Location parameter first_slice_segment_in_pic_flag and slice_segment_address, wherein first_
It is current slice sequence in 8K number that slice_segment_in_pic_flag, which is set as 0, slice_segment_address,
Modified parameter set is pressed HEVC standard, re-generates new slice head information by the initial position in；
S3.3: the new slice head information of every slice sequence is closed with corresponding slice subsequent coded data
And obtain the newly encoded data of every slice sequence；
S3.4: the picture parameter set pps of overall sequence parameter set sps and first slice sequence in S3.1 are written
Then total code stream is sequentially added into the newly encoded data in the region every slice obtained in S3.3, obtain a frame 8K image most
Whole code stream；
S3.5: loop iteration S3.1 to S3.4, until entire sequential coding is completed, the HEVC code stream of entire sequence is obtained,
Complete 8K HEVC real-time coding.
The present embodiment obtains standard code stream then by way of splicing code stream using more GPU composition cluster, reaches real
When efficient 8K HEVC coding.
The above, only presently preferred embodiments of the present invention, are not intended to limit the invention, patent protection model of the invention
It encloses and is subject to claims, it is all to change with equivalent structure made by specification and accompanying drawing content of the invention, similarly
It should be included within the scope of the present invention.
Claims (5)
1. a kind of method for realizing 8K HEVC real-time coding based on GPU cluster, which is characterized in that the method is serviced based on x86
Device includes the following steps:
S1: according to efficient video coding standard, by 8K image, spatially position height is divided into N number of slice sequence；
S2: forming cluster by N NVIDIA GPU, and N number of slice sequence is respectively corresponded N GPU of feeding and is encoded, N is obtained
The corresponding coded data of a slice sequence；
S3: it modifies adjustment to the coded data of N number of slice sequence obtained in S2, loses the sequence of each coded data
Pps and slice parameter set sps, picture parameter set information generate total sequence parameter set sps according to whole frame totality coding parameter
With total picture parameter set pps, the coded data of N number of slice sequence adjusted is spliced in order, obtains final code
Stream completes 8K HEVC real-time coding.
2. a kind of method for realizing 8K HEVC real-time coding based on GPU cluster according to claim 1, which is characterized in that
The efficient video coding standard of foundation is ITU-RBT.2073 in the S1.
3. a kind of method for realizing 8K HEVC real-time coding based on GPU cluster according to claim 1, which is characterized in that
Every NVIDIA GPU uses Turing framework, and NVENC stone encoder is respectively created in every NVIDIA GPU.
4. a kind of method for realizing 8K HEVC real-time coding based on GPU cluster according to claim 3, which is characterized in that
In the S2, according to the NVENC stone encoder breadth of the size of the obtained slice sequence of S1 setting creation, according to overall code
Code rate parameter is arranged to each slice sequence in rate, and N number of NVENC stone encoder encodes corresponding slice sequence simultaneously, obtains
Corresponding coded data.
5. a kind of method for realizing 8K HEVC real-time coding based on GPU cluster according to claim 1, which is characterized in that
The S3 specifically:
S3.1: for a frame 8K image, standard parsing, note parsing are carried out according to the sequence parameter set sps of first slice sequence
The bit stream parsed before pic_width_in_luma_samples and pic_height_in_luma_samples parameter is
N parses remaining bit stream after pic_width_in_luma_samples and pic_height_in_luma_samples parameter
For M；
The overall wide height of the frame is successively subjected to exp-Golomb coding again, note code stream is X, N, X and M successively spliced,
As overall sequence parameter set sps, the picture parameter set pps of first slice sequence is left, as total picture parameter set pps；
S3.2: successively parsing the slice head information of remaining slice sequence, modifies the macro block initial position of an every slice information
Parameter first_slice_segment_in_pic_flag and slice_segment_address, wherein first_slice_
It is current slice sequence rising in 8K image that segment_in_pic_flag, which is set as 0, slice_segment_address,
Modified parameter set is pressed HEVC standard, re-generates new slice head information by beginning position；
S3.3: the new slice head information of every slice sequence is merged with corresponding slice subsequent coded data, is obtained
To the newly encoded data of every slice sequence；
S3.4: total code is written into the picture parameter set pps of overall sequence parameter set sps and first slice sequence in S3.1
Stream, is then sequentially added into the newly encoded data in the region every slice obtained in S3.3, obtains the final code of a frame 8K image
Stream；
S3.5: for 8K video sequence, loop iteration S3.1 to S3.4 obtains entire sequence until entire sequential coding is completed
HEVC code stream, i.e., completion 8K HEVC real-time coding.
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Application publication date: 20191122 |