CN110491849A - Chip, input/output structure and bed course - Google Patents
Chip, input/output structure and bed course Download PDFInfo
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- CN110491849A CN110491849A CN201910652078.4A CN201910652078A CN110491849A CN 110491849 A CN110491849 A CN 110491849A CN 201910652078 A CN201910652078 A CN 201910652078A CN 110491849 A CN110491849 A CN 110491849A
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- 239000002184 metal Substances 0.000 claims abstract description 191
- 229910052751 metal Inorganic materials 0.000 claims abstract description 191
- 230000005669 field effect Effects 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims description 8
- 230000002180 anti-stress Effects 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 238000007363 ring formation reaction Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
The present invention relates to a kind of chip, input/output structure and bed course, the bed course includes the first metal layer, second metal layer group and the third metal layer group set gradually along the direction close to chip device；The second metal layer group includes mutually independent conducting area, input and output power supply area and input and output area, the conducting area passes through via layer respectively and connect with the first metal layer and the third metal layer group, the first metal layer is connect with packaging frame, and the third metal layer group, the input and output power supply area and the input and output area are connected to the antistatic metal-oxide-semiconductor field effect transistor in chip respectively.Input and output power supply area and input and output area are released, and are respectively formed the cabling of power supply and ground, are reduced the resistance of power supply and ground, are enhanced the access of releasing of antistatic metal-oxide-semiconductor field effect transistor, promote the anti-static ability of input/output structure；Bedding design has been simplified, the area of input/output structure is reduced, has greatly improved the encapsulation convenience of chip.
Description
Technical field
The present invention relates to technical field of semiconductor device more particularly to a kind of chips, input/output structure and bed course.
Background technique
In integrated circuits, the size of bare die (die) determines the cost of chip, and the ruler of input/output structure (IO)
It is very little, especially in the case where IO limits cake core (PAD limit), it will have a direct impact on the size of bare die (die), input and output
Structure (IO) needs while meeting the design objective of the performances such as sequential logic, antistatic (ESD), as far as possible reduction face
Product increases design margin for the layout of top layer and the selection of pad put, encapsulated.Chip device is placed in the shape below pad
Pad (pad), is overlayed antistatic (ESD) device of input/output structure (IO) by CUP (circuit under pad) IO of formula
On part, compared to common, save pad (PAD) and puts the area additionally occupied, reduce the area of input/output structure (IO),
Using extensive.The CUP scheme for the form that current chip is set to below pad mostly uses multiple layer metal bed course (>=2), great Liang Jin
Belong to resource and be only used for stress support, antistatic (ESD) leakage path metal resource is limited, and antistatic (ESD) lacks in ability.
Accordingly, it is desirable to provide a kind of chip, input/output structure and bed course solve the deficiencies in the prior art.
Summary of the invention
In order to solve the problems in the prior art, the present invention provides a kind of chip, input/output structure and bed courses.
A kind of bed course of chip input/output structure, including the first metal set gradually along the direction close to chip device
Layer, second metal layer group and third metal layer group；
The second metal layer group includes mutually independent conducting area, input and output power supply area and input and output area, institute
Conducting area is stated to pass through via layer respectively and connect with the first metal layer and the third metal layer group, the first metal layer and
Packaging frame connection, the third metal layer group, the input and output power supply area and the input and output area respectively with chip
Interior antistatic metal-oxide-semiconductor field effect transistor connection.
Further, the second metal layer group includes at least two layers for passing sequentially through via layer connection by its thickness direction
Metal layer, the via layer and at least two layers metal layer include mutually independent conducting area, input and output power supply area and
Input and output area, the conducting area of the via layer and the conducting district's groups of at least two layers metal layer are at the second metal layer
The input and output power supply area composition of the conducting area of group, the input and output power supply area of the via layer and at least two layers metal layer
The input and output power supply area of the second metal layer group, the input and output area of the via layer and at least two layers metal layer
Input and output area form the second metal layer group input and output area.
Further, the third metal layer component not with the end D of N-type antistatic metal-oxide-semiconductor field effect transistor and p-type antistatic
The end D of metal-oxide-semiconductor field effect transistor connects.
Further, the input and output power supply area is connect with the end S of p-type antistatic metal-oxide-semiconductor field effect transistor.
Further, the input and output area is connect with the end S of N-type antistatic metal-oxide-semiconductor field effect transistor.
Further, the second metal layer group further includes and the conducting area, the input and output power supply area and described
The mutually independent logic power area in input and output area and logic area, the logic power area and the logic area are also mutual
It is independent；
The logic power area and the logically area are connect with the logic area in chip respectively.
Further, the via layer and at least two layers metal layer include respectively with the conducting area, described defeated
Enter the mutually independent logic power area in out-put supply area and input and output area and logic area, the logic of the via layer
The logic power district's groups of power supply area and at least two layers metal layer at the second metal layer group logic power area, it is described logical
The logic regional group of the logic area of aperture layer and at least two layers metal layer is regional at the logic of the second metal layer group.
Further, the third metal layer group including one layer of metal layer or passes sequentially through via layer company by its thickness direction
At least two metal layers connect.
Further, the thickness of the first metal layer be respectively greater than the metal layer of the second metal layer group thickness and
The thickness of the metal layer of the third metal layer group.
Further, the side far from the second metal layer group of the first metal layer is additionally provided with passivation layer.
Further, the passivation layer is equipped with wiring window, exposes the first metal layer at the wiring window, cruelly
The first metal layer exposed is connect by bonding wire with packaging frame.
Further, the first metal layer is equipped at least one anti-stress hole.
Further, the first metal layer, the second metal layer group, the third metal layer group and via layer are embedding
In dielectric layer；The via layer includes the alloy column that at least one is embedded in the dielectric layer.
The second metal layer group includes a conducting area or multiple mutually independent conducting areas.
It is defeated including the chip the present invention also provides a kind of chip input/output structure based on same invention thinking
Enter the bed course of export structure.
Based on same invention thinking, the present invention provides a kind of chips, including the chip input/output structure.
Technical solution of the present invention has the advantages that compared with the immediate prior art
The bed course for the chip input/output structure that technical solution provided by the invention provides, by by second metal layer component
Be segmented into independent conducting area, input and output power supply area and input and output area, and only conducting area be used for combine the first metal layer and
Third metal layer group be connected to chip in antistatic metal-oxide-semiconductor field effect transistor and packaging frame, and respectively with conducting the independent input in area
Out-put supply area and input and output area are released, and are respectively formed the cabling of power supply and ground, effectively reduce power supply and ground
Resistance enhances the access of releasing of antistatic metal-oxide-semiconductor field effect transistor, and then improves the anti-static ability of input/output structure；And
And for the first metal layer window area that is directly connect with packaging frame as pad, then other of chip device and bed course layer
Lower section in pad is in layered distribution with pad, has simplified the design of bed course, reduced the area of input/output structure, pole
The earth improves the encapsulation convenience of chip.
Detailed description of the invention
Fig. 1 is the top view of the bed course of the chip input/output structure of the first form provided by the invention；
Fig. 2 is the cross-sectional view of the position in Fig. 1 where AB line；
Fig. 3 is the conspectus of the bed course of the chip input/output structure of the first form provided by the invention；
Fig. 4 is the top view of the bed course of the chip input/output structure of second of form provided by the invention.
Wherein, 1- the first metal layer；2- second metal layer group；3- third metal layer group；4- via layer；Area is connected in 5-；6-
Input and output area；7- input and output power supply area；8- logic area；9- logic power area；10- alloy column；11- metal layer；12-
Passivation layer；13- wiring window；The anti-stress hole 14-；15- bonding wire；16-N type antistatic metal-oxide-semiconductor field effect transistor；17-P type antistatic
Metal-oxide-semiconductor field effect transistor；18- logic area.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
The embodiment of the application a part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's every other embodiment obtained without making creative work, all should belong to the model of the application protection
It encloses.
It should be noted that the description and claims of this application and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to embodiments herein described herein.In addition, term " includes " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing a series of steps or units
Process, method, system, product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include without clear
Other step or units listing to Chu or intrinsic for these process, methods, product or equipment.
In this application, term " on ", "lower", "inner", " in ", "outside", the orientation of the instructions such as "front", "rear" or position close
System is to be based on the orientation or positional relationship shown in the drawings.These terms are primarily to better describe the application and its implementation
Example, is not intended to limit indicated device, element or component must have particular orientation, or carries out structure with particular orientation
It makes and operates.
Also, above-mentioned part term is other than it can be used to indicate that orientation or positional relationship, it is also possible to for indicating it
His meaning, such as term " on " also are likely used for indicating certain relations of dependence or connection relationship in some cases.For ability
For the those of ordinary skill of domain, the concrete meaning of these terms in this application can be understood as the case may be.
In addition, term " setting ", " connection ", " fixation " shall be understood in a broad sense.For example, " connection " may be a fixed connection,
It is detachably connected or monolithic construction；It can be mechanical connection, or electrical connection；It can be directly connected, or pass through centre
Medium is indirectly connected, or is two connections internal between device, element or component.For ordinary skill
For personnel, the concrete meaning of above-mentioned term in this application can be understood as the case may be.
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.1-4 and it is described in detail the application in conjunction with the embodiments below with reference to the accompanying drawings.Fig. 1 is that chip provided by the invention is defeated
Enter the top view of the bed course of export structure；Fig. 2 is the cross-sectional view in Fig. 1 where AB line；Fig. 3 is chip input provided by the invention
The conspectus of the bed course of export structure；And Fig. 4 is the chip input/output structure of second of form provided by the invention
Bed course top view.
The present invention provides a kind of bed courses of chip input/output structure, including successively setting along the direction close to chip device
The first metal layer (Top Metal) 1, second metal layer group 2 and the third metal layer group 3 set；The second metal layer group 2 includes
Mutually independent conducting area 5, input and output power supply area 7 and input and output area 6, the conducting area 5 respectively by via layer 4 with
The first metal layer 1 and the third metal layer group 3 connection, the first metal layer 1 are connect with packaging frame, the third
Metal layer group 3, the input and output power supply area 7 and the input and output area 6 respectively with the antistatic MOS field-effect in chip
Pipe connection.
By the way that the segmentation of second metal layer group 2 is independent conducting area 5, input and output power supply area 7 and input and output area
6, and only conducting area 5 is used to that the first metal layer 1 to be combined to be connected to the antistatic metal-oxide-semiconductor field effect transistor in chip with third metal layer group 3
And packaging frame, packaging frame can reserve exposed part in subsequent encapsulation process, then exposed part passes through bent
At the pin of chip, pin is connected to internal the first metal layer 1 is encapsulated in；And respectively with conducting the independent input in area 5
Out-put supply area 7 and input and output area 6 are released, and are respectively formed the cabling of power supply and ground, are effectively reduced power supply and ground
Resistance, enhance the access of releasing of antistatic metal-oxide-semiconductor field effect transistor, and then improve the anti-static ability of input/output structure；
And for 1 window area of the first metal layer that is directly connect with packaging frame as pad, then its of chip device and bed course
His layer is in the lower section of pad, is in layered distribution with pad, has simplified the design of bed course, reduced the face of input/output structure
Product, greatly improves the encapsulation convenience of chip.
In some embodiments of the invention, the second metal layer group 2 includes passing sequentially through through-hole by its thickness direction
At least two metal layers 11 of 4 connection of layer, the via layer 4 and at least two layers metal layer 11 include mutually independent lead
Logical area 5, input and output power supply area 7 and input and output area 6, the conducting area 5 of the via layer 4 and at least two layers metal layer
11 conducting area 5 forms the conducting area 5 of the second metal layer group 2, the input and output power supply area 7 of the via layer 4 and at least
The input and output power supply area 7 of two layers of metal layer 11 forms the input and output power supply area 7 of the second metal layer group 2, described
The input and output area 6 of via layer 4 and the 6 composition second metal layer of input and output area of at least two layers metal layer 11
The input and output area 6 of group 2.
Bed course is multilayered structure, and is 4 alternating structure of metal layer 11 and via layer, is also according to one layer of sequence when preparing
What one layer of preparation was completed, therefore second metal layer group 2 is metal layer 11 and 4 alternating structure of via layer, and entire second metal
Floor group 2 by dielectric layer is divided into multiple independent areas again, including conducting area 5, input and output power supply area 7 and input and output
Area 6, and each layer structure in front, are each split into corresponding conducting area 5, input and output power supply area 7 and input and output
The three parts in area 6, and the conducting area 5 of each floor structure constitutes complete conducting area 5,7 structure of input and output power supply area of each layer structure
At complete input and output power supply area 7, the input and output area 6 of each layer structure constitutes complete input and output area 6.
In some embodiments of the invention, the third metal layer group 3 respectively with N-type antistatic metal-oxide-semiconductor field effect transistor 16
The end D connected with the end D of p-type antistatic metal-oxide-semiconductor field effect transistor 17.The end D of N-type antistatic metal-oxide-semiconductor field effect transistor 16 and p-type antistatic
The pad that the end D of metal-oxide-semiconductor field effect transistor 17 passes through the conducting area 5 and the first metal layer 1 of third metal layer group 3, second metal layer group 2
Region connection, electrostatic (ESD) voltage for enabling pad (PAD) to introduce rapidly arrives at antistatic metal-oxide-semiconductor field effect transistor, and this is quiet
Electric release channel avoids electrostatic (ESD) voltage from scurrying into other circuits of input/output structure, avoids the damage of other function device
It is bad.
In some embodiments of the invention, the S of the input and output power supply area 7 and p-type antistatic metal-oxide-semiconductor field effect transistor 17
End connection.Input and output power supply area 7 is the metal resource released from second metal layer group 2, power-supply wiring is used for, when multiple
Input/output structure be successively stitched together cyclization when, the power supply loop of chip level can be formed, such power-supply wiring is logical
Road can greatly reduce the resistance that input/output structure (IO) arrives power supply, to promote antistatic (ESD) ability of chip level.
In some embodiments of the invention, the end S in the input and output area 6 and N-type antistatic metal-oxide-semiconductor field effect transistor 16
Connection.Input and output area 6 is the metal resource released from second metal layer group 2, for the wiring on ground, when multiple inputs
Export structure be once stitched together cyclization when, the loop on the ground of chip level can be formed, the wiring channel on such ground can
Greatly to reduce the resistance that input/output structure (IO) arrives ground, to promote antistatic (ESD) ability of chip level.
In some embodiments of the invention, the second metal layer group 2 further includes and the conducting area 5, the input
Out-put supply area 7 and the regional 6 mutually independent logic power areas 9 of the input and output and logic area 8, the logic power area
9 and the logic area 8 it is also mutually indepedent；The logic power area 9 and the logic area 8 respectively with the logic area in chip
18 connections.
Only conducting area 5 is for connecting the first metal layer 1 and third metal layer group 3 in second metal layer group 2, and then is used for
Packaging frame and antistatic metal-oxide-semiconductor field effect transistor are connected, therefore it is otherwise utilized to release a large amount of metal resource, is discharging
Metal resource out is individually formed except input and output power supply area 7 and input and output area 6, can also form another group of electricity
Source, area, this group of power supply, area correspond to the logic area 18 in chip, therefore are logic power area 9 and logic area 8, and divide
It is not connect with logic area 18.
In some embodiments of the invention, the via layer 4 and at least two layers metal layer include respectively with institute
State conducting area 5, regional 6 mutually independent logic power areas 9 of the input and output power supply area 7 and the input and output and logically
The logic power area 9 of area 8, the logic power area 9 of the via layer 4 and at least two layers metal layer forms second metal
The logic power area 9 of floor group 2, the logic area 8 of the via layer 4 and the logic area 8 of at least two layers metal layer form
The logic area 8 of the second metal layer group 2.Bed course is multilayered structure, and is 4 alternating structure of metal layer 11 and via layer,
It is also to be completed according to the preparation of sequence in layer, therefore second metal layer group 2 is that metal layer 11 and via layer 4 are handed over when preparation
For structure, and entire second metal layer group 2 is divided into multiple independent areas by dielectric layer, except including conducting area 5, input and output
It further include independent logic power area 9 and logic area 8, mentioned-above each layer except power supply area 7 and input and output area 6
Structure corresponds to conducting area 5 except being divided into, and outside the three parts in input and output power supply area 7 and input and output area 6, there are also logics
Power supply area 9 and logic area 8, and the logic power area 9 of each floor structure constitutes complete logic power area 9, each layer structure it is defeated
Enter logic area 8 and constitutes complete input logic area 8.
In some embodiments of the invention, the third metal layer group 3 includes one layer of metal layer 11 by its thickness direction
Or pass sequentially through at least two metal layers 11 of the connection of via layer 4.Third metal layer group 3 directly with the antistatic MOS in chip
Field-effect tube connection can discharge needs according to voltage, select 11 number of metal layer of third metal layer group 3.
In some embodiments of the invention, the thickness of the first metal layer 1 is respectively greater than the second metal layer group 2
11 thickness of metal layer and the third metal layer group 3 metal layer 11 thickness.The window area of the first metal layer 1 is as weldering
Disk can simplify the number of plies of entire bed course inner metal layer 11, and biggish thickness can also make under it by increasing its thickness
The bed course other parts of side and the other parts of input/output structure (IO) by routing pressure and are not pullled stress and are influenced, in turn
Guarantee the electric connection between the antistatic metal-oxide-semiconductor field effect transistor in pad to chip.
In some embodiments of the invention, the first metal layer 1 far from the second metal layer group 2 side also
Equipped with passivation layer 12.Passivation layer 12 can protect the first metal layer 1, second metal layer group 2 and third metal layer group 3.
In some embodiments of the invention, the passivation layer 12 is equipped with wiring window 13, sudden and violent at the wiring window 13
Expose the first metal layer 1, the first metal layer 1 i.e. pad exposed is connect by bonding wire 15 with packaging frame.It is blunt
Change the wiring window 13 that the setting of layer 12 is used for routing, lead, lead are pulled out by the first metal layer 1 leaked out at wiring window 13
Far from pad stress area and the input and output area 6 in second metal layer group 2, input and output power supply area 7,8 and of logic area
Cabling except the region in logic power area 9.
In some embodiments of the invention, the first metal layer 1 is equipped at least one anti-stress hole 14.First metal
13 region of wiring window of layer 1 is as pad, if deformation will affect the electricity in bonding wire and chip between antistatic metal-oxide-semiconductor field effect transistor
Connection, influence its anti-static ability, and expand with heat and contract with cold or other influences caused by the first metal layer 1 generate stress, easily
Cause its deformation, and anti-stress hole 14 is set, by stress elimination, can avoid being deformed shadow when generating stress and deformation
Ring leg and being electrically connected between antistatic metal-oxide-semiconductor field effect transistor in chip；Preferably, the section in anti-stress hole 14 is designed as rectangle
Or strip.
In some embodiments of the invention, the first metal layer 1, the second metal layer group 2, the third metal
Layer group 3 and via layer 4 are embedded in dielectric layer；The via layer 4 includes that at least one is embedded at the conjunction in the dielectric layer
Principal column 10.Multiple alloy columns 10 form sets of vias, for connecting different metal layers 11, including connection second metal layer group
Different metal layer 11 in 2, connection the first metal layer 1 and the metal layer 11 in second metal layer group 2, connect second metal layer group
The metal layer 11 in metal layer 11 and third metal layer group 3 in 2.
In some embodiments of the invention, the second metal layer group 2 includes that the conducting area 5 or multiple is mutual
The independent conducting area 5.As shown in Figure 1 to Figure 3, the case where being equipped with conducting area 5 for second metal layer group 2, such as Fig. 4 institute
Show, sets the case where there are two conducting area 5 for second metal layer group 2.Certainly, finer by carrying out second metal layer group 2
To divide, multiple conducting areas 5 can be set, this is communicated with two the separate of conducting areas 5 in one conducting area 5 of setting and setting,
Its preparation process is also identical.
The bed course of chip input/output structure provided by the invention reduces chip area, and tests in actual package
In, meet encapsulation and require, and antistatic (ESD) ability has passed through greater than 8KV HBM ESD test.
It is defeated including the chip the present invention also provides a kind of chip input/output structure based on same invention thinking
Enter the bed course of export structure.
Based on same invention thinking, the present invention provides a kind of chips, including the chip input/output structure.
It should be noted that, in this document, the relational terms of such as " first " and " second " or the like are used merely to one
A entity or operation with another entity or operate distinguish, without necessarily requiring or implying these entities or operation it
Between there are any actual relationship or orders.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (16)
1. a kind of bed course of chip input/output structure, which is characterized in that including being set gradually along the direction close to chip device
The first metal layer (1), second metal layer group (2) and third metal layer group (3)；
The second metal layer group (2) includes mutually independent conducting area (5), input and output power supply area (7) and input and output
Area (6), the conducting area (5) pass through via layer (4) and the first metal layer (1) and the third metal layer group (3) respectively
Connection, the first metal layer (1) connect with packaging frame, the third metal layer group (3), the input and output power supply area
(7) it is connected to respectively with the antistatic metal-oxide-semiconductor field effect transistor in chip with the input and output regional (6).
2. the bed course of chip input/output structure according to claim 1, which is characterized in that the second metal layer group
(2) by its thickness direction include pass sequentially through via layer (4) connection at least two metal layers (11), the via layer (4) and
At least two layers metal layer (11) is including mutually independent conducting area (5), input and output power supply area (7) and input and output
Conducting area (5) composition described second of area (6), the conducting area (5) of the via layer (4) and at least two layers metal layer (11)
The conducting area (5) of metal layer group (2), the input and output power supply area (7) and at least two layers metal layer of the via layer (4)
(11) input and output power supply area (7) forms the input and output power supply area (7) of the second metal layer group (2), the via layer
(4) input and output regional (6) and the input and output regional (6) of at least two layers metal layer (11) form second metal
The input and output of layer group (2) are regional (6).
3. the bed course of chip input/output structure according to claim 1, which is characterized in that the third metal layer group
(3) it is connect respectively with the end D at the end D of N-type antistatic metal-oxide-semiconductor field effect transistor (16) and p-type antistatic metal-oxide-semiconductor field effect transistor (17).
4. the bed course of chip input/output structure according to claim 1, which is characterized in that the input and output power supply area
(7) it is connect with the end S of p-type antistatic metal-oxide-semiconductor field effect transistor (17).
5. the bed course of chip input/output structure according to claim 1, which is characterized in that the input and output area
(6) it is connect with the end S of N-type antistatic metal-oxide-semiconductor field effect transistor (16).
6. the bed course of chip input/output structure according to claim 2, which is characterized in that the second metal layer group
It (2) further include mutually independent with the conducting area (5), the input and output power supply area (7) and the input and output regional (6)
Logic power area (9) and logic are regional (8), and the logic power area (9) and the logic regional (8) are also mutually indepedent；
The logic power area (9) and the logic regional (8) are connect with the logic area (18) in chip respectively.
7. the bed course of chip input/output structure according to claim 6, which is characterized in that the via layer (4) and extremely
Few two layers of metal layer include respectively with the conducting area (5), the input and output power supply area (7) and the input and output
Regional (6) mutually independent logic power area (9) and logic area (8), the logic power area (9) of the via layer (4) and extremely
The logic power area (9) of few two layers of metal layer (11) forms the logic power area (9) of the second metal layer group (2), institute
The logic regional (8) of the logic regional (8) and at least two layers metal layer (11) of stating via layer (4) forms second metal
The logic of layer group (2) is regional (8).
8. the bed course of chip input/output structure according to claim 2, which is characterized in that the third metal layer group
It (3) include one layer of metal layer (11) or at least two metal layers (11) for passing sequentially through via layer (4) connection by its thickness direction.
9. the bed course of chip input/output structure according to claim 8, which is characterized in that the first metal layer (1)
Thickness be respectively greater than the second metal layer group (2) metal layer (11) thickness and the third metal layer group (3) gold
Belong to the thickness of layer (11).
10. the bed course of chip input/output structure according to claim 9, which is characterized in that the first metal layer (1)
Be additionally provided with passivation layer (12) far from the side of the second metal layer group (2).
11. the bed course of chip input/output structure according to claim 10, which is characterized in that the passivation layer (12) sets
Have wiring window (13), exposes the first metal layer (1) at the wiring window (13), first metal exposed
Layer (1) is connect by bonding wire (15) with packaging frame.
12. the bed course of chip input/output structure according to claim 1, which is characterized in that the first metal layer (1)
Equipped at least one anti-stress hole (14).
13. the bed course of -12 described in any item chip input/output structures according to claim 1, which is characterized in that described first
Metal layer (1), the second metal layer group (2), the third metal layer group (3) and via layer (4) are embedded in dielectric layer；
The via layer (4) includes the alloy column (10) that at least one is embedded in the dielectric layer.
14. the bed course of -12 described in any item chip input/output structures according to claim 1, which is characterized in that described second
Metal layer group (2) includes a conducting area (5) or multiple mutually independent conducting areas (5).
15. a kind of chip input/output structure, which is characterized in that including the described in any item chip inputs of claim 1 to 14
The bed course of export structure.
16. a kind of chip, which is characterized in that including the chip input/output structure described in claim 15.
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