CN110459155B

CN110459155B - Display panel and detection method thereof

Info

Publication number: CN110459155B
Application number: CN201910810575.2A
Authority: CN
Inventors: 李广耀; 王东方; 汪军; 王海涛
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-08-29
Filing date: 2019-08-29
Publication date: 2022-10-25
Anticipated expiration: 2039-08-29
Also published as: CN110459155A

Abstract

A display panel and its detection method, wherein, the display panel includes the grid drive circuit and multiple first test signal lines; the gate driving circuit includes a plurality of cascaded shift registers, each shift register including: a control sub-circuit; a control sub-circuit, connected to the first signal input terminal, the first power terminal, the second power terminal and the pull-up node, for providing the signal of the first signal input terminal to the pull-up node and maintaining the potential of the pull-up node under the control of the first power terminal and the second power terminal; the pull-up node is connected to a first test signal line. According to the embodiment of the application, whether the control sub-circuit of the shift register is abnormal or not is determined by detecting the output signal waveform of the first test signal line.

Description

Display panel and detection method thereof

Technical Field

The present disclosure relates to display technologies, and particularly to a display panel and a method for detecting the same.

Background

Currently, the trend of display panels is the panel design and quality of narrow bezel. However, the inventor has found that the gate driving circuit in the display panel in the related art includes Thin Film Transistors (TFTs) with different width-to-length ratios (W/L), and the structure is complex, and the abnormality of any one TFT may cause Mura in brightness non-uniformity in the panel, and even some regions may not display. Therefore, how to increase the detection rate of the abnormal portion of the gate driving circuit in the display panel is an urgent technical problem to be solved.

Disclosure of Invention

The application provides a display panel and a detection method thereof, which can improve the detection rate of abnormal parts of a gate drive circuit in the display panel.

In one aspect, the present application provides a display panel, comprising: a gate driving circuit, a plurality of first test signal lines; the gate driving circuit includes a plurality of cascaded shift registers, each shift register including: a control sub-circuit; the control sub-circuit is connected with the first signal input end, the first power end, the second power end and the pull-up node, and is used for providing a signal of the first signal input end to the pull-up node and maintaining the potential of the pull-up node under the control of the first power end and the second power end; the pull-up node is connected with a first test signal line so as to determine whether the control sub-circuit has an abnormality or not by detecting an output signal waveform of the first test signal line in a detection stage.

In another aspect, the present application provides a method for detecting a display panel, which is used for detecting the display panel as described above; the detection method comprises the following steps: in the detection stage, a first test signal is provided for a first signal input end, a first power supply end and a second power supply end in each stage of shift register; and determining whether the control sub-circuit of the shift register of the display panel has an abnormality by detecting the output signal waveform of the first test signal line.

The display panel comprises a grid driving circuit and a plurality of first test signal lines, wherein in a detection stage, a first test signal is provided for a first signal input end, a first power supply end and a second power supply end in each stage of shift register, so that cascaded shift registers become a short-circuit structure, and whether a control sub-circuit of the shift register is abnormal or not is determined by detecting the waveform of an output signal of the first test signal line. Therefore, on the basis of not influencing the normal function of the display panel, the area detection of the gate driving circuit can be independently carried out, so that the abnormal part of the gate driving circuit in the display panel can be effectively detected, and the detection rate of the abnormal part of the gate driving circuit in the display panel is improved.

In an exemplary embodiment, the display panel may further include a plurality of second test signal lines, the test signal may be provided to the first clock signal terminal or the third power source terminal of the shift register for any one of the stages of the shift register in the test stage, and whether there is an abnormality in the output sub-circuit or the output terminal pull-down sub-circuit of the shift register may be determined by detecting an output signal waveform of the second test signal lines. Therefore, on the basis of not influencing the normal function of the display panel, the area detection of the gate driving circuit can be further supported, so that the detection rate of abnormal parts in the gate driving circuit in the display panel is effectively improved.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the written description and claims hereof, as well as the appended drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but rather are merely intended to illustrate the context of the application.

Fig. 1 is a schematic structural diagram of a shift register in a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another shift register in a display panel according to an embodiment of the present disclosure;

fig. 3 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

fig. 4 is a schematic partial cross-sectional view of a display panel according to an embodiment of the present application;

fig. 5 is a top view of a display panel provided in an embodiment of the present application;

fig. 6 is an exemplary diagram of the operation timing of the detection stage in the embodiment of the present application.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Unless otherwise defined, technical or scientific terms used throughout the disclosure of the embodiments of the present application shall have the ordinary meaning as understood by those having ordinary skill in the art to which the present application belongs. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It will be appreciated by those skilled in the art that the transistors employed in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Illustratively, the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and the drain of the transistor used herein are symmetrical, the source and the drain can be interchanged. In the embodiment of the present application, in order to distinguish two electrodes of a transistor except for a gate, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source or a drain, the second electrode may be a drain or a source, and the gate of the transistor is referred to as a control electrode.

In order to effectively detect an abnormal portion of a gate driving circuit in a display panel to improve a detection rate of the abnormal portion of the gate driving circuit in the display panel, embodiments of the present application provide a display panel and a detection method thereof. In this embodiment, on the basis of not affecting the normal function of the display panel, a plurality of first test signal lines are led out from the gate driving circuit, so as to support the abnormal detection of the control sub-circuit in each stage of the shift register; and a plurality of second test signal lines can be led out from the gate drive circuit, so that the abnormal detection of the output sub-circuit or the output end pull-down sub-circuit in each stage of the shift register is supported, and the region detection of the gate drive circuit is supported. In addition, in the detection stage of the display panel provided by the embodiment of the application, different test waveforms can be provided for different detection areas to realize area detection of the gate driving circuit, so that the detection rate of abnormal parts of the gate driving circuit is improved.

An embodiment of the present application provides a display panel, including: a gate driving circuit and a plurality of first test signal lines; the grid driving circuit comprises a plurality of cascaded shift registers. A first test signal line is led out from each shift register and used for detecting whether the control sub-circuit of the corresponding shift register is abnormal or not through the first test signal line.

Fig. 1 is a schematic diagram of an exemplary structure of a shift register in a display panel according to an embodiment of the present disclosure. As shown in fig. 1, each shift register includes: the circuit comprises a control sub-circuit, an output sub-circuit and an output end pull-down sub-circuit.

The control sub-circuit is connected to the first signal INPUT terminal INPUT1, the first power terminal VGH, the second power terminal VGL1 and the pull-up node PU, and configured to provide a signal of the first signal INPUT terminal INPUT1 to the pull-up node PU, and maintain a potential of the pull-up node PU under the control of the first power terminal VGH and the second power terminal VGL1.

The output sub-circuit is connected with the first clock signal terminal CLK1, the signal output terminal OUT and the pull-up node PU, and is configured to provide a signal of the first clock signal terminal CLK1 to the signal output terminal OUT under the control of the pull-up node PU.

The output end pull-down sub-circuit is connected with the RESET signal end RESET, the third power end VGL2 and the signal output end OUT, and is used for providing a signal of the third power end VGL2 for the signal output end OUT under the control of the RESET signal end RESET.

The first TEST signal line TEST1 may be led out from the pull-up node PU to support the detection of the control sub-circuit of the shift register for the presence of an abnormality through the output signal waveform of the first TEST signal line in the subsequent detection stage.

Fig. 2 is a schematic diagram of another exemplary structure of a shift register in a display panel according to an embodiment of the present disclosure. As shown in fig. 2, each shift register includes: the circuit comprises an input sub-circuit, a control sub-circuit, a first output sub-circuit, a second output sub-circuit and an output end pull-down sub-circuit.

The INPUT sub-circuit is connected to the third clock signal terminal CLKE, the second signal INPUT terminal INPUT2 and the pull-up node PU, and is configured to provide the signal of the second signal INPUT terminal INPUT2 to the pull-up node PU under the control of the third clock signal terminal CLKE. The display panel provided by the example can be applied to the preparation of an OLED Television (TV); the second signal INPUT terminal INPUT2 may be connected to an output terminal of a sensing (sense) unit, and the sensing unit is used for supporting external compensation. In the process of compensating the interior of the display panel by the sensing unit in the shift register, the sensing unit is opened, and the first signal output end OUT1 and the second signal output end OUT2 output signals.

The pull-up node PU is connected to the first signal INPUT terminal INPUT 1. The first signal INPUT terminal INPUT1 of the shift register of the nth stage is connected to the cascade signal output terminal CR < N-X > of the shift register of the nth-X stage, where X is greater than or equal to 1. The value of X is not limited in this application. The first signal INPUT end INPUT1 of the first-stage to Xth-stage shift registers is connected with an initial signal end STV; for example, if X is 1, the first signal INPUT terminal INPUT1 of the first stage shift register is connected to the initial signal terminal STV; and X is 2, the first signal INPUT ends INPUT1 of the first-stage and second-stage shift registers are connected with the initial signal end STV.

Wherein the control sub-circuit comprises: the circuit comprises an inverter sub-circuit, a voltage stabilizing sub-circuit, a down-transmission sub-circuit and an input end pull-down sub-circuit.

The voltage stabilizing sub-circuit is connected with the second power supply end VGL1, the pull-up node PU and the output end of the inverting sub-circuit; the input end of the inverting sub-circuit is connected with the pull-up node PU, and the inverting sub-circuit is used for taking the potential of the pull-up node PU as an input signal and outputting a signal to control the voltage stabilizing sub-circuit to enable the potential of the pull-up node PU to be stable.

The downstream sub-circuit is connected to the pull-up node PU, the second clock signal terminal CLK2, and the cascade signal output terminal CR, and configured to provide a signal of the second clock signal terminal CLK2 to the cascade signal output terminal CR under the control of the pull-up node PU.

The input end pull-down sub-circuit is connected with the RESET signal end RESET, the second power supply end VGL1 and the pull-up node PU, and is used for providing a signal of the second power supply end VGL1 to the pull-up node PU under the control of the RESET signal end RESET. The RESET signal end RESET of the Nth-stage shift register is connected with the cascade signal output end CR < N + Y > of the (N + Y) -th-stage shift register, wherein Y is larger than or equal to 1. The value of Y in the present application is not limited. The input terminal pull-down sub-circuit is used for pulling down the pull-up node PU in the reset stage so as to reduce noise.

The first output sub-circuit is connected to the first sub-clock signal terminal CLK11, the pull-up node PU, and the first signal output terminal OUT1, and configured to provide a signal of the first sub-clock signal terminal CLK11 to the first signal output terminal OUT1 under the control of the pull-up node PU.

The second output sub-circuit is connected to the second sub-clock signal terminal CLK12, the pull-up node PU, and the second signal output terminal OUT2, and configured to provide a signal of the second sub-clock signal terminal CLK12 to the second signal output terminal OUT2 under the control of the pull-up node PU.

The output terminal pull-down sub-circuit is connected with the RESET signal terminal RESET, the third power terminal VGL2, the first signal output terminal OUT1 and the second signal output terminal OUT2, and is used for providing signals of the third power terminal VGL2 to the first signal output terminal OUT1 and the second signal output terminal OUT2 under the control of the RESET signal terminal RESET. The output end pull-down sub-circuit is used for pulling the signal output end low in the reset stage.

Fig. 3 is an equivalent circuit diagram of a shift register according to an embodiment of the present application. As shown in fig. 3, the output sub-circuit includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit includes: a first transistor M1 and a first capacitor C1; a control electrode of the first transistor M1 is connected to the pull-up node PU, a first electrode of the first transistor M1 is connected to the first sub-clock signal terminal CLK11, and a second electrode of the first transistor M1 is connected to the first signal output terminal OUT 1; a first electrode of the first capacitor C1 is connected to the control electrode of the first transistor M1, and a second electrode of the first capacitor C1 is connected to the first signal output terminal OUT 1.

As shown in fig. 3, the second output sub-circuit includes: a second transistor M2 and a second capacitor C2; a control electrode of the second transistor M2 is connected to the pull-up node PU, a first electrode of the second transistor M2 is connected to the second sub-clock signal terminal CLK12, and a second electrode of the second transistor M2 is connected to the second signal output terminal OUT 2; a first electrode of the second capacitor C2 is connected to the control electrode of the second transistor M2, and a second electrode of the second capacitor C2 is connected to the second signal output terminal OUT 2.

As shown in fig. 3, the INPUT sub-circuit includes a third transistor M3, a control electrode of the third transistor M3 is connected to the third clock signal terminal CLKE, a first electrode of the third transistor M3 is connected to the second signal INPUT terminal INPUT2, and a second electrode of the third transistor M3 is connected to the pull-up node PU.

As shown in fig. 3, the input terminal pull-down sub-circuit includes a fourth transistor M4, a control electrode of the fourth transistor M4 is connected to the RESET signal terminal RESET, a first electrode of the fourth transistor M4 is connected to the pull-up node PU, and a second electrode of the fourth transistor M4 is connected to the second power source terminal VGL1.

As shown in fig. 3, the inverting sub-circuit includes: a fifth transistor M5 and a sixth transistor M6; a control electrode and a first electrode of the fifth transistor M5 are connected to the first power supply terminal VGH, a second electrode of the fifth transistor M5 is connected to a first electrode of the sixth transistor M6, a control electrode of the sixth transistor M6 is connected to the pull-up node PU, and a second electrode of the sixth transistor M6 is connected to the second power supply terminal VGL1. The output terminal PD of the inverting sub-circuit is connected to the second pole of the fifth transistor M5 and the first pole of the sixth transistor M6.

As shown in fig. 3, the regulator sub-circuit includes: and a control electrode of the seventh transistor M7 is connected to the output terminal PD of the inverter sub-circuit, a first electrode of the seventh transistor M7 is connected to the pull-up node PU, and a second electrode of the seventh transistor M7 is connected to the second power supply terminal VGL1.

When the potential of the pull-up node PU is at a high potential and the first power supply terminal VGH is at a low potential, the potential of the output terminal PD of the inverting sub-circuit is at a low potential, so that the seventh transistor M7 is turned off, and the potential of the pull-up node PU is maintained at the high potential; when the voltage level of the pull-up node PU is low and the first power source terminal VGH is high, the voltage level of the output terminal PD of the inverter sub-circuit is high, so that the seventh transistor M7 is turned on, and thus the second power source terminal VGL1 (low voltage level) is input to the pull-up node PU, and the voltage level of the pull-up node PU is maintained at the low voltage level.

As shown in fig. 3, the down sub-circuit includes an eighth transistor M8, a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode of the eighth transistor M8 is connected to the second clock signal terminal CLK2, and a second electrode of the eighth transistor M8 is connected to the cascade signal output terminal CR. The down sub-circuit of the nth stage shift register can provide an input signal for the inverting sub-circuit of the (N + X) th stage shift register and can also provide a reset signal for the pull-down sub-circuit of the (N-Y) th stage shift register.

As shown in fig. 3, the pull-down sub-circuit includes a ninth transistor M9 and a tenth transistor M10; a control electrode of the ninth transistor M9 is connected to the RESET signal terminal RESET, a first electrode of the ninth transistor M9 is connected to the first signal output terminal OUT1, and a second electrode of the ninth transistor M9 is connected to the third power supply terminal VGL2; a control electrode of the tenth transistor M10 is connected to the RESET signal terminal RESET, a first electrode of the tenth transistor M10 is connected to the second signal output terminal OUT2, and a second electrode of the tenth transistor M10 is connected to the third power source terminal VGL 2.

In the present embodiment, an exemplary structure of the input sub-circuit, the control sub-circuit, the output sub-circuit, and the output terminal pull-down sub-circuit is specifically shown in fig. 3. Those skilled in the art will readily appreciate that the implementation of the input sub-circuit, the control sub-circuit, the output sub-circuit, and the output pull-down sub-circuit is not limited thereto as long as the functionality thereof is achieved.

As shown in fig. 3, the first TEST signal line TEST1 may be led out from the first electrode of the first capacitor C1 (i.e., the control electrode of the first transistor M1) to support that whether there is an abnormality in the control sub-circuit of the corresponding shift register may be detected by the output signal waveform of the first TEST signal line in a subsequent detection stage. The second TEST signal lines are in one-to-one correspondence with the signal output terminals, and as shown in fig. 3, the second TEST signal line TEST21 may be led OUT from the first signal output terminal OUT1, and the second TEST signal line TEST22 may be led OUT from the second signal output terminal OUT 2. However, this is not limited in this application. For example, in other implementations, the first test signal line may be led out from the first electrode of the second capacitor C2 (the control electrode of the second transistor M2).

On the basis of not affecting the normal function, the display panel provided by the embodiment leads out a first test signal line and a second test signal line from each shift register of the gate driving circuit, and is used for supporting the split-region detection of the gate driving circuit.

As shown in fig. 4, the display panel provided in this embodiment further includes: the light-shielding layer SHILLED, the BUFFER layer BUFFER, the grid layer GATE, the interlayer insulating layer ILD, the source and drain electrode layer SD and the passivation layer PVX are sequentially arranged on the substrate; the first test signal line and the second test signal line are arranged on the same layer and are arranged on one side, far away from the substrate, of the passivation layer PVX.

In this embodiment, the first electrode of each capacitor is disposed on the same layer as the GATE layer GATE, the first electrode of each capacitor is connected to the pull-up node PU, the interlayer insulating layer ILD and the passivation layer PVX are disposed with a first through hole, and the first test signal line is connected to the first electrode of the first capacitor C1 or the first electrode of the second capacitor C2 through the first through hole.

As shown in fig. 4, the second electrode of each capacitor may be disposed at the same layer as the light shielding layer SHIELD. Taking the first capacitor C1 as an example for description, since the second electrode of the first capacitor C1 is connected to the source or the drain of the first transistor M1, the second electrode disposed on the same layer as the light shielding layer SHIELD may be connected to the source/drain electrode layer SD to realize connection with the source or the drain of the first transistor M1.

In this embodiment, the first test signal line and the second test signal line may be made of a transparent conductive material, such as indium tin oxide ITO. For example, a transparent conductive film is deposited on the side of the passivation layer PVX away from the substrate, and the transparent conductive film is patterned by a patterning process to form a pattern of a first test signal line and a second test signal line (e.g., an ITO layer as shown in fig. 4).

Fig. 5 is a top view of the display panel provided in this embodiment. The first test signal line is connected to the first electrode of the first capacitor C1. As shown in fig. 4 and 5, the first electrode of the first capacitor C1 is disposed on the same layer as the gate electrode layer 12, and the first through hole 20 is disposed on the interlayer insulating layer and the passivation layer such that the first test signal line (corresponding to the ITO layer 16) formed outside the passivation layer is connected to the first electrode of the first capacitor C1 through the first through hole 20. Here, 14 denotes the source/drain electrode layer SD.

In this embodiment, the display panel further includes: a gate line disposed on the substrate. The second TEST signal line TEST21 connected to the first signal output terminal OUT1 will be described as an example. In order to realize the driving of the display circuit, the first signal output terminal OUT1 is connected to a gate line of the display circuit to provide a driving signal to the display circuit. For the convenience of the subsequent detection, the second TEST signal line TEST21 is disposed at the same layer as the first TEST signal line TEST1, and a second through hole may be disposed on the passivation layer PVX, through which the second TEST signal line TEST21 may be connected to the first signal output terminal OUT1 connected to the gate line. The first signal output end OUT1 of the shift register is connected to the source or the drain of the first transistor M1, and the second TEST signal line TEST21 is connected to the source or the drain of the first transistor M1, which is disposed on the source/drain layer SD and connected to the gate line, through the second through hole, so that the second TEST signal line TEST21 is connected to the gate line. Similarly, the second TEST signal line TEST22 may be connected to the second signal output terminal OUT2 connected to the gate line through a second through hole provided on the passivation layer PVX.

It should be noted that, compared to the related art, the manufacturing process of the display panel in this embodiment is the same as that of the related art except for adding and leading out the first test signal line and the second test signal line. Moreover, the punching process can also refer to the related art, and thus, the details are not repeated herein.

Based on the gate driving circuit in the display panel provided in this embodiment in fig. 1, the method for detecting the display panel provided in this embodiment may include: in the detection stage, a first test signal is provided to a first signal INPUT end INPUT1, a first power supply end VGH and a second power supply end VGL1 in each stage of the shift register; by detecting the output signal waveform of the first TEST signal line TEST1, it is determined whether or not there is an abnormality in the control sub-circuit of the shift register.

In an exemplary embodiment, for any stage of shift register, when it is detected that the waveform of the output signal of the first TEST signal line TEST1 led out from the stage of shift register is equal to the waveform of a first TEST signal, which is a high potential signal, it is determined that the control sub-circuit of the shift register is normal. In this embodiment, a continuous high potential signal is provided to the first signal INPUT terminal INPUT1, the first power supply terminal VGH, and the second power supply terminal VGL1 of each stage of the shift register, so that the cascade structure of the shift register is changed to a short-circuit (Shorting) structure, and at this time, a high potential may exist at the pull-up node PU theoretically, and whether an abnormality exists in the transistor in the control sub-circuit is determined by detecting whether an output signal waveform of the first TEST signal line TEST1 led out from the pull-up node PU is maintained at the high potential.

Based on the gate driving circuit in the display panel provided in this embodiment and fig. 2, the method for detecting a display panel provided in this embodiment includes:

in the detection phase, a continuous low-level signal is provided to the third clock signal terminal CLKE of each stage of the shift register, and a first test signal (e.g., a continuous high-level signal) is provided to the first signal INPUT terminal INPUT1, the first power terminal VGH, and the second power terminal VGL 1; by detecting the output signal waveform of the first TEST signal line TEST1, it is determined whether or not there is an abnormality in the control sub-circuit of the shift register.

Wherein, in the stage of detecting the control sub-circuit, the clock control terminals CLK11, CLK12 and the third power terminal VGL2 can be turned off; alternatively, the clock control terminals CLK11 and CLK12 and the third power supply terminal VGL2 are supplied with the low potential signals continuously.

In this embodiment, when detecting the control sub-circuit of each stage of the shift register, the second signal INPUT terminal INPUT2 is prevented from affecting the detection process by providing the third clock signal terminal CLKE with a continuous low-level signal. By providing a continuous high potential signal to the first signal INPUT terminal INPUT1, the first power supply terminal VGH, and the second power supply terminal VGL1, the cascade structure of the shift register is changed to a short circuit (Shorting) structure, and at this time, a high potential theoretically exists at the pull-up node PU, and whether an abnormality exists in a transistor in the control sub-circuit is determined by detecting whether an output signal waveform of the first test signal line led out from the pull-up node PU is maintained at the high potential.

Wherein, in the case where the transistors in the control sub-circuit are all normal, the output signal waveform of the first TEST signal line TEST1 is equal to the waveform of the first TEST signal (maintained at a high potential); when the output signal waveform of the first TEST signal TEST1 led out from a certain stage of shift register is detected not to be maintained at a high potential, the fact that the transistor in the control sub-circuit of the shift register is abnormal is indicated, and therefore a fault area can be determined so as to facilitate further processing.

In an exemplary embodiment, since the first signal INPUT terminal INPUT1 of the first to X-th stage shift registers is connected to the initial signal terminal STV, a first test signal (a sustained high signal) is supplied to the initial signal terminal STV; since the first signal INPUT terminal INPUT1 of the nth stage shift register is connected to the cascade signal output terminal CR < N-X > of the nth-X stage shift register, the first test signal (a sustained high signal) may be supplied to the second clock signal terminal CLK2 of the nth-X stage shift register. When the pull-up node PU is at a high level, the cascade signal output terminal CR < N-X > of the nth-X stage shift register continuously provides the first test signal (high level signal), so that the first signal INPUT terminal INPUT1 of the nth stage shift register continuously receives the first test signal (high level signal).

Based on the gate driving circuit in the display panel provided in this embodiment and fig. 2, the method for detecting a display panel provided in this embodiment may further include:

for any stage of shift register, in a detection stage, a second TEST signal is simultaneously provided for a first sub-clock signal terminal CLK11 and a second sub-clock signal terminal CLK12 of the shift register, a continuous low-potential signal is provided for a third power supply terminal, and whether an output sub-circuit of the shift register is abnormal or not is determined by detecting output signal waveforms of a second TEST signal line TEST21 and TEST 22;

and simultaneously supplying a continuous low potential signal to the first sub-clock signal terminal CLK11 and the second sub-clock signal terminal CLK12 of the shift register, supplying a third TEST signal to a third power supply terminal, and determining whether there is an abnormality in the pull-down sub-circuit at the output terminal of the shift register by detecting the output signal waveforms of the second TEST signal lines TEST21 and TEST 22.

FIG. 6 is a diagram illustrating an exemplary operation sequence of the detection stage in the embodiment of the present application. In this embodiment, when the pull-up node PU maintains a high voltage level, the output sub-circuit and the output pull-down sub-circuit of any stage of the shift register can be detected. For any stage of shift register, in case that it is detected that the control sub-circuit of the stage of shift register is normal, the pull-up node PU is continuously maintained at the high level, and the second test signal (e.g., pulse signal) is simultaneously provided to the first sub-clock signal terminal CLK11 and the second sub-clock signal terminal CLK12, and the continuous low level signal is provided to the third power terminal VGL2, for example, during the period T1 as shown in fig. 6. Then, whether or not there is an abnormality in the transistors in the first output sub-circuit is determined by detecting the output signal waveform of the second TEST signal line TEST21, and whether or not there is an abnormality in the transistors in the second output sub-circuit is determined by detecting the output signal waveform of the second TEST signal line TEST 22. When the output signal waveform of the second TEST signal line TEST21 is detected to be matched with the waveform of the second TEST signal, the transistor in the first output sub-circuit is determined to be normal, otherwise, the transistor in the first output sub-circuit is considered to be abnormal. When the output signal waveform of the second TEST signal line TEST22 is detected to be matched with the waveform of the second TEST signal, the transistor in the second output sub-circuit is determined to be normal, otherwise, the transistor in the first output sub-circuit is considered to be abnormal. As shown in fig. 6, the first output sub-circuit and the second output sub-circuit of the shift register of this stage are in a normal state.

In this embodiment, for any stage of shift register, in case that it is detected that the control sub-circuit of the stage of shift register is normal, the pull-up node PU is continuously maintained at the high level, and the low level signal is continuously provided to the first sub-clock signal terminal CLK11 and the second sub-clock signal terminal CLK12 at the same time, and the second test signal (e.g., pulse signal) is provided to the third power terminal VGL2, for example, at the T2 stage as shown in fig. 6. Then, by detecting the output signal waveforms of the second TEST signal lines TEST21, TEST22, it is determined whether or not there is an abnormality in the transistors in the output terminal pull-down sub-circuit. When the output signal waveforms of the second TEST signal lines TEST21 and TEST22 are matched with the waveform of the second TEST signal, the transistors in the output end pull-down sub-circuit are determined to be normal, otherwise, the transistors in the output end pull-down sub-circuit are considered to be abnormal. As shown in fig. 6, the output terminal pull-down sub-circuit of the shift register stage is in a normal state.

In an exemplary embodiment, for any stage of shift register, in case that it is detected that there is an abnormality in the control sub-circuit of the stage of shift register, the pull-up node PU cannot be maintained at the high potential, and at this time, a first TEST signal (a continuous high potential signal) may be provided to the pull-up node PU through the first TEST signal line TEST1 to support the detection of the output sub-circuit or the output pull-down sub-circuit of the stage of shift register.

In an exemplary embodiment, for any stage of the shift register, when the output sub-circuit of the stage of the shift register includes only one signal output terminal, a second test signal line may be drawn from the signal output terminal, and the second test signal line may be used to detect whether there is an abnormality in the output sub-circuit and the output terminal pull-down sub-circuit of the stage of the shift register. Aiming at any stage of shift register, in the detection stage, a second test signal is provided for a first clock signal end of the stage of shift register, a continuous low-potential signal is provided for a third power supply end, and whether an output sub circuit of the shift register is abnormal or not is determined by detecting the output signal waveform of a second test signal line connected with a signal output end of the stage of shift register; aiming at any stage of shift register, in the detection stage, a continuous low-potential signal is provided for the first clock signal end of the stage of shift register, a third test signal is provided for the third power supply end, and whether the pull-down sub-circuit at the output end of the shift register is abnormal or not is determined by detecting the waveform of the output signal of the second test signal line. The specific process of detecting through the second test signal line is the same as above, and therefore is not described herein again.

According to the detection method of the display panel, the gate driving circuit is detected in the sub-region mode through providing different test signal waveforms, and therefore the detection rate of the abnormal portion of the gate driving circuit is effectively improved.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A display panel, comprising: a gate driving circuit, a plurality of first test signal lines; the gate driving circuit includes a plurality of cascaded shift registers, each shift register including: a control sub-circuit;

the control sub-circuit is connected with the first signal input end, the first power end, the second power end and the pull-up node, and is used for providing a signal of the first signal input end to the pull-up node and maintaining the potential of the pull-up node under the control of the first power end and the second power end;

the pull-up node is connected with a first test signal line so as to determine whether the control sub-circuit has an abnormality or not by detecting the output signal waveform of the first test signal line in a detection stage;

the display panel further includes: a plurality of second test signal lines;

the shift register further includes: an output sub-circuit and an output terminal pull-down sub-circuit;

the output sub-circuit is connected with the first clock signal end, the signal output end and the pull-up node, and is used for providing a signal of the first clock signal end for the signal output end under the control of the pull-up node;

the output end pull-down sub-circuit is connected with the reset signal end, the third power end and the signal output end and is used for providing a signal of the third power end for the signal output end under the control of the reset signal end;

the signal output end is connected with a second test signal line, so that whether the output sub-circuit or the output end pull-down sub-circuit is abnormal or not is determined by detecting the output signal waveform of the second test signal line in a detection stage;

the first clock signal terminal includes: a first sub-clock signal terminal and a second sub-clock signal terminal; the signal output terminal includes: a first signal output terminal and a second signal output terminal; the first signal output end and the second signal output end are connected with the second test signal line in a one-to-one correspondence manner; the output sub-circuit includes: a first output sub-circuit and a second output sub-circuit;

the first output sub-circuit includes: a first transistor and a first capacitor; a control electrode of the first transistor is connected with the pull-up node, a first electrode of the first transistor is connected with a first sub-clock signal end, and a second electrode of the first transistor is connected with a first signal output end; a first electrode of the first capacitor is connected with a control electrode of the first transistor, and a second electrode of the first capacitor is connected with the first signal output end;

the second output sub-circuit includes: a second transistor and a second capacitor; a control electrode of the second transistor is connected with the pull-up node, a first electrode of the second transistor is connected with a second sub-clock signal end, and a second electrode of the second transistor is connected with a second signal output end; and a first electrode of the second capacitor is connected with the control electrode of the second transistor, and a second electrode of the second capacitor is connected with the second signal output end.

2. The display panel according to claim 1, wherein the display panel further comprises: the first test signal line is arranged on one side, far away from the substrate, of the passivation layer;

the first electrode of each capacitor is arranged on the same layer as the gate layer and is connected with the pull-up node, the interlayer insulating layer and the passivation layer are provided with first through holes, and the first test signal line is connected with the first electrode of the first capacitor or the first electrode of the second capacitor through the first through hole.

3. The display panel according to claim 2, wherein the second test signal line is provided in the same layer as the first test signal line;

the display panel further includes: a gate line disposed on the substrate; and the passivation layer is also provided with a second through hole, and the second test signal line is connected with the first signal output end or the second signal output end connected with the grid line through the second through hole.

4. A method for inspecting a display panel, characterized by inspecting the display panel according to any one of claims 1 to 3;

the detection method comprises the following steps:

in the detection stage, a first test signal is provided for a first signal input end, a first power supply end and a second power supply end in each stage of shift register;

and determining whether the control sub-circuit of the shift register of the display panel has an abnormality by detecting the output signal waveform of the first test signal line.

5. The method according to claim 4, wherein the determining whether there is an abnormality in a control sub-circuit of a shift register of the display panel by detecting an output signal waveform of the first test signal line includes:

and when the output signal waveform of the first test signal line is detected to be equal to the waveform of a first test signal, determining that a control sub-circuit of the shift register is normal, wherein the first test signal is a high-potential signal.

6. The method of claim 4, wherein providing the first test signal to the first signal input of the shift register of each stage comprises:

providing a first test signal to first signal input ends of the first-level to Xth-level shift registers;

and providing a first test signal to a second clock signal end of the N-X stage shift register, so that a first signal input end of the N-X stage shift register receives the first test signal provided by a cascade signal output end of a downstream sub-circuit of the N-X stage shift register, wherein X is greater than or equal to 1.

7. The method of claim 4, wherein the detection method further comprises at least one of:

aiming at any stage of shift register, in a detection stage, a second test signal is provided for a first clock signal end of the shift register, a continuous low-potential signal is provided for a third power supply end, and whether an output sub-circuit of the shift register is abnormal or not is determined by detecting the waveform of an output signal of a second test signal line;

and aiming at any stage of shift register, in a detection stage, a continuous low-potential signal is provided for a first clock signal end of the shift register, a third test signal is provided for a third power supply end, and whether the pull-down sub-circuit at the output end of the shift register is abnormal or not is determined by detecting the waveform of an output signal of the second test signal line.

8. The method according to claim 7, wherein the determining whether there is an abnormality in the output sub-circuit of the shift register by detecting the output signal waveform of the second test signal line includes: when the output signal waveform of the second test signal line corresponding to the shift register is detected to be matched with the waveform of the second test signal, determining that an output sub-circuit of the shift register is normal;

the determining whether the pull-down sub-circuit at the output end of the shift register is abnormal by detecting the output signal waveform of the second test signal line includes: and when the output signal waveform of the second test signal line corresponding to the shift register is detected to be matched with the waveform of the third test signal, determining that the pull-down sub-circuit at the output end of the shift register is normal.

9. The method of claim 7, wherein when the first clock signal terminal comprises: a first sub-clock signal terminal and a second sub-clock signal terminal, the signal output terminal comprising: the first signal output end and the second signal output end are connected with the second test signal line in a one-to-one correspondence manner;

the step of determining whether an output sub-circuit of the shift register is abnormal or not by detecting the waveform of an output signal of the second test signal line, which is to be specific to any stage of the shift register, during a detection stage, supplying a second test signal to a first clock signal terminal of the shift register, supplying a continuous low-potential signal to a third power terminal, and including:

for any stage of shift register, in a detection stage, when a pull-up node of the shift register is maintained at a high potential, a second test signal is simultaneously provided to the first sub-clock signal terminal and the second sub-clock signal terminal, a continuous low potential signal is provided to a third power supply terminal, whether a first output sub-circuit of the shift register is abnormal or not is determined by detecting an output signal waveform of a second test signal line connected with the first signal output terminal, and whether the second output sub-circuit of the shift register is abnormal or not is determined by detecting an output signal waveform of a second test signal line connected with the second signal output terminal.