CN110457149B - SRAM type FPGA reliable loading and error-proofing design method based on PowerPC control - Google Patents
SRAM type FPGA reliable loading and error-proofing design method based on PowerPC control Download PDFInfo
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- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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Abstract
The SRAM type FPGA reliable loading and error-proofing design method based on PowerPC control is disclosed. The method is used for loading the configuration file into the SRAM type FPGA, and comprises the following steps: transmitting the FPGA configuration file and the readback file from the main control computer to the PowerPC processor through a network interface of the PowerPC processor; storing the FPGA configuration file and the readback file transmitted to the PowerPC processor into a RAM; loading the configuration file into the SRAM type FPGA according to the SelectMAP parallel loading time sequence of the FPGA and returning read-back data; comparing the read-back data with the read-back file, and monitoring a single event upset detection signal of the FPGA when the read-back data is consistent with the read-back file; and reloading the configuration file when the read-back data is inconsistent with the read-back file.
Description
Technical Field
The invention relates to a reliable loading and error-proofing design method for SRAM type FPGA based on PowerPC control.
Background
In the field of aerospace, and in particular airborne radar, systems are required that are capable of processing large amounts of data at high speeds and that continue to operate reliably. As the SRAM type FPGA has abundant logic resources and has the advantages of rapid parallel processing capability and the like, the SRAM type FPGA becomes an indispensable device in airborne radar equipment.
In the prior airborne radar system, the logic resource of the SRAM type FPGA reaches millions of gates or even tens of millions of gates, and the logic loss characteristic of the SRAM type FPGA after power-down is realized, so that a Flash chip with larger capacity is required to reload logic after power-up, and the problems of overlong loading period, longer logic curing period and the like are caused. Due to the SRAM type FPGA process attribute, the problem of single event upset is easy to occur.
Traditional method for loading FPGA: the serial active loading mode is generally adopted after the plug-in Flash chip is powered on. There are certain drawbacks:
(1) The FPGA active serial loading speed is low, the solidification period of the Flash chip is long when the version is upgraded, and the storage version is single;
(2) Flash causes the situation of memory content missing or bit overturning due to the factor of error erasure or memory medium, which can cause the misoperation of logic functions and finally cause the equipment to not normally run;
(3) After the single event upset problem appears in the loading and running processes, the error correction mechanism is imperfect, and the reliable loading and reliable running of the FPGA cannot be ensured.
Disclosure of Invention
According to the method, the network is adopted for remote loading, so that a Flash chip is saved, and the hardware cost is reduced; the SelectMAP parallel loading and readback verification technology is adopted, so that the loading speed is improved, and reliable loading is realized; in addition, an SEM IP core is added or read back is performed regularly, the single event upset condition is detected, the problem is found out and error correction is performed timely, and the reliable operation of the system is realized.
According to one aspect of the present invention, there is provided a method for reliable loading and error-proofing design of an SRAM-type FPGA based on PowerPC control, the method being used for loading a configuration file into the SRAM-type FPGA, the method comprising:
transmitting the FPGA configuration file and the readback file from the main control computer to the PowerPC processor through a network interface of the PowerPC processor;
storing the FPGA configuration file and the readback file transmitted to the PowerPC processor into a RAM;
loading the configuration file into the SRAM type FPGA according to the SelectMAP parallel loading time sequence of the FPGA and returning read-back data; and
comparing the read-back data with the read-back file,
when the read-back data is consistent with the read-back file, monitoring a single event upset detection signal of the FPGA; and
and reloading the configuration file when the read-back data is inconsistent with the read-back file.
According to one embodiment, the FPGA comprises an SEM module, which monitors the single event upset in real time and generates the single event upset detection signal.
According to one embodiment, the host computer stores and transmits configuration files for each FPGA.
According to one embodiment, the RAM comprises DDR2, DDR3SDRAM and is connected to the PowerPC processor via a memory interface.
According to one embodiment, the PowerPC processor is connected to the host computer via a network interface, and the network interface supports TCP/IP protocols.
According to one embodiment, the FPGA is a chip that supports SelectMAP parallel loading and supports SEM IP cores.
According to one embodiment, the PowerPC processor includes a GPIO interface and the PowerPC processor loads the configuration file into the FPGA via the GPIO interface.
According to one embodiment, after the configuration file loading is completed, the PowerPC processor reads back a configuration memory in the FPGA via a GPIO interface according to a SelectMAP read back timing of the FPGA, wherein the configuration file is stored in the configuration memory.
According to one embodiment, when the read-back data is consistent with the read-back file, an SEM module in the FPGA is started to monitor the single event upset condition in real time, a monitoring signal is transmitted to the PowerPC in real time through a GPIO interface, and if the monitoring signal is abnormal, the configuration file is reloaded.
The invention has the following advantages:
(1) The method gives up the active loading of the traditional FPGA, saves a Flash configuration chip of the SRAM type FPGA and reduces the hardware cost;
(2) Compared with the traditional method, the remote loading based on network communication ensures that version upgrading is more convenient, flexible and efficient;
(3) The SelectMAP parallel loading and readback verification technology can realize the monitoring of the logic loading process, ensure the reliable loading of the configuration file, and improve the loading speed by improving the frequency of the configuration clock;
(4) By adding the SEM IP core, the single event upset condition is detected in real time, the problem is found out and corrected in time, and the reliable operation of the product is realized;
(5) The above functions are realized on the original product without any cost.
Aiming at a DSP+FPGA or ARM+FPGA multi-core system with network communication capability, particularly in a system with a large-capacity SRAM type FPGA and higher requirements on reliability, the method improves the loading speed, makes version upgrading and maintenance more convenient, and enables an error prevention mechanism to be more comprehensive, thereby realizing reliable loading and reliable operation of the SRAM type FPGA.
As SRAM type FPGA is used in a large amount in the fields of industrial control, artificial intelligence, civil aviation and military industry, the method has wide application prospect and great application value.
Other features of the present invention will become apparent from the following description of exemplary embodiments, which refers to the accompanying drawings.
Drawings
FIG. 1 is a schematic block diagram of a reliable loading and error proofing design of an SRAM type FPGA based on PowerPC control; and
FIG. 2 is a flow chart of the reliable loading and error proofing design of an SRAM type FPGA based on PowerPC control.
Detailed Description
Hereinafter, embodiments according to the present invention are described with reference to the accompanying drawings, but it should be understood that the following description is merely exemplary and is not intended to limit the present invention to the following embodiments.
The method and the device according to the invention are susceptible to many variations, and many of the description of the method and the device has been simplified for the sake of clarity of the brief description. Many of the descriptions use specific standard structures and terminology. However, the disclosed methods and apparatus may be more widely applicable.
Those of skill in the art will appreciate that the various illustrative logical blocks, modules, units, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, and steps have been described below in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular system, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. Furthermore, functional groupings of units, modules, blocks or steps are for ease of description. Specific functions or steps may be removed from a unit, module or block without departing from the invention.
The following description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present technology is not limited to the specific examples described below. It is to be understood, therefore, that the description and drawings presented herein represent a presently preferred embodiment of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. Further, it should be understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.
The invention provides a design method for error-proof loading and single event upset resistance of an SRAM type FPGA of an Xilinx company based on PowerPC control in an airborne radar system. The method is suitable for all systems containing SRAM type FPGA chips of Xilinx company, a main control computer transmits configuration files of the SRAM type FPGA to a system cache through a network protocol, a PowerPC processor loads the configuration files to the FPGA through a parallel loading technology and reads back the configuration files for verification, and single event upset condition is monitored when verification is carried out through SEM IP in the FPGA. The method solves the problems that the loading speed of the conventional SRAM type FPGA is low, single event upset is easy to occur in the loading and running processes, and the like. And finally, the quick remote upgrading, reliable loading and reliable operation of the SRAM type FPGA are realized.
The technical scheme comprises the following steps:
(1) TCP/IP network communication technology: the PowerPC processor supports TCP/IP network communication and receives a configuration file sent by the main control computer;
(2) SelectMAP parallel loading technique: the FPGA supports high-speed parallel loading and readback verification of logic;
(3) FPGA single event upset resistant technology: the FPGA can support SEU IP cores resistant to single event upset, and single event upset conditions are monitored in real time. In the invention, single event upset refers to the condition that O becomes 1 and 1 becomes 0 in the running process after logic is loaded into an FPGA.
According to the technical scheme, the FPGA configuration file can be quickly loaded after power-on, version upgrading is carried out at any time according to requirements in the running process, abnormal conditions such as single sheet overturning in the loading process and the running process are monitored in real time, and the reliability of the system is enhanced.
Next, the method according to the invention is further described with reference to the accompanying drawings.
First, referring to fig. 1, a block diagram according to the technical solution principle of the present invention is shown. The scheme of the invention is divided into a main control machine, a PowerPC processor, a RAM cache and an SRAM type FPGA.
The main control computer is responsible for version storage and transmission of FPGA configuration files of all subsystems.
The PowerPC processor receives the FPGA configuration file and the read-back file transmitted by the main control computer through the network interface, and caches the FPGA configuration file and the read-back file into the RAM, then loads the configuration file into the SRAM type FPGA according to the SelectMAP parallel loading time sequence, and carries out read-back verification, if the read-back data and the read-back file are consistent, the successful loading is indicated, and if the read-back data and the read-back file are inconsistent, the loading is considered to be failed, the loading is reloaded. After successful loading, the FPGA operates normally, a PowerPC processor monitors a single event upset detection signal (a signal provided by an SEM module) of the FPGA in real time, and if single event upset occurs, the FPGA is considered to have partial function errors, and the PowerPC processor reloads the configuration file.
In the present exemplary embodiment, the SelectMAP bus is a bidirectional bus, and read-back verification is also performed through the SelectMAP bus. Further, the readback data may be data read back as it is from a configuration file loaded into the FPGA, and the readback file is a file existing in the RAM. In addition, the term "consistent" is the case where, for example, bits of bytes are all the same, otherwise inconsistent.
The RAM cache is a storage component of SRAM type FPGA configuration files and read-back files, such as DDR2, DDR3SDRAM and the like;
the SRAM type FPGA is an FPGA product of Xilinx company comprising an SEM IP core, can detect the single sheet turnover condition of the SRAM type FPGA in real time, and transmits detection signals to the PowerPC processor in real time.
In the invention, the system is required to be a PowerPC+FPGA architecture, and the specific composition is as follows:
(1) PowerPC processor: has the following interface circuits:
1) The network interface supports TCP/IP communication protocol, and performs network communication with the main control computer to complete the request and the reception of the FPGA configuration file and the read-back file;
2) GPIO interface: the system is connected with a SelectMAP interface of the FPGA, is used for executing parallel loading and readback of the FPGA and is used for receiving a monitoring signal (single event upset signal) of the SEM module;
3) External storage access interface: the method is used for completing the moving of the FPGA configuration file and the read-back file;
(2) And (3) FPGA: the Xilinx company SRAM type FPGA chip supports SelectMAP parallel loading and SEM IP cores;
(3) RAM cache: and the main stream RAM such as DDR2, DDR3 and the like is used for storing FPGA configuration files and readback files.
As shown in fig. 2, the specific implementation of the technology is as follows:
(1) The system is powered on, the PowerPC starts working, initialization of each interface and read-write verification of the RAM are completed, and bit overturn is avoided;
(2) The PowerPC sends a request to the main control computer through a network interface, receives the FPGA configuration file and the readback file, caches the FPGA configuration file and the readback file in the RAM, then checks (generally performs check operation through check bits), and if the check is not passed, requests the main control computer to resend the configuration file and the readback file;
(3) According to the SelectMAP configuration time sequence requirement, the PowerPC configures a GPIO interface to load a configuration file into the FPGA;
(4) After loading is completed, a PowerPC is configured to read back a configuration memory in the FPGA (a configuration file is loaded into the configuration memory, so that reading back is carried out from the memory during reading back) according to the SelectMAP reading time sequence requirement, the configuration memory is compared with the reading back file in the RAM, if the configuration file is consistent with the reading back file, the loading is judged to be successful, and if the configuration file is inconsistent with the reading back file, the loading is reloaded;
(5) And after the loading is successful, starting an SEM module in the FPGA, monitoring the single event upset condition in real time, transmitting a monitoring signal to the PowerPC in real time through a GPIO interface, and if the monitoring signal is abnormal, considering that the single event upset occurs, and reloading.
One or more embodiments of the present invention may also be implemented by a computer of a system or apparatus that reads out and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a 'non-transitory computer-readable storage medium') to perform the functions of one or more of the above-described embodiments and/or that includes one or more circuits (e.g., application Specific Integrated Circuits (ASICs)) for performing the functions of one or more of the above-described embodiments, and a method of performing by a computer of a system or apparatus, e.g., by reading out and executing computer-executable instructions from a storage medium to perform the functions of one or more of the above-described embodiments and/or controlling one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may include one or more processors (e.g., a Central Processing Unit (CPU), a micro-processing unit (MPU)) and may include a separate computer or a network of separate processors to read out and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, a hard disk, random Access Memory (RAM), read Only Memory (ROM), storage for a distributed computing system, an optical disk (such as a Compact Disk (CD), digital Versatile Disk (DVD), or blu-ray disc (BD) TM ) One or more of a flash memory device, memory card, etc.
The embodiments of the present invention can also be realized by a method in which software (program) that performs the functions of the above embodiments is supplied to a system or apparatus, a computer of the system or apparatus or a method in which a Central Processing Unit (CPU), a Micro Processing Unit (MPU), or the like reads out and executes the program, through a network or various storage mediums.
While the invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
Claims (6)
1. The method is used for loading configuration files into the SRAM type FPGA, and is characterized by comprising the following steps:
transmitting the FPGA configuration file and the readback file from the main control computer to the PowerPC processor through a network interface of the PowerPC processor;
storing the FPGA configuration file and the readback file transmitted to the PowerPC processor into a RAM;
loading the configuration file into the SRAM type FPGA according to the SelectMAP parallel loading time sequence of the FPGA and returning read-back data; and
comparing the read-back data with the read-back file,
when the read-back data is consistent with the read-back file, monitoring a single event upset detection signal of the FPGA; and
reloading the configuration file when the read-back data is inconsistent with the read-back file;
wherein, the FPGA supports SelectMAP parallel loading and SEM IP core;
after the configuration file is loaded, according to a SelectMAP read-back time sequence of the FPGA, the PowerPC processor reads back a configuration memory in the FPGA through a GPIO interface, wherein the configuration file is stored in the configuration memory;
when the read-back data is consistent with the read-back file, an SEM module in the FPGA is started to monitor the single event upset condition in real time, a monitoring signal is transmitted to the PowerPC in real time through a GPIO interface, and if the monitoring signal is abnormal, the configuration file is reloaded.
2. The PowerPC control-based SRAM type FPGA reliable loading and error-proofing design method of claim 1, wherein the FPGA comprises an SEM module, and the SEM module monitors a single event upset condition in real time and generates the single event upset detection signal.
3. The PowerPC control-based SRAM-based FPGA reliable loading and error-proofing design method of claim 1, wherein the host computer stores and transmits configuration files for each FPGA.
4. The PowerPC control-based SRAM-based FPGA reliable loading and error-proofing design method of claim 1, wherein the RAM comprises DDR2, DDR3 and SDRAM and is connected to the PowerPC processor via a memory interface.
5. The PowerPC control-based SRAM-based FPGA reliable loading and error-proofing design method of claim 1, wherein the PowerPC processor is connected to the host computer via a network interface, and the network interface supports TCP/IP protocols.
6. The PowerPC control-based SRAM-based FPGA reliable loading and error-proofing design method of claim 1, wherein the PowerPC processor comprises a GPIO interface and the PowerPC processor loads a configuration file into the FPGA via the GPIO interface.
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| CN114035994B (en) * | 2021-11-17 | 2022-06-07 | 北京极光星通科技有限公司 | Data storage system, failure processing method, electronic device, and storage medium |
| CN115328401B (en) * | 2022-08-15 | 2024-02-13 | 西安大合智能科技有限公司 | High-speed data storage and readback system based on FPGA |
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