CN110457070B

CN110457070B - Verification method and device and related product

Info

Publication number: CN110457070B
Application number: CN201910759870.XA
Authority: CN
Inventors: 不公告发明人
Original assignee: Anhui Cambricon Information Technology Co Ltd
Current assignee: Anhui Cambricon Information Technology Co Ltd
Priority date: 2019-08-16
Filing date: 2019-08-16
Publication date: 2020-11-24
Anticipated expiration: 2039-08-16
Also published as: CN110457070A

Abstract

The present disclosure relates to a verification method and apparatus and related products. The product includes a control module, the control module including: the device comprises an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing the calculation instruction associated with the artificial neural network operation; the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions; the storage queue unit is configured to store an instruction queue, where the instruction queue includes: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue. Through the method, the efficiency of verifying the related products can be improved.

Description

Verification method and device and related product

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a verification method and apparatus, and a related product.

Background

With the development of computer technology, the related system design becomes more and more complex. When the instruction sequence is used for verifying the multi-core system, because the relation among the instructions is very complex, and there are instructions whose correctness cannot be detected in real time in the verification environment (the errors caused by the instructions may be spread in the instruction sequence), a verification person needs to spend a lot of time for analyzing and positioning the errors, so that the verification work is complex and time-consuming.

Disclosure of Invention

In view of the foregoing, it is desirable to provide an authentication method and apparatus capable of detecting an error in an authentication process as early as possible, and a related product.

According to an aspect of the present disclosure, there is provided an authentication method applied to a processor including a plurality of processing units, the method including: determining a plurality of synchronization domains of an instruction sequence according to a plurality of preset instruction synchronization points in the instruction sequence, wherein each instruction synchronization point is used for indicating a synchronization relation among a plurality of instructions executed by one or more processing units in the instruction sequence, and each synchronization domain is used for indicating an instruction subsequence between adjacent instruction synchronization points; executing, by one or more of the processing units, a sub-sequence of instructions of at least one set of synchronization domains of the plurality of synchronization domains to obtain a first execution result; when the first execution result has an error, determining erroneous first data in the first execution result and a first instruction having an operation on the first data; and according to the first data and the first instruction, executing processing corresponding to the error category of the first execution result so as to locate the instruction causing the error of the first execution result.

According to another aspect of the present disclosure, there is provided an authentication apparatus applied to a processor including a plurality of processing units, the apparatus including: the synchronous domain determining module is used for determining a plurality of synchronous domains of the instruction sequence according to a plurality of preset instruction synchronous points in the instruction sequence, wherein each instruction synchronous point is used for indicating a synchronous relation among a plurality of instructions executed by one or more processing units in the instruction sequence, and each synchronous domain is used for indicating an instruction subsequence between adjacent instruction synchronous points; the synchronous domain execution module is used for executing the instruction subsequences of at least one group of synchronous domains in the plurality of synchronous domains through one or more processing units to obtain a first execution result; the data and instruction determining module is used for determining first data with errors in the first execution result and a first instruction with operation on the first data when the first execution result has errors; and the error instruction determining module is used for executing processing corresponding to the error category of the first execution result according to the first data and the first instruction so as to locate the instruction causing the error of the first execution result.

According to another aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the memory-stored instructions to perform the above-described authentication method.

According to another aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described authentication method.

According to the embodiment of the disclosure, the instruction sequence is divided into a plurality of synchronization domains by setting the instruction synchronization point, when the execution result of the instruction subsequence of at least one group of synchronization domains is wrong, wrong data and an instruction with an operation on the data are determined, processing corresponding to the wrong category is executed according to the wrong data and the instruction with the operation on the data, and the instruction causing the error is positioned, so that system verification can be performed in stages, and the error in the verification process can be found as soon as possible.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of an application environment of an authentication method according to an embodiment of the present disclosure.

Fig. 2 shows a flow diagram of a verification method according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of a synchronization domain according to an embodiment of the present disclosure.

FIG. 4 shows a schematic diagram of dependencies, according to an embodiment of the present disclosure.

FIG. 5 illustrates a schematic diagram of a storage structure of possible parallel domains of a synchronization domain according to an embodiment of the disclosure.

FIG. 6 illustrates a schematic diagram of a first instruction dependency tree, according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of an application scenario of a verification method according to an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of an application scenario of a verification method according to an embodiment of the present disclosure.

Fig. 9 shows a block diagram of an authentication device according to an embodiment of the present disclosure.

FIG. 10 shows a block diagram of an electronic device in accordance with an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The verification method according to the embodiment of the present disclosure may be applied to a processor, which may be a general-purpose processor, such as a Central Processing Unit (CPU), or an artificial Intelligence Processor (IPU) for performing artificial intelligence operations. The artificial intelligence operation may include a machine learning operation or a brain-like operation, etc. The machine learning operation comprises neural network operation, k-means operation, support vector machine operation and the like. The artificial intelligence processor may include one or a combination of a GPU (Graphics Processing Unit), an NPU (Neural-Network Processing Unit), a DSP (Digital Signal Processing Unit), and a Field Programmable Gate Array (FPGA) chip. The present disclosure is not limited to a particular type of processor.

In one possible implementation, the processor referred to in this disclosure may include multiple processing units, each of which may independently run various tasks assigned thereto, such as: a convolution operation task, a pooling task, a full connection task, or the like. The present disclosure is not limited to processing units and tasks executed by processing units.

Fig. 1 shows a schematic diagram of an application environment of an authentication method according to an embodiment of the present disclosure. As shown in fig. 1, an application environment of the authentication method of the present disclosure includes an authentication environment 100 and a processor (DUT)200 as an object of authentication. The Verification environment 100 is used to provide a running and supporting environment required for Verification, such as a uvm (universal Verification method) Verification environment; the processor 200 may include a plurality of processing units 201 for executing sequences of instructions and a Memory unit 202 for storing data, which may include a Random Access Memory (RAM) and a register file. The plurality of processing units 201 in the processor 200 may share a part of the memory space, for example, share a part of the RAM memory space and the register file, and may simultaneously have respective memory spaces. Optionally, the processor to be verified may be an artificial intelligence chip or a board card, and the like, which is not specifically limited herein.

Fig. 2 shows a flow diagram of a verification method according to an embodiment of the present disclosure. As shown in fig. 2, the authentication method includes:

step S21, determining a plurality of synchronization fields of the instruction sequence according to a plurality of preset instruction synchronization points in the instruction sequence.

The instructions in the instruction sequence may include real-time detection instructions and non-real-time monitoring instructions. The real-time detection instruction refers to an instruction which can detect the correctness of an execution result in real time in the verification environment in the execution process, and the non-real-time detection instruction refers to an instruction which cannot detect the correctness of the execution result in real time in the verification environment in the execution process. For example, a control instruction (not outputting an execution result), an instruction that is difficult to obtain an execution result, or an instruction whose real-time verification increases complexity in the instruction sequence may be used as the non-real-time detection instruction.

Optionally, each instruction synchronization point may be used to indicate a synchronization relationship between a plurality of instructions in the sequence of instructions that are executed by one or more processing units. Optionally, the instruction synchronization point is used to indicate a synchronization relationship between multiple instructions executed by multiple processing units in the instruction sequence, and when one or more processing units of the processor execute multiple instructions, the processing unit that reaches the instruction synchronization point first suspends execution, and waits for other processing units controlled by the instruction synchronization point to reach the instruction synchronization point before continuing to execute the instructions. The instruction synchronization point may be an instruction or an operation, and the present disclosure does not limit the specific content of the instruction synchronization point.

Alternatively, the instruction synchronization point may also be used to indicate a synchronization relationship between multiple instructions executed by one processing unit in an instruction sequence, i.e. the instruction synchronization point may also be used to achieve synchronization between multiple instructions executed by a single processing unit. In this case, the processing unit of the processor may execute other instructions after the instruction before the instruction synchronization point is executed completely.

Optionally, a plurality of preset instruction synchronization points may be included in the instruction sequence. The instruction synchronization point can be set according to the synchronization point existing in the instruction sequence, and can also be set according to the verification requirement. For example, when the execution result of an instruction needs to be observed, the instruction may be set as an instruction synchronization point, the verification need may be combined with a synchronization point already existing in the instruction sequence to set the instruction synchronization point, or the instruction synchronization point may be set in another way. Alternatively, an initial point before the execution of the instruction sequence and an end point (end point) after the execution of all the instruction sequences may be also used as the instruction synchronization point. It should be understood that the present disclosure is not limited to the particular number and arrangement of instruction synchronization points.

In one possible implementation, the verification environment 100 may determine a plurality of synchronization fields of an instruction sequence according to a plurality of preset instruction synchronization points in the instruction sequence. Wherein each synchronization field is operable to indicate a sub-sequence of instructions between adjacent instruction synchronization points. That is, for a processing unit, the sub-sequence of instructions between two adjacent instruction synchronization points in a processing unit can be taken as a synchronization field. Alternatively, the verification environment may determine the start and end points of the synchronization domain as the lower and upper bounds, respectively, of the synchronization domain from which the subsequence of instructions for the synchronization domain may be determined.

Step S22, executing, by one or more of the processing units, the sub-sequence of instructions of at least one group of the plurality of synchronization domains to obtain a first execution result.

In one possible implementation, at least one set of synchronization domains may be determined based on at least one instruction synchronization point and a plurality of synchronization domains. Wherein a set of synchronization fields may include one or more synchronization fields controlled by the same instruction synchronization point. The present disclosure does not limit the number of synchronization domains included in a set of synchronization domains.

Further, the one or more processing units execute the sub-sequence of instructions of at least one group of the plurality of synchronization domains to obtain a first execution result. The first execution result may include an execution result of at least one instruction in the instruction sequence and data in at least one storage location (e.g., RAM and register file), such as a machine state snapshot. The present disclosure does not limit the specific content of the first execution result.

Step S23, when the first execution result has an error, determining the erroneous first data in the first execution result and the first instruction having an operation on the first data.

In a possible implementation manner, when the first execution result has an error, one or more first data having the error in the first execution result may be determined, and then, according to a storage address of the first data, a first instruction having an operation on the first data may be determined. The storage address of the first data may be a section of storage area or some registers in the RAM, and the first instruction operating on the first data may include an instruction in which the storage address of the operand of the first instruction is identical to the storage address of the first data, or an instruction in which the storage address of the operand of the first instruction partially overlaps with the storage address of the first data.

Step S24, according to the first data and the first instruction, executing a process corresponding to the error category of the first execution result to locate an instruction that causes an error in the first execution result.

Wherein the error category may be used to indicate a category to which an error occurring in the first execution result belongs, for example, depending on the nature of the error, the error category may include a software error (e.g., an error of an instruction, data, etc.) and a hardware error; depending on the source of the error information, the error categories may include errors reported by the verification environment and errors found at the instruction synchronization point. The error category can be set by those skilled in the art according to practical situations, and the disclosure does not limit this.

In a possible implementation manner, when the error categories of the first execution result are different, the corresponding processing methods may be different. The verification environment may determine an error category corresponding to the error of the first execution result based on the first data with the error and the first instruction operating on the first data, and then perform a process corresponding to the error category to locate the instruction causing the error of the first execution result. For example, when the error category of the first execution result is an error found by the instruction synchronization point, the synchronization domain where the instruction causing the error is located may be determined first, and then the instruction causing the first execution result error may be located according to the synchronization domain.

According to the embodiment of the disclosure, the instruction sequence is divided into a plurality of synchronization domains by setting the instruction synchronization point, when the execution result of the instruction subsequence of at least one group of synchronization domains is wrong, wrong data and an instruction with an operation on the data are determined, processing corresponding to the wrong category is executed according to the wrong data and the instruction with the operation on the data, and the instruction causing the error is positioned, so that system verification can be performed in stages, and the error in the verification process can be found as soon as possible. Moreover, according to the embodiment of the disclosure, the synchronization domain where the instruction causing the error is located can be located first when the error occurs, and then the instruction causing the error is determined according to the synchronization domain, so that the time consumed by locating the instruction causing the error is reduced, and the system verification efficiency is improved.

FIG. 3 shows a schematic diagram of a synchronization domain according to an embodiment of the present disclosure. As shown in fig. 3, there are 4 instruction sequences shown: instruction sequence 31, instruction sequence 32, instruction sequence 33 and instruction sequence 34. The four instruction sequences may include a plurality of instruction synchronization points: instruction synchronization point 35, instruction synchronization point 36, instruction synchronization point 37, and instruction synchronization point 38. Alternatively, the initial point of each instruction sequence and the end point (end point) after all the instruction sequences are executed are also used as the instruction synchronization points. The verification environment divides 4 instruction sequences into a plurality of synchronization domains according to adjacent synchronization points in the same instruction sequence, wherein the instruction sequence 31 is divided into a synchronization domain A1, a synchronization domain A2 and a synchronization domain A3, the instruction sequence 32 is divided into a synchronization domain B1, a synchronization domain B2, a synchronization domain B3 and a synchronization domain B4, the instruction sequence 33 is divided into a synchronization domain C1, a synchronization domain C2 and a synchronization domain C3, and the instruction sequence 34 is divided into a synchronization domain D1 and a synchronization domain D2.

After the synchronous domain is determined, the lower bound and the upper bound of the synchronous domain can be respectively determined according to the starting point and the ending point of the synchronous domain, and then the instruction subsequence of the synchronous domain is determined according to the lower bound and the upper bound of the synchronous domain. For example, the lower bound of synchronization field A2 is instruction synchronization point 35, the upper bound is instruction synchronization point 37, and the instruction subsequence of synchronization field A2 can be determined from instruction synchronization point 35 and instruction synchronization point 37.

In one possible implementation, a processor comprising 4 processing units, each executing a sequence of instructions, may be verified using 4 sequences of instructions as shown in fig. 3, the execution of the sequences of instructions of the different processing units being synchronized by 4 instruction synchronization points. Wherein each instruction synchronization point is operable to synchronize execution of instruction sequences of at least one processing unit. For example, the synchronization domains a1 and B1 are controlled by the instruction synchronization point 35, and when an instruction in the synchronization domain a1 reaches the instruction synchronization point 35 before an instruction in the synchronization domain B1, the synchronization domain a1 waits for the completion of the execution of an instruction in the synchronization domain B1 at the instruction synchronization point 35 after the completion of the execution of the instruction, whereas when an instruction in the synchronization domain B1 reaches the instruction synchronization point 35 before an instruction in the synchronization domain a1, the synchronization domain B1 waits for the completion of the execution of an instruction in the synchronization domain a1 at the instruction synchronization point 35 after the completion of the execution of the instruction. Similarly, the instruction synchronization point 36 may control synchronization domains C1 and D1, the instruction synchronization point 37 may control synchronization domains A2 and B2, and the instruction synchronization point 38 may control synchronization domains B3 and C2.

In one possible implementation, the synchronization fields in which the end points of the instruction subsequences in the plurality of synchronization fields are controlled by the same instruction synchronization point may be determined as a group of synchronization fields. As shown in FIG. 3, the synchronization fields A1 and B1 controlled by the command synchronization point 35 are a set of synchronization fields, the synchronization fields C1 and D1 controlled by the command synchronization point 36 are a set of synchronization fields, the synchronization fields A2 and B2 controlled by the command synchronization point 37 are a set of synchronization fields, the synchronization fields B3 and C2 controlled by the command synchronization point 38 are a set of synchronization fields, and the synchronization fields A3, B4, C3 and D2 controlled by the end points of all command sequences are a set of synchronization fields.

In one possible implementation, a set of synchronization fields may include multiple synchronization fields, i.e., an instruction synchronization point may control multiple adjacent or non-adjacent synchronization fields. While one instruction synchronization point in FIG. 3 may synchronize two synchronization fields of two instruction sequences, in other embodiments, one instruction synchronization point may also synchronize more than two synchronization fields of an instruction sequence. For example, the synchronization domains a1, B1, and C1 may be a set of synchronization domains, the synchronization domains A3, B3, C2, and D2 may also be a set of synchronization domains, and the synchronization domains a1, B1, and D1 in non-adjacent instruction sequences may also be a set of synchronization domains. The specific synchronization domain may be divided according to each instruction synchronization point, and is not limited herein.

In one possible implementation, step S22 may include: and executing the instruction subsequences of at least one group of the synchronous domains in the plurality of synchronous domains through one or more processing units according to the dependency relationship among the synchronous domains to obtain a first execution result.

The dependency relationship between the synchronization domains can be used to represent the correlation between the synchronization domains, and can include a sequential execution relationship and a parallel execution relationship. A plurality of synchronous domains with the dependency relationship of sequential execution need to be sequentially executed according to the sequence; multiple synchronization domains whose dependencies are in parallel execution relation may execute in parallel on different processing units. The present disclosure may refer to other synchronization domains that have a parallel execution relationship with one synchronization domain as the synchronization domain parallel domain.

In one possible implementation, the verification environment 100 may determine the dependency relationship between the synchronization domains, i.e., the execution order of the synchronization domains and the possible parallel domains of the synchronization domains, according to the instruction synchronization points and the synchronization domains. The verification environment may then determine at least one set of synchronization domains based on the dependencies between the synchronization domains.

Further, in determining the possible parallel domains of the synchronization domain, a linked list may be used to store the possible parallel domains of the synchronization domain, the head of the linked list being the synchronization domain, and the linked list may be referred to as the possible parallel domain linked list of the synchronization domain. The present disclosure may also use other ways to store the possible parallel domains of the synchronization domain, which the present disclosure does not limit. The present disclosure may increase the speed of finding parallel domains by storing possible parallel domains for the synchronization domain. Further, the present disclosure may obtain the first execution result by executing, by the one or more processing units, the sub-sequence of instructions of the at least one group of synchronization domains according to the dependency relationship between the synchronization domains.

In this embodiment, at least one group of synchronization domains can be determined among the plurality of synchronization domains according to the dependency relationship among the synchronization domains, and the first execution result is obtained after the execution by the processing unit, so that at least one group of synchronization domains can be determined and executed simply and accurately, and the efficiency of system verification is improved.

FIG. 4 shows a schematic diagram of dependencies, according to an embodiment of the present disclosure. As shown in fig. 4, the synchronization field indicated by the arrow is executed after the synchronization field indicated by the arrow tail. For example, synchronization domain B2 executes after synchronization domain A1 or synchronization domain B1, and synchronization domain A3 executes after synchronization domain A2 or synchronization domain B2.

Further, the present disclosure may determine the instruction dependency graph according to the division of the synchronization domains, and when a path exists between two synchronization domains, the synchronization domains on the path are in a sequential execution relationship. For example, there is a path from sync domain a1 to sync domain C3, and sync domains a1, B2, B3, and C3 on the path are in sequential execution relationship.

Further, when there is no path between two synchronization domains, which may be in a parallel execution relationship, one synchronization domain may be considered to be a parallel domain of the other synchronization domain. For example, if there is no path between sync domain A1 and sync domain C2, then sync domain A1 and sync domain C2 may be in a parallel execution relationship, sync domain C2 may be a parallel domain of sync domain A1, and sync domain A1 may also be a parallel domain of sync domain C2. FIG. 5 illustrates a schematic diagram of a storage structure of possible parallel domains of a synchronization domain according to an embodiment of the disclosure. The possible parallel domains of the synchronization domain are found according to the instruction dependency graph, as shown in fig. 5, the current synchronization domain is a1, and the possible parallel domains include synchronization domain B1, synchronization domain C1, synchronization domain C2, synchronization domain D1, and synchronization domain D2, that is, other synchronization domains in fig. 4 without a path to synchronization domain a 1.

Further, since the synchronization domain pointed by the arrow is executed after the synchronization domain pointed by the arrow tail, the synchronization domain pointed by the arrow tail pointing to the same synchronization domain can be determined as a set of synchronization domains according to the dependency graph shown in fig. 4, so as to determine at least one set of synchronization domains. For example, there are two arrows pointing to the synchronization domain C1, and the synchronization domains pointed by the arrow tails of the two arrows are the synchronization domains a1 and B1, respectively, so that the synchronization domains a1 and B1 can be determined as a set of synchronization domains. In the same way, it can be determined that the synchronization domains C1 and D1 are a set of synchronization domains and the synchronization domains A2 and B2 are a set of synchronization domains. A processor comprising 4 processing units may then be used to execute the sub-sequence of instructions of the two sets of synchronization domains (A1 and B1, C1 and D1) that may be executed in parallel, resulting in a first execution result.

In one possible implementation, step S24 may include:

judging whether a second instruction from a different synchronization domain than the first instruction exists in the first instruction dependency tree;

and when a second instruction from a different synchronization domain than the first instruction exists in the first instruction dependency tree, determining the second instruction and an instruction having data competition with the second instruction as a third instruction triggering an error.

The data contention can be used to indicate that a plurality of instructions operate on the same data address, and the operation of the plurality of instructions includes at least one write operation. Alternatively, the data race may include write after write operations, write after read operations, and read after write operations. For write-after-write operation, two instructions with data competition are located in the same node of the first instruction dependency tree; for a write-after-read or read-after-write operation, two instructions that have data contention are located in a set of parent-child nodes in the first instruction dependency tree, e.g., one instruction is located in a parent node and the other instruction is located in a child node of the parent node in the first instruction dependency tree.

In this embodiment, the first instruction dependency tree may include at least one instruction, where the at least one instruction may be an instruction from the current synchronization domain where the first instruction is located and/or a parallel domain of the current synchronization domain, and the determining of the parallel domain of the current synchronization domain may refer to the above, and the parallel domain of the current synchronization domain may be searched in the parallel domain linked list of the current synchronization domain. When it is determined that a second instruction from a different synchronization domain from the first instruction exists in the first instruction dependency tree, that is, when it is determined that a second instruction from a parallel domain of the synchronization domain where the first instruction is located exists in the first instruction dependency tree, it may be that a first execution result is wrong due to data contention among instructions between the parallel domains, so that the second instruction and the instruction having data contention with the second instruction may be determined as a third instruction that triggers a fault.

In one possible implementation, after determining the first data in the first execution result that is erroneous and the first instruction having an operation on the first data, the verification environment may establish a first instruction dependency tree based on the first data and the first instruction. Wherein the first instruction dependency tree describes the dependency relationship between the instructions related to the first data or the first instruction through a tree structure. There are various dependencies between instructions, for example, the result of an operation of one instruction is used as an operand of another instruction, or multiple instructions simultaneously write data with overlapping address ranges. The present disclosure does not limit dependencies between instructions.

In a possible implementation manner, the verification environment may trace back the instruction sequence upward from the data location where the first data is located according to the dependency relationship between the instructions, and establish the first instruction dependency tree. Optionally, the verification environment may establish a corresponding first instruction dependency tree for each first data. It should be understood that the present disclosure is not limited to the particular method of building the first instruction dependency tree, nor to the particular number of first instruction dependency trees.

Optionally, the establishing, by the verification environment, a first instruction dependency tree according to the first data and the first instruction may include: determining a root node of the first instruction dependency tree, wherein a storage address corresponding to the first data and a first instruction having an operation on the first data are stored in the root node; determining child nodes of the root node, wherein storage addresses corresponding to operands of the first instructions and instructions having operations on the operands are stored in the child nodes; and under the condition of meeting a preset condition, determining the first instruction dependency tree according to the root node and each child node.

In this implementation, when the first instruction dependency tree is established, a root node may be determined first, and a storage address corresponding to the first data and a first instruction having an operation on the first data may be stored in the root node, that is, the storage address corresponding to the first data and the first instruction having an operation on the first data are stored in the root node of the first instruction dependency tree. The storage address corresponding to the first data may be an address interval or a register number in the RAM; the first instruction that operates on the first data may be a value of a program counter (i.e., a PC value) corresponding to the first instruction. The PC value corresponding to each instruction is a value of a program counter corresponding to each instruction, and the program counter is used for storing and indicating an address of a next instruction to be executed.

After determining the root node, child nodes of the root node may be determined, and a storage address corresponding to an operand of the first instruction and an instruction having an operation on the operand may be stored in the child nodes of the root node, where each operand corresponds to one child node. One or more child nodes of a node may then be determined based on the rules that the data stored in the child nodes of the node includes a storage address corresponding to an operand of an instruction in the node and an instruction that operates on the operand. In this way, new child nodes can be continuously expanded. The storage manner of the data and the instructions in the child nodes is similar to that of the root node, and is not described herein again.

Under the condition that the preset condition is met, the child nodes can be stopped from being expanded, and the first instruction dependency tree is determined according to the root node and each child node. Wherein the preset condition may be used to indicate that the instruction in the newly-extended child node has been verified to be correct, for example, the preset condition may be that the instruction in the newly-extended child node is an instruction from a synchronization domain having a sequential execution relationship with a current synchronization domain. Since the synchronization domain executed before the current synchronization domain is verified to be correct at the instruction synchronization point, it can be considered that there is no instruction triggering an error, and therefore, when the preset condition is satisfied, the child node can stop being expanded. The preset conditions can be set by a person skilled in the art according to actual situations, and the present disclosure does not limit the specific contents of the preset conditions.

FIG. 6 illustrates a schematic diagram of a first instruction dependency tree, according to an embodiment of the present disclosure. As shown in fig. 6, stored in the root node 61 is the storage address (address range 1) corresponding to the first data and the PC value M of the first instruction M having an operation on the first data; the root node 61 has two child nodes of a node 62 and a node 63, the node 62 stores a storage address (register 1) corresponding to one operand of the first instruction M, a PC value N of the instruction N having an operation on the operand, and a PC value Q of the instruction Q, and the node 63 stores a storage address (address interval 2) corresponding to the other operand of the first instruction M, a PC value R of the instruction R having an operation on the operand, and a PC value S of the instruction S; the node 62 has two sub-nodes, a node 64 and a node 65, the node 64 stores a storage address (address interval 3) corresponding to one operand of the instruction N and/or the instruction Q and a PC value T of the instruction T and a PC value X of the instruction X, the node 65 stores a storage address (address interval 4) corresponding to the other operand of the instruction N and/or the instruction Q and a PC value Y of the instruction Y, the operand of which is operated; node 63 has a child of node 66, and stored in node 66 are the storage addresses (address range 5) corresponding to the operands of instruction R and/or instruction S, and the PC value Z of instruction Z, which operates on the operands.

In this embodiment, the root node and each child node of the first instruction dependency tree can be determined according to the first data and the first instruction, and when the preset condition is met, the first instruction dependency tree is established according to the root node and each child node, so that the established first instruction dependency tree can simply and accurately describe the dependency relationship between the instructions, and the search for the instruction with the triggering error is facilitated.

Further, the verification environment may determine whether a second instruction from a different synchronization domain than the first instruction exists in the first instruction dependency tree after the first instruction dependency tree is established to locate a third instruction that triggered the error. The synchronization domain where the first instruction is located can be used as the current synchronization domain, and whether a second instruction from a synchronization domain different from the first instruction exists in the first instruction dependency tree or not is judged according to the synchronization domain where the instruction in the first instruction dependency tree is located. When a second instruction from a different synchronization domain than the first instruction exists in the first instruction dependency tree, the error of the first execution result may be caused by data contention, so that the second instruction and the instruction having data contention with the second instruction may be determined as a third instruction triggering an error. The data hazards determined in this manner may include existing data hazards and/or data hazards that may exist, and due to the unpredictable nature of hardware behavior, finding existing data hazards and/or data hazards that may exist in the execution sequence may increase the efficiency of finding faulty instructions.

Still further, the verification environment may further determine that there is an instruction in the first instruction dependency tree that has data contention with a second instruction when there is a second instruction in the first instruction dependency tree from a different synchronization domain than the first instruction. The data contention can be used to indicate that a plurality of instructions operate on the same data address, and the operation of the plurality of instructions includes at least one write operation.

In a possible implementation manner, when determining an instruction having data contention with a second instruction, a data address of an operation of the second instruction may be determined first, and then, other instructions except the second instruction that operates on the data address in the first instruction dependency tree are determined, and operations of the other instructions and the second instruction include at least one write operation, and then, the determined other instructions are determined as instructions having data contention with the second instruction. Alternatively, when there are a plurality of second instructions from a different synchronization domain than the first instruction in the first instruction dependency tree, an instruction having data contention with each of the second instructions may be separately determined. Still further, the verification environment may determine the second instruction and the instruction having data contention with the second instruction as a third instruction that triggers the error when there is an instruction having data contention with the second instruction in the first instruction dependency tree.

For example, the present disclosure may establish a first instruction dependency tree based on the first data and the first instruction, determine that the current synchronization domain is synchronization domain A2, and determine whether there are second instructions from other synchronization domains in the first instruction dependency tree of synchronization domain A2. When a second instruction from another synchronization domain (e.g., synchronization domain B2) is present in the first instruction dependency tree, the second instruction and an instruction that has data contention with the second instruction may be determined to be a third instruction that triggered the error.

In this embodiment, a first instruction dependency tree can be established according to the first data and the first instruction, and whether a second instruction from another synchronization domain exists in the first instruction dependency tree is determined, and when the second instruction exists, the second instruction and an instruction having data contention with the second instruction are determined as a third instruction that triggers an error. In this way, the instructions with data contention in each synchronization domain can be determined, thereby reducing the overhead of data contention among lookup instructions.

In a possible implementation manner, the at least one group of synchronization domains includes a group of first synchronization domains and at least one group of second synchronization domains executed in parallel with the first synchronization domains, where step S24 may further include:

when a second instruction from a different synchronization domain than the first instruction does not exist in the first instruction dependency tree, judging whether the first data come from the second synchronization domain;

and when the first data are all from the second synchronous domain, executing the instruction subsequences of at least one group of synchronous domains of the next stage.

In one possible implementation, the at least one set of synchronization domains may include a set of first synchronization domains and at least one set of second synchronization domains that execute in parallel with the first synchronization domains. The first synchronization domain is a synchronization domain with the currently encountered instruction synchronization point as an upper bound.

For example, as shown in fig. 3, starting from the initial point of the instruction sequence, two sets of synchronization domains, namely synchronization domains a1 and B1, synchronization domains C1 and D1, can be executed, and the currently encountered instruction synchronization point is the instruction synchronization point 35, then the synchronization domains a1 and B1 bounded by the instruction synchronization point 35 are first synchronization domains, the synchronization domains C1 and D1 executed in parallel with the first synchronization domains are second synchronization domains, and at least one set of synchronization domains executed by the processing unit includes a set of first synchronization domains (a1 and B1) and a set of second synchronization domains (C1 and D1) executed in parallel with the first synchronization domains; when the execution of the sub-sequence of instructions in the synchronization domains a1 and B1 is completed, the instructions continue to be executed, and the currently encountered instruction synchronization point is the instruction synchronization point 36, then the synchronization domains C1 and D1 bounded by the instruction synchronization point 36 are the first synchronization domains, the synchronization domains a2 and B2 executed in parallel with the first synchronization domains are the second synchronization domains, and at least one set of synchronization domains executed by the processing unit includes a set of first synchronization domains (C1 and D1) and a set of second synchronization domains (a2 and B2) executed in parallel with the first synchronization domains.

Further, the verification environment may determine whether the first data all come from the second synchronization domain when a second instruction from a synchronization domain different from the first instruction does not exist in the first instruction dependency tree, that is, determine whether the synchronization domains where the first data is located are all the second synchronization domains. When the first data all come from the second synchronization domain, if each instruction in the second synchronization domain reads and writes data according to the specified address and the data is correct, the wrong first data can be considered to be caused by the fact that the execution progress of the second synchronization domain is inconsistent with the execution progress of the second synchronization domain in the reference model, no operation error exists, and the instruction subsequence of at least one group of synchronization domains at the next stage can be executed. If there is a possible operation error in the second synchronization domain, since the second synchronization domain is not executed completely, the execution can be continued to the instruction synchronization point of the upper bound of the second synchronization domain, and the possible operation error can be found by judging the data state of the instruction synchronization point, so in this case, the instruction subsequence of at least one group of synchronization domains of the next stage can be executed.

In this embodiment, when there is no second instruction from a different synchronization domain from the first instruction in the first instruction dependency tree, it is determined whether the erroneous first data all come from the second synchronization domain (i.e. the parallel domain of the first synchronization domain), and when the first data all come from the second synchronization domain, the instruction sub-sequence of at least one group of synchronization domains of the next stage is executed, so that the verification process may be continued when the execution progress of the second synchronization domain is inconsistent with the reference model or a possible operation error occurs in the second synchronization domain.

In a possible implementation manner, the at least one group of synchronization domains includes a group of first synchronization domains and at least one group of second synchronization domains executed in parallel with the first synchronization domains, the first execution result includes a machine state snapshot of an instruction synchronization point of the first synchronization domain, and the error category of the first execution result includes a state snapshot exception, the step S24 may include:

when the error type of the first execution result is abnormal state snapshot, judging whether the first data are from the second synchronization domain; and when the first data are all from the second synchronous domain, executing the instruction subsequences of at least one group of synchronous domains of the next stage.

In one possible implementation, the first execution result may include a machine state snapshot of an instruction synchronization point of the first synchronization domain. The machine state snapshot may be a file storing various values in storage units (such as a RAM and a register file) of the verification object (processor), and may be stored in a file directory according to a file organization manner of the verification object.

Optionally, the error category of the first execution result may include a state snapshot exception. The state snapshot exception may refer to a data difference between a machine state snapshot of the instruction synchronization point and a preset model state snapshot. The model state snapshot may refer to a machine state snapshot obtained by referring to a model to execute an instruction subsequence of at least one group of synchronization domains in the plurality of synchronization domains to an instruction synchronization point, and the model state snapshot may be stored in a file directory in the same file organization manner as the verification object. At an instruction synchronization point, the acquired machine state snapshot may be compared with the corresponding model state snapshot, and when there is a data difference between the two, the state snapshot may be considered abnormal.

In a possible implementation manner, when the error type of the first execution result is the state snapshot exception, it may be determined whether all the first data in the machine state snapshot that has errors are in the second synchronization domain. When the first data all come from the second synchronization domain, if each instruction in the second synchronization domain reads and writes data according to the specified address and the data is correct, it can be considered that the state snapshot exception is caused by the fact that the execution progress of the second synchronization domain in the verification object is inconsistent with the execution progress of the second synchronization domain in the reference model, no operation error exists, and the instruction subsequence of at least one group of synchronization domains at the next stage can be continuously executed. If there is a possible execution error in the second synchronization domain, the possible execution error may occur in the machine state snapshot of the instruction synchronization point of the second synchronization domain and be found by a comparison between the machine state snapshot and the model state snapshot because the second synchronization domain is not executing completely, and thus in this case, at least one group of instruction subsequences of the synchronization domain of the next stage may be executed.

For example, as shown in FIG. 3 for the synchronization domains, the at least one set of synchronization domains for which the verification object executes includes a set of first synchronization domains (synchronization domains A1 and B1) and a set of second synchronization domains (synchronization domains C1 and D1). When the system runs to the instruction synchronization point 35, the machine state snapshot of the instruction synchronization point 35 is compared with the corresponding model state snapshot to obtain a first execution result. When the state snapshot exception occurs in the first execution result, the erroneous first data in the first execution result and the first instruction having an operation on the first data may be determined, and it is determined whether the first data are both from the second synchronization domains C1 and D1. When the first data comes from the second synchronization domains C1 and D1, and the instructions in the second synchronization domains C1 and D1 read and write data according to the specified addresses, and the data is correct, it can be considered that the state snapshot exception is caused by the fact that the execution progress of the second synchronization domains C1 and D1 is inconsistent with the execution progress of the second synchronization domains in the reference model, there is no operation error, and the instruction subsequence of at least one group of synchronization domains at the next stage can be executed. Wherein the at least one set of synchronization domains of the next stage comprises first synchronization domains C1 and D1 bounded by the instruction synchronization point 36 and second synchronization domains A2 and B2 executing in parallel with the first synchronization domains.

In this embodiment, when the error type of the first execution result is the state snapshot exception and the first data is from the second synchronization domain, the instruction subsequence of the at least one group of synchronization domains at the next stage is executed, so that the verification process can be continuously executed when the state snapshot exception caused by inconsistency of the execution progress of the second synchronization domain occurs or there is a possible operation error in the second synchronization domain, thereby improving the efficiency of system verification.

In one possible implementation, step S24 may further include: when the first data do not all come from the second synchronous domain, determining a second instruction dependency tree according to the first data and the synchronous domain where the first instruction is located; and determining a third instruction triggering an error according to the second instruction dependency tree.

In this implementation, when the erroneous first data in the first execution result does not all come from the second synchronization domain, it may be considered that an instruction triggering an error exists in the first synchronization domain. In the first synchronization domain, whether the synchronization domains where the instructions in the first instruction dependency tree are located are the same as the synchronization domains where the first data and the first instructions are located may be determined according to the first data and the synchronization domains where the first instructions are located. When the synchronization fields of the two are the same, the first instruction dependency tree can be determined as a second instruction dependency tree in which a third instruction triggering an error is located.

Further, after the second instruction dependency tree is determined, a different instruction may be selected from the second instruction dependency tree as an ending instruction, and the verification process is repeatedly performed to determine a third instruction that triggers an error. For example, when determining that the error third instruction is triggered, any node may be selected from the second instruction dependency tree, one instruction in the node is used as an end instruction, the instruction subsequence is executed by one or more processing units from the lower bound of the current synchronization domain to obtain an execution result, and whether an error exists in the execution result is determined.

If no error exists in the execution result, the next instruction in the node can be used as an end instruction, and the process is repeatedly executed. When the execution results of all the instructions in the node as the ending instructions are correct, it may be considered that the subtree taking the node as the root does not include the third instruction triggering the error, and the subtree taking the node as the root is pruned. By pruning the subtree that does not contain the instruction that triggered the error from the first instruction dependency tree, the nodes of the first instruction dependency tree may be reduced, thereby narrowing the search range for finding the third instruction.

If the execution result has errors, the ending instruction is determined as the instruction with the wrong execution result, then the next instruction of the node can be selected as the ending instruction, and the above process is repeatedly executed. After the selected node is executed, one instruction in a child node or other nodes of the selected node can be selected as an ending instruction, and the process is repeatedly executed until all instructions with wrong execution results in the second instruction dependency tree are selected. Among the instructions with the wrong execution result, the instruction executed first (i.e., the instruction with the smallest PC value) is determined as the third instruction that triggers the error.

In a possible implementation manner, after the second instruction dependency tree is determined, whether an instruction with a trigger error exists in each node of the second instruction dependency tree can be judged through a probe mark and a probe instruction, when the instruction with the trigger error exists, all the instructions with the trigger error in the second instruction dependency tree are determined, and the instruction executed first in the instructions with the trigger error is determined to be a third instruction with the trigger error, wherein the probe instruction is an instruction capable of obtaining an execution result in real time.

For example, any node in the second instruction dependency tree may be selected, and the probe flag of the node is set as the instruction to be added into the probe; then adding a probe instruction behind each instruction of the node, and determining a plurality of instruction subsequences by taking the lower bound of the current synchronous domain as a starting point and the probe instruction as an end point; and executing the plurality of instruction subsequences through one or more processing units to obtain the execution result of the probe instruction corresponding to each instruction.

When the execution results of the probe instructions corresponding to the instructions are all correct, it can be considered that no instruction with a triggering error exists in the node, and the probe marks of all the child nodes of the node are set to be not required to be added with the probe instructions. And selecting other nodes without probe marks in the second instruction dependency tree, and repeatedly executing the process.

When the execution result of the probe instruction corresponding to each instruction has an error, the node is considered to have an instruction triggering the error, the instruction corresponding to the probe instruction with the wrong execution result is determined, and the probe instruction behind each instruction is cancelled. Then, the probe mark of the child node of the node or other nodes (selected nodes without probe marks when no child node exists) can be set as the instruction needing to add the probe, the above process is repeatedly executed, the instruction corresponding to the probe instruction with the wrong execution result is determined, until all nodes in the second instruction dependency tree are the nodes with the probe marks, and the above processing is performed on the nodes with the probe marks needing to add the probe instruction.

Among all the instructions corresponding to the probe instructions with the wrong execution result, the instruction executed first (i.e. the instruction with the smallest PC value) is determined as the third instruction triggering the error.

For example, the first instruction dependency tree shown in fig. 6 may be determined as a second instruction dependency tree, and when a third instruction triggering an error is determined according to the second instruction dependency tree, a probe instruction may be set as a probe instruction to be added from the root node 61, then the probe instruction may be added after the instruction M, and the probe instruction is set as an end point from the lower boundary of the synchronization domain where the instruction M is located, an instruction subsequence is determined, the instruction subsequence is executed by one or more processing units, an execution result is obtained, the execution result of the probe instruction corresponding to the instruction M is incorrect, then the probe instruction after the instruction M is cancelled, the probe instructions of two sub-nodes (sub-node 62 and sub-node 63) of the root node 61 are both set as probe instructions to be added, and the above processing (similar to the root node 61) is repeatedly executed, respectively obtaining the execution results of the probe instructions corresponding to the instruction N, the instruction Q, the instruction R and the instruction S, wherein the execution result of the probe instruction corresponding to the instruction N is wrong, the execution result of the probe instruction corresponding to other instructions is correct, the instruction with the triggering error does not exist in the child node 63, and the probe mark of the child node 66 is set to be not required to be added with the probe instruction; and considering that an instruction with a triggering error exists in the child node 62, setting the probe marks of the child node 64 and the child node 65 as probe instructions to be added, and repeatedly executing the processing to obtain the execution results of the probe instructions corresponding to the instruction T, the instruction X and the instruction Y respectively, wherein the execution result of the probe instruction corresponding to the instruction Y is wrong, and the execution result of the probe instruction corresponding to other instructions is correct. After marking and processing all nodes in the second instruction dependency tree are completed, an instruction (for example, instruction Y) with the smallest PC value can be selected from the instructions M, N, and Y corresponding to the probe instruction with the wrong execution result, and is used as a third instruction triggering the error.

It should be understood that, when marking and processing each node in the second instruction dependency tree, nodes may be selected sequentially from the root node, or may be selected as needed, and the present disclosure does not limit the selection of nodes. When the instruction to be executed first is selected from the instructions corresponding to the probe instruction with the wrong execution result, the selection may be performed while processing is performed in the node marking and processing process, or the selection may be performed after all the node marking and processing are completed.

In one possible implementation, before determining the third instruction triggering the error, the instructions in the second instruction dependency tree may be checked to delete the real-time detection instruction stored therein, because the real-time detection instruction executed before the error occurred in the first execution result is correct and verified. If all instructions in a node and its children are immediate-detect instructions, then the subtree rooted at the node may be pruned. By deleting real-time detected instructions in the second instruction dependency tree, instructions in the second instruction dependency tree may be reduced.

In this embodiment, when the first data does not all come from the second synchronization domain, the second instruction dependency tree can be determined according to the first data and the synchronization domain where the first instruction is located, and the instruction with the trigger error can be determined according to the second instruction dependency tree, so that the search range for searching the instruction with the trigger error can be reduced, and the efficiency for locating the instruction with the trigger error can be improved.

In a possible implementation manner, the error category of the first execution result includes an environmental error, and step S24 may further include:

when the instructions in a first instruction dependency tree all come from the same synchronization domain and the error category of the first execution result is an environmental error, determining the first instruction dependency tree as a second instruction dependency tree where a third instruction triggering an error is located; and determining a third instruction triggering an error according to the second instruction dependency tree.

In one possible implementation, the error category of the first execution result may include an environmental error. An environmental error refers to error information that verifies an environmental report during execution of the current at least one set of synchronization domains. That is, during the execution of the current at least one set of synchronization domains, when the execution result of one real-time detection instruction is wrong, the verification process may stop at the instruction, and the verification environment reports error information occurring during the execution of the instruction in real time, for example, the value (i.e., PC value) of the program counter of the real-time detection instruction, which reports the error information in real time, that is, the environmental error.

Optionally, when the instructions in the first instruction dependency tree all come from the same synchronization domain and the error category of the first execution result is an environmental error, it may be considered that the first instruction dependency tree includes a third instruction triggering an error, the first instruction dependency tree may be determined as a second instruction dependency tree where the third instruction triggering an error is located, and then the third instruction triggering an error is determined according to the second instruction dependency tree.

In this embodiment, when the instructions in the first instruction dependency tree all come from the same synchronization domain, and when the error type of the first execution result is an environmental error, the first instruction dependency tree is used to determine the second instruction dependency tree, and a third instruction which triggers the error is determined according to the second instruction dependency tree, so that when the environmental error occurs, the range where the instruction which triggers the error is located can be quickly determined, and the efficiency of positioning the instruction which triggers the error is improved.

Optionally, determining a third instruction triggering an error according to the second instruction dependency tree may include: taking the instructions in each node of the second instruction dependency tree as ending instructions respectively to obtain a plurality of instruction subsequences; executing each instruction subsequence by one or more processing units to obtain a second execution result; determining an end instruction corresponding to the second execution result as a fourth instruction when the second execution result has an error; and determining a fourth instruction executed firstly in each instruction subsequence as a third instruction. Further optionally, when there are multiple second instruction dependency trees in the current synchronization domain, one of the second instruction dependency trees may be arbitrarily selected, and then the third instruction that triggers the error may be determined according to the second instruction dependency tree.

In a possible implementation manner, the instructions in each node in the second instruction dependency tree may be respectively used as an end instruction to obtain a plurality of instruction subsequences, where the instruction subsequences may use a starting point of the instruction sequence or a lower bound of the current first synchronization domain (where an initial state of the processing unit at the lower bound needs to be restored using the machine state snapshot) as a starting point. The respective sub-sequences of instructions may then be executed by one or more processing units to obtain a second execution result.

In a possible implementation manner, after the second execution result is obtained, the machine state snapshot of the second execution result may be compared with the corresponding model state snapshot to determine whether the second execution result has an error. When the second execution result has an error, the ending instruction corresponding to the second execution result may be determined as a fourth instruction, and a fourth instruction executed first in each instruction subsequence, that is, a fourth instruction with a minimum PC value, may be determined as a third instruction that triggers the error.

For example, the first instruction dependency tree shown in fig. 6 may be determined as a second instruction dependency tree, and when determining a third instruction causing an error according to the second instruction dependency tree, each instruction (i.e., instruction M, instruction N, instruction Q, instruction R, instruction S, instruction T, instruction X, instruction Y, and instruction Z) in the second instruction dependency tree may be first used as an end instruction, and a last instruction synchronization point that is executed correctly is used as a starting point, so as to obtain a plurality of instruction subsequences; and then executing each instruction subsequence through one or more processing units to obtain a second execution result, judging whether the second execution result has errors, and when the second execution result has errors, determining an instruction corresponding to the second execution result as a fourth instruction, for example, determining an instruction with the second execution result error of the instruction subsequence of which the ending instruction is the instruction R, the instruction S and the instruction Z respectively, determining the instruction R, the instruction S and the instruction Z as the fourth instruction, and determining an instruction Z with the smallest PC value in the instruction R, the instruction S and the instruction Z as a third instruction triggering an error.

In this embodiment, the instruction in the second instruction dependency tree is used as the ending instruction, the execution subsequence of the first synchronization domain is executed again to obtain a second execution result, when the second execution result has an error, the ending instruction corresponding to the second execution result is used as a fourth instruction, and the fourth instruction executed first is determined as a third instruction. By setting different ending instructions and repeatedly executing the instruction subsequence of the first synchronous domain, a third instruction which triggers errors can be determined in a smaller instruction range (in the instruction subsequence of the first synchronous domain), and therefore the efficiency of positioning wrong instructions is improved.

In one possible implementation, when locating an instruction that triggers a fault, if only one instruction that triggers a fault is located, i.e., one fault is resolved at a time, a second instruction dependency tree may be analyzed using the above method to determine the instruction that triggers the fault. If a plurality of instructions triggering errors need to be positioned, that is, a plurality of errors are simultaneously solved, the method can be used for analyzing the plurality of second instruction dependency trees to determine a plurality of instructions triggering errors. The data of the second instruction dependency tree to be analyzed can be set by those skilled in the art according to actual needs, and the present disclosure does not limit this.

In one possible implementation, the method may further include: and when the first execution result is correct, executing the instruction subsequence of at least one group of synchronous domains of the next stage. That is, after dividing the instruction sequence into a plurality of synchronization domains by the instruction synchronization point, a plurality of sets of synchronization domains can be determined, and in the verification process, the instruction subsequences of at least one set of synchronization domains can be executed to obtain a first execution result. When the first execution result is correct, the instruction subsequences of at least one group of synchronous domains of the next stage can be executed until the instruction subsequences of all synchronous domains are executed completely.

In this embodiment, when the execution result of the instruction subsequence in the at least one group of synchronization domains is correct, the instruction subsequence in the at least one group of synchronization domains at the next stage is executed, so that the verification process can be performed in stages, errors in the verification process can be found as soon as possible, and the system verification efficiency is improved.

Fig. 7 shows a schematic diagram of an application scenario of a verification method according to an embodiment of the present disclosure. The authentication method is for authenticating a processor comprising a plurality of processing units.

As shown in fig. 7, when the processor is verified, a plurality of synchronization domains may be first determined according to instruction synchronization points preset in an instruction sequence in step S701, and then at step S702, at least one group of instruction subsequences of the synchronization domains in the plurality of synchronization domains is executed by one or more processing units to obtain a first execution result.

After obtaining the first execution result, in step S703, it may be determined whether the first execution result is correct. If the first execution result has an error, step S704 is executed to determine the erroneous first data in the first execution result and the first instruction having an operation on the first data, and establish a first instruction dependency tree according to the first data and the first instruction.

After the first instruction dependency tree is built, in step S705, it may be determined whether a second instruction from a different synchronization domain than the first instruction exists in the first instruction dependency tree. If the second instruction exists, executing step S709, determining that there is an instruction of data competition, and ending the verification; if not, step S706 is executed to determine whether the first data are all from a second synchronization domain executed in parallel with the first synchronization domain.

In step S705, if the second instruction does not exist, it is determined in step S706 whether the first data are all from a second synchronization domain that is executed in parallel with the first synchronization domain. If the first data are both from the second synchronization field, step S711 can be executed to execute at least one sub-sequence of instructions of the synchronization field of the next stage.

In step S706, if the first data does not all come from the second synchronization domain, in step S707, a second instruction dependency tree in which a third instruction with an error is triggered is determined according to the first data and the synchronization domain in which the first instruction is located, then in step S708, a third instruction with an error is determined according to the second instruction dependency tree, and this verification is ended.

In step 703, if the first execution result is correct, step S710 may be executed to determine whether the execution of the instruction sequence is completed, and if the execution of the instruction sequence is not completed, step S711 may be executed to execute the instruction subsequence of at least one group of synchronization fields of the next stage; if the execution of the sequence of instructions is complete, then the validation of the processor is complete.

Fig. 8 shows a schematic diagram of an application scenario of a verification method according to an embodiment of the present disclosure. As shown in fig. 8, when the verification method is applied in a UVM verification environment, the UVM verification environment 800 includes an analyzer 801, a reference model 802, a database 803, and a score board 804.

The analyzer 801 may include an instruction analyzer and a scheduling information analyzer. Wherein the instruction analyzer is operable to perform instruction analysis related processing, for example, dividing the instruction sequence into a plurality of synchronization fields according to a plurality of instruction synchronization points; establishing a first instruction dependency tree according to the first data and a first instruction having an operation on the first data; determining a second instruction dependency tree which meets the condition from the first instruction dependency tree; determining data contention between instructions, and determining an instruction that triggered an error based on a second instruction dependency tree, etc. The schedule information analyzer may be used to perform scheduling information related processing, such as analyzing the schedule information to generate a configuration file of the verification object or reference model.

The reference model 802 may be used to implement exactly the same design as the verification object. For example, the reference model may be implemented using C + + multithreading, each thread runs an instruction sequence of one processing unit, the threads may communicate with each other according to a shared array, the storage structure, access rights and verification objects of the reference model are completely consistent, and meanwhile, the reference model may schedule multithreading according to a configuration file to ensure that each thread runs the same instruction sequence as its corresponding processing unit, and the reference model may also start from a specific model state snapshot and repeat an instruction subsequence execution process after a specific instruction synchronization point. The present disclosure does not limit the specific implementation of the reference model.

Database 803 may be used to store machine state snapshots as well as model state snapshots. For example, the database may use a Git local file system that facilitates saving a tree directory structure, two branches may be established in the Git local file system to save the machine state snapshot and the model state snapshot, respectively, and a new snapshot newly generated at the same instruction synchronization point will update an old snapshot stored in the database. In addition, the Git local file system also provides a variety of operation commands to operate on data in the database, for example, a Git-commit command can be used to save historical data, a Git-checkout command can be used to obtain historical data, and a Git-diff command can be used to compare dissimilarities between the machine state snapshot and the model state snapshot. The present disclosure is not limited to a particular type of database.

The scoreboard 804 may be used to check the correctness of the real-time detection instruction execution result and to compare the machine state snapshot and the model state snapshot of the same instruction synchronization point. After the snapshot comparison is made, scoreboard 804 may also be used to determine whether to continue the verification process. When there is a data difference between the machine state snapshot and the model state snapshot, the scoring board 804 may send the RAM address interval and/or the register number where the data difference is located to the analyzer 801 for establishing the first instruction dependency tree. Scoreboard 804 may be constructed using conventional UVM scoreboards, and scoreboards constructed by this method may support the inspection process of UVM assertions. The present disclosure does not limit the specific implementation of the scoreboard.

According to the embodiment of the disclosure, the instruction synchronization point is set, so that the verification process can be performed in stages, and each stage executes the instruction subsequence of at least one group of synchronization domains, thereby being capable of finding errors in the verification process as early as possible (for example, detecting an environmental error caused by an instruction execution result error in real time, and a state snapshot anomaly in which a machine state snapshot and a model state snapshot of the instruction synchronization point have a data difference), further reducing time consumed by finding an error instruction, and improving system verification efficiency.

According to the embodiment of the disclosure, data competition among the instructions can be discovered as early as possible by judging the synchronization domain where the instructions in the first instruction dependency tree are located, and the situation that the data competition occurs in the execution of a lengthy instruction sequence is avoided.

According to the embodiment of the disclosure, the execution results of the real-time detection instruction and the non-real-time detection instruction in the instruction sequence can be found when the execution results are wrong. The execution result error of the real-time detection instruction in the instruction sequence can be found through an environmental error. For the error of the execution result of the non-real-time detection instruction in the instruction sequence, the method can be found by comparing the machine state snapshot with the model state snapshot at the upper boundary of the current synchronization domain (namely the currently encountered instruction synchronization point); and when the execution result of the real-time detection instruction with the dependency relationship is wrong, the error is reported through the environment, and under the condition, the instruction with the wrong triggering environment may not be the actual instruction with the wrong triggering, and an instruction dependency tree needs to be established for analysis to determine the instruction with the wrong triggering. In addition, if the real-time detection instruction with the dependency relationship is not encountered in the execution process of the non-real-time detection instruction and the instruction sequence is already executed, the execution result of the non-real-time detection instruction can be found to be wrong by comparing the machine state snapshot at the execution end point with the model state snapshot.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowcharts are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in each flowchart may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Fig. 9 shows a block diagram of an authentication device according to an embodiment of the present disclosure. The device is applied to a processor which comprises a plurality of processing units. As shown in fig. 9, the apparatus includes:

a synchronization domain determining module 91, configured to determine a plurality of synchronization domains of an instruction sequence according to a plurality of instruction synchronization points preset in the instruction sequence, where each instruction synchronization point is used to indicate a synchronization relationship between a plurality of instructions executed by one or more processing units in the instruction sequence, and each synchronization domain is used to indicate an instruction subsequence between adjacent instruction synchronization points;

a synchronization domain executing module 92, configured to execute, by one or more processing units, a sub-sequence of instructions of at least one group of synchronization domains in a plurality of synchronization domains to obtain a first execution result;

a data and instruction determining module 93, configured to determine, when the first execution result has an error, erroneous first data in the first execution result and a first instruction that operates on the first data;

an erroneous instruction determination module 94, configured to execute, according to the first data and the first instruction, processing corresponding to an erroneous category of the first execution result to locate an instruction that causes an error in the first execution result.

In one possible implementation, the synchronization domain executing module 92 includes: and the instruction sequence execution sub-module is used for executing the instruction sub-sequences of at least one group of synchronous domains in the plurality of synchronous domains through one or more processing units according to the dependency relationship among the synchronous domains to obtain a first execution result.

In one possible implementation, the erroneous instruction determination module 94 includes: the instruction judgment submodule is used for judging whether a second instruction from a different synchronization domain from the first instruction exists in the first instruction dependency tree or not; and the first error instruction determination submodule is used for determining a second instruction and an instruction having data competition with the second instruction as a third instruction triggering an error when the second instruction from a different synchronization domain exists in the first instruction dependency tree than the first instruction.

In a possible implementation manner, the at least one group of synchronization domains includes a group of first synchronization domains and at least one group of second synchronization domains executed in parallel with the first synchronization domains, where the faulty instruction determination module 94 further includes: a first synchronization domain judgment submodule, configured to judge whether the first data all come from the second synchronization domain when a second instruction that is from a different synchronization domain from the first instruction does not exist in the first instruction dependency tree; and the first execution submodule is used for executing the instruction subsequences of at least one group of synchronous domains of the next stage when the first data come from the second synchronous domain.

In one possible implementation manner, the at least one group of synchronization domains includes a group of first synchronization domains and at least one group of second synchronization domains executed in parallel with the first synchronization domains, the first execution result includes a machine state snapshot of an instruction synchronization point of the first synchronization domain, an error category of the first execution result includes a state snapshot exception, and the erroneous instruction determination module 94 includes: a second synchronization domain determining submodule, configured to determine whether the first data all come from the second synchronization domain when the error type of the first execution result is the state snapshot anomaly; and the second execution submodule is used for executing the instruction subsequence of at least one group of synchronous domains of the next stage when the first data are all from the second synchronous domain.

In a possible implementation manner, the erroneous instruction determination module 94 further includes: a first instruction dependency tree determining submodule, configured to determine a second instruction dependency tree according to the first data and the synchronization domain where the first instruction is located, when the first data does not all come from the second synchronization domain; and the second error instruction determination submodule is used for determining a third instruction triggering an error according to the second instruction dependency tree.

In a possible implementation manner, the error category of the first execution result includes an environmental error, and the error instruction determination module 94 further includes: the second instruction dependency tree determining submodule is used for determining the first instruction dependency tree as a second instruction dependency tree where a third instruction triggering an error is located when the instructions in the first instruction dependency tree all come from the same synchronization domain and the error category of the first execution result is an environment error; and the second error instruction determination submodule is used for determining a third instruction triggering an error according to the second instruction dependency tree.

In one possible implementation, the apparatus further includes: a root node determining module, configured to determine a root node of the first instruction dependency tree, where a storage address corresponding to the first data and a first instruction having an operation on the first data are stored in the root node; a child node determining module, configured to determine a child node of the root node, where a storage address corresponding to an operand of the first instruction and an instruction having an operation on the operand are stored in the child node; and the instruction dependency tree establishing module is used for determining the first instruction dependency tree according to the root node and each child node under the condition of meeting a preset condition.

In a possible implementation manner, the second faulty instruction determination submodule is configured to: taking the instructions in each node of the second instruction dependency tree as ending instructions respectively to obtain a plurality of instruction subsequences; executing each instruction subsequence by one or more processing units to obtain a second execution result; determining an end instruction corresponding to the second execution result as a fourth instruction when the second execution result has an error; and determining a fourth instruction executed firstly in each instruction subsequence as a third instruction.

In one possible implementation, the apparatus further includes: and the execution module is used for executing the instruction subsequence of at least one group of synchronous domains of the next stage when the first execution result is correct.

In a possible implementation manner, the state snapshot exception refers to a data difference between the machine state snapshot of the instruction synchronization point and a preset model state snapshot, and the environmental error refers to error information for verifying an environmental report during execution of the current at least one group of synchronization domains.

In one possible implementation, the apparatus is applied to a UVM verification environment.

It should be understood that the above-described apparatus embodiments are merely illustrative and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In one possible implementation, an electronic device is also disclosed, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the memory-stored instructions to perform the above-described authentication method.

In one possible implementation, a computer-readable storage medium is also disclosed, on which computer program instructions are stored, which when executed by a processor implement the above-described authentication method.

Fig. 10 shows a block diagram of an electronic device 1900 according to an embodiment of the disclosure. For example, the electronic device 1900 may be provided as a server. Referring to fig. 10, electronic device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1922 is configured to execute instructions to perform the above-described method.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output (I/O) interface 1958. The electronic device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1932, is also provided that includes computer program instructions executable by the processing component 1922 of the electronic device 1900 to perform the above-described methods.

In addition, unless otherwise specified, each functional unit/module in each embodiment of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. The artificial intelligence processor may be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, ASIC, etc., unless otherwise specified. Unless otherwise specified, the Memory unit may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1, a method of verification, the method being applied to a processor, the processor comprising a plurality of processing elements, the method comprising:

determining a plurality of synchronization domains of an instruction sequence according to a plurality of preset instruction synchronization points in the instruction sequence, wherein each instruction synchronization point is used for indicating a synchronization relation among a plurality of instructions executed by one or more processing units in the instruction sequence, and each synchronization domain is used for indicating an instruction subsequence between adjacent instruction synchronization points;

executing, by one or more of the processing units, a sub-sequence of instructions of at least one set of synchronization domains of the plurality of synchronization domains to obtain a first execution result;

when the first execution result has an error, determining erroneous first data in the first execution result and a first instruction having an operation on the first data;

and according to the first data and the first instruction, executing processing corresponding to the error category of the first execution result so as to locate the instruction causing the error of the first execution result.

Clause a2, the method of clause a1, wherein executing, by the one or more processing units, the subsequence of instructions of at least one set of synchronization domains of the plurality of synchronization domains resulting in a first execution result, comprises:

and executing the instruction subsequences of at least one group of the synchronous domains in the plurality of synchronous domains through one or more processing units according to the dependency relationship among the synchronous domains to obtain a first execution result.

Clause A3, the method of clause a1, performing, according to the first data and the first instruction, processing corresponding to an error category of the first execution result, comprising:

Clause A4, the method of clause A3, the at least one set of synchronization domains including a set of first synchronization domains and at least one set of second synchronization domains executing in parallel with the first synchronization domains,

wherein, according to the first data and the first instruction, executing processing corresponding to the error category of the first execution result, further comprises:

Clause a5, the method of clause a1, the at least one set of synchronization domains including a set of first synchronization domains and at least one set of second synchronization domains executing in parallel with the first synchronization domains, the first execution result including a machine state snapshot of an instruction synchronization point of the first synchronization domain, the error category of the first execution result including a state snapshot exception;

according to the first data and the first instruction, executing processing corresponding to the error category of the first execution result, including:

when the error type of the first execution result is abnormal state snapshot, judging whether the first data are from the second synchronization domain;

Clause a6, the method of clause a4 or a5, executing, according to the first data and the first instruction, processing corresponding to an error category of the first execution result, further comprising:

when the first data do not all come from the second synchronous domain, determining a second instruction dependency tree according to the first data and the synchronous domain where the first instruction is located;

and determining a third instruction triggering an error according to the second instruction dependency tree.

Clause a7, the method of clause A3, the error category of the first execution result comprising an environmental error;

executing processing corresponding to the error category of the first execution result according to the first data and the first instruction, further comprising:

when the instructions in a first instruction dependency tree all come from the same synchronization domain and the error category of the first execution result is an environmental error, determining the first instruction dependency tree as a second instruction dependency tree where a third instruction triggering an error is located;

Clause A8, the method of any one of clauses A3-a 7, further comprising:

determining a root node of the first instruction dependency tree, wherein a storage address corresponding to the first data and a first instruction having an operation on the first data are stored in the root node;

determining child nodes of the root node, wherein storage addresses corresponding to operands of the first instructions and instructions having operations on the operands are stored in the child nodes;

and under the condition of meeting a preset condition, determining the first instruction dependency tree according to the root node and each child node.

Clause a9, the method of clause a6 or a7, determining a third instruction that triggers an error according to the second instruction dependency tree, comprising:

taking the instructions in each node of the second instruction dependency tree as ending instructions respectively to obtain a plurality of instruction subsequences;

executing each instruction subsequence by one or more processing units to obtain a second execution result;

determining an end instruction corresponding to the second execution result as a fourth instruction when the second execution result has an error;

and determining a fourth instruction executed firstly in each instruction subsequence as a third instruction.

Clause a10, the method of any one of clauses a 1-a 9, further comprising:

and when the first execution result is correct, executing the instruction subsequence of at least one group of synchronous domains of the next stage.

Clause a11, the method according to clause a5 or a7, wherein the state snapshot exception is a data difference between the machine state snapshot of the instruction synchronization point and the preset model state snapshot, and the environmental error is an error message of verifying the environmental report during the execution of the current at least one set of synchronization domains.

Clause a12, a verification apparatus for use with a processor comprising a plurality of processing units, the apparatus comprising:

the synchronous domain determining module is used for determining a plurality of synchronous domains of the instruction sequence according to a plurality of preset instruction synchronous points in the instruction sequence, wherein each instruction synchronous point is used for indicating a synchronous relation among a plurality of instructions executed by one or more processing units in the instruction sequence, and each synchronous domain is used for indicating an instruction subsequence between adjacent instruction synchronous points;

the synchronous domain execution module is used for executing the instruction subsequences of at least one group of synchronous domains in the plurality of synchronous domains through one or more processing units to obtain a first execution result;

the data and instruction determining module is used for determining first data with errors in the first execution result and a first instruction with operation on the first data when the first execution result has errors;

and the error instruction determining module is used for executing processing corresponding to the error category of the first execution result according to the first data and the first instruction so as to locate the instruction causing the error of the first execution result.

Clause a13, the apparatus of clause a12, the synchronization domain executing module comprising:

and the instruction sequence execution sub-module is used for executing the instruction sub-sequences of at least one group of synchronous domains in the plurality of synchronous domains through one or more processing units according to the dependency relationship among the synchronous domains to obtain a first execution result.

Clause a14, the apparatus of clause a12, the error instruction determination module, comprising:

the instruction judgment submodule is used for judging whether a second instruction from a different synchronization domain from the first instruction exists in the first instruction dependency tree or not;

and the first error instruction determination submodule is used for determining a second instruction and an instruction having data competition with the second instruction as a third instruction triggering an error when the second instruction from a different synchronization domain exists in the first instruction dependency tree than the first instruction.

Clause A15, the apparatus of clause A14, the at least one set of synchronization domains including a set of first synchronization domains and at least one set of second synchronization domains executing in parallel with the first synchronization domains,

wherein, the error instruction determining module further comprises:

a first synchronization domain judgment submodule, configured to judge whether the first data all come from the second synchronization domain when a second instruction that is from a different synchronization domain from the first instruction does not exist in the first instruction dependency tree;

and the first execution submodule is used for executing the instruction subsequences of at least one group of synchronous domains of the next stage when the first data come from the second synchronous domain.

Clause a16, the apparatus of clause a12, the at least one set of synchronization domains including a set of first synchronization domains and at least one set of second synchronization domains executing in parallel with the first synchronization domains, the first execution result including a machine state snapshot of an instruction synchronization point of the first synchronization domain, the error category of the first execution result including a state snapshot exception,

the wrong instruction determination module comprises:

a second synchronization domain determining submodule, configured to determine whether the first data all come from the second synchronization domain when the error type of the first execution result is the state snapshot anomaly;

and the second execution submodule is used for executing the instruction subsequence of at least one group of synchronous domains of the next stage when the first data are all from the second synchronous domain.

Clause a17, the apparatus of clause a15 or a16, the fault command determination module, further comprising:

a first instruction dependency tree determining submodule, configured to determine a second instruction dependency tree according to the first data and the synchronization domain where the first instruction is located, when the first data does not all come from the second synchronization domain;

and the second error instruction determination submodule is used for determining a third instruction triggering an error according to the second instruction dependency tree.

Clause A18, the apparatus of clause A14, the error category of the first execution result comprising an environmental error,

the error instruction determination module further includes:

the second instruction dependency tree determining submodule is used for determining the first instruction dependency tree as a second instruction dependency tree where a third instruction triggering an error is located when the instructions in the first instruction dependency tree all come from the same synchronization domain and the error category of the first execution result is an environment error;

Clause a19, the apparatus of any one of clauses a 14-a 18, further comprising:

a root node determining module, configured to determine a root node of the first instruction dependency tree, where a storage address corresponding to the first data and a first instruction having an operation on the first data are stored in the root node;

a child node determining module, configured to determine a child node of the root node, where a storage address corresponding to an operand of the first instruction and an instruction having an operation on the operand are stored in the child node;

and the instruction dependency tree establishing module is used for determining the first instruction dependency tree according to the root node and each child node under the condition of meeting a preset condition.

Clause a20, the apparatus of clause a17 or a18, the second fault command determining submodule to:

Clause a21, the apparatus of any one of clauses a 12-a 20, further comprising:

and the execution module is used for executing the instruction subsequence of at least one group of synchronous domains of the next stage when the first execution result is correct.

Clause a22, the apparatus according to clause a16 or a18, wherein the state snapshot exception is a data difference between the machine state snapshot of the instruction synchronization point and the preset model state snapshot, and the environmental error is an error message of verifying the environmental report during the execution of the current at least one set of synchronization domains.

Clause a23, the apparatus according to any one of clauses a12 to a22, applied in a UVM verification environment.

Clause a24, an electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to invoke the memory-stored instructions to perform the method of any of clauses A1-A11.

Clause a25, a computer readable storage medium having computer program instructions stored thereon which, when executed by a processor, implement the method of any one of clauses a 1-a 11.

The embodiments of the present disclosure have been described in detail, and the principles and embodiments of the present disclosure are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present disclosure. Meanwhile, a person skilled in the art should, based on the idea of the present disclosure, change or modify the specific embodiments and application scope of the present disclosure. In view of the above, the description is not intended to limit the present disclosure.

Claims

1. An authentication method applied to a processor including a plurality of processing units, the method comprising:

executing processing corresponding to the error category of the first execution result according to the first data and the first instruction to locate an instruction causing an error in the first execution result,

wherein the set of synchronization fields includes one or more synchronization fields controlled by the same instruction synchronization point.

2. The method of claim 1, wherein executing, by one or more of the processing units, the sub-sequence of instructions for at least one of the plurality of synchronization domains to obtain the first execution result comprises:

3. The method according to claim 1, wherein executing, based on the first data and the first instruction, processing corresponding to an error category of the first execution result includes:

4. The method of claim 3, wherein the at least one set of synchronization domains comprises a set of first synchronization domains and at least one set of second synchronization domains that execute in parallel with the first synchronization domains,

5. The method of claim 1, wherein the at least one set of synchronization domains comprises a set of first synchronization domains and at least one set of second synchronization domains executed in parallel with the first synchronization domains, wherein the first execution result comprises a machine state snapshot of an instruction synchronization point of the first synchronization domain, and wherein the error category of the first execution result comprises a state snapshot exception;

6. The method according to claim 4, wherein executing processing corresponding to an error category of the first execution result according to the first data and the first instruction further comprises:

7. The method of claim 3, wherein the error category of the first execution result comprises an environmental error;

8. The method according to any one of claims 3 to 7, further comprising:

9. The method of claim 6 or 7, wherein determining a third instruction that triggers an error based on the second instruction dependency tree comprises:

10. The method of claim 1, further comprising:

11. The method according to claim 5 or 7, wherein the state snapshot exception is a data difference between the machine state snapshot of the instruction synchronization point and a preset model state snapshot, and the environmental error is an error message for verifying an environmental report during execution of the current at least one set of synchronization domains.

12. An authentication apparatus applied to a processor including a plurality of processing units, the apparatus comprising:

an erroneous instruction determination module for performing processing corresponding to an erroneous category of the first execution result based on the first data and the first instruction to locate an instruction that causes an error in the first execution result,

13. The apparatus of claim 12, wherein the apparatus is applied to a UVM verification environment.

14. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to invoke the memory-stored instructions to perform the method of any of claims 1 to 11.

15. A computer readable storage medium having computer program instructions stored thereon, which when executed by a processor implement the method of any one of claims 1 to 11.