CN110445364B - For a 1: soft start and drive circuit of 2-direction charge pump and realization method thereof - Google Patents

For a 1: soft start and drive circuit of 2-direction charge pump and realization method thereof Download PDF

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CN110445364B
CN110445364B CN201910855259.7A CN201910855259A CN110445364B CN 110445364 B CN110445364 B CN 110445364B CN 201910855259 A CN201910855259 A CN 201910855259A CN 110445364 B CN110445364 B CN 110445364B
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charge pump
nmos
tube
circuit
chip
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CN110445364A (en
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马俊
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Shanghai Southchip Semiconductor Technology Co Ltd
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Southchip Semiconductor Technology Shanghai Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

The invention discloses a method for 1:2 soft start and drive circuit of reverse charge pump and its implementation method, mainly solve the existing charge pump drive circuit and need connect QB tube in series to realize the soft start, both increased the chip cost, QB produced the extra heat loss while working normally at the same time, reduced the problem of the conversion efficiency of the voltage. The circuit comprises a divider resistor RF1, an MOS tube switch S and a clamp circuit A3 which are all connected with a VOUT pin of a charge pump chip, a clamp circuit A1 and a clamp circuit A2 which are all connected with a BT pin of the charge pump chip, and a passive current limiting circuit which is connected with an NMOS tube Q3 and an NMOS tube Q4 on the charge pump chip. The product of the current limiting values of the PMOS transistor Q3b and the NMOS transistor Q4 and (VIN-VOUT/2) is used as negative feedback quantity, and the negative feedback quantity and a reference P _ REF are integrated to control the current limiting values of the Q3b and the Q4, so that the current limiting values of the Q3b and the Q4 are ensured to be the maximum value under the premise that the heat loss of a chip is smaller than the P _ REF, namely the maximum load carrying capacity is achieved. Meanwhile, the chip cost is reduced, and the voltage conversion efficiency is improved.

Description

For a 1: soft start and drive circuit of 2-direction charge pump and realization method thereof
Technical Field
The present invention relates to an integrated circuit, and more particularly to a circuit for 1:2 soft start and drive circuit of reverse charge pump and its realization method.
Background
Charge pumps are switching converters that store energy using capacitors, wherein the capacitors are switched between a supply and a discharge state using switches, so that the supply voltage can be raised or lowered. In a mobile terminal or a portable electronic device, the voltage of the power supply may be lower than the operating voltage, and the charge pump may provide the voltage of the power supply to operate the system, for example, the voltage generated by the charge pump is in a range of 3.3V to 4.0V, so as to meet the operating requirement of the electronic device.
Most charge pump chips are applied at 2, which drops the input voltage to half: mode 1, there is little 1: mode 2. As shown in fig. 1, which is a schematic circuit diagram of the charge pump, four P transistors are divided into two phases ɸ 1 and ɸ 2, which are respectively turned on, and in an ideal case of no load, VX =2 × VY. The most common application is to use VX as the input power source, resulting in approximately half the output voltage VY. Similarly, if VY is used as the input power, then approximately twice the output voltage VX will be obtained.
The charge pump chip integrated with P-type transistor usually uses N-type MOS devices, which requires corresponding driving circuits. Since the charge pump does not have an energy storage device such as an inductor that limits current variation, a soft start process is required to limit the start-up current. For forward direction 2: the scheme of the 1 mode charge pump and the soft start is simple and mature. But for reverse 1: 2-mode charge pumps, this becomes very challenging since the input voltage is lower than the output voltage.
As shown in FIG. 2, the driving circuit of the charge pump in the prior art does not have the highest voltage point to supply power to the driving circuit of Q1/Q2/Q3, so Q1/2/3 cannot be turned on.
Most commonly, this is done by using additional sub-charge pumps to generate a maximum voltage (higher than 2 VIN + V _ overdrive, here 3 VIN) and then driving Q1/2/3 with this maximum voltage. To generate a level V _ overdrive higher than twice VIN, two sub charge pumps are required. Since the current for driving the Q1/2/3 is far less than the working current of the Q1/2/3, the area of the sub charge pump tube is far less than that of the P tube; however, driving the Q1/2/3 high-speed switch requires a current of mA level, so the capacitance of the sub charge pump is usually in nF level, and such large capacitance is difficult to integrate on chip, so an off-chip capacitance is required.
After the highest voltage is generated, the Q1/2/3 can be driven, and the power cannot be directly started. Because the on-resistance of Q1/2/3/4 is small (mohm level), the voltage difference between the initial VOUT level and the steady-state VOUT level is at most VIN +2 Vdiode. If Q1/2/3/4 is directly turned on hard, hundreds of amperes or even higher current is generated instantaneously, the chip is burnt out, and therefore a current-limiting soft start process is needed. In the soft starting process, the QB works in a saturation region through a feedback loop formed by an operational amplifier, and the maximum current in the starting process is limited, so that safe soft starting is realized. When VOUT level is close to twice VIN level, the drive level of QB is pulled to the maximum to make QB work in a linear region (minimum on-resistance), and the soft start is finished and normal work is started.
The traditional scheme has the advantages of intuition and common practice. Yet another benefit is that the scheme that produces the highest level from VIN is more efficient than the scheme that produces the highest level from VOUT, since twice the VIN current is equivalent to one time the VOUT current.
The disadvantages of the conventional solutions are also apparent. Firstly, the implementation of the circuit requires two extra capacitors and four chip pins, which is a great disadvantage for system application, especially for small-volume application scenarios such as mobile phones. Secondly, because the QB tube is required to be connected in series to realize soft start, the cost of the chip is increased, and meanwhile, extra heat loss is generated by the QB tube during normal work, so that the voltage conversion efficiency is reduced. If another MOS chip is used to reduce the on-resistance of QB, an extra two pins are required in addition to increasing the system cost. Finally, if VOUT is initially loaded, then an on-load soft start is required, resulting in a significant heat loss on QB. To ensure the safety of the QB, the current limit value is typically chosen to be a safe current at maximum differential pressure. However, as VOUT voltage rises, this current limit is too conservative, and the chip may have greater load capability.
Disclosure of Invention
The object of the invention is to provide a method for 1:2 soft start and drive circuit of reverse charge pump and its implementation method, mainly solve the existing charge pump drive circuit and need connect QB tube in series to realize the soft start, both increased the chip cost, QB produced the extra heat loss while working normally at the same time, reduced the problem of the conversion efficiency of the voltage.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a method for use in a 1: a soft start and drive circuit of a 2-inverter charge pump includes a voltage dividing resistor RF1, a MOS transistor switch S and a clamp circuit A3 all connected to a VOUT pin of a charge pump chip, a clamp circuit A1 and a clamp circuit A2 all connected to a BT pin of the charge pump chip, a subtracter SUB having a negative electrode connected to the voltage dividing resistor RF1, a multiplier MUL having a voltage input terminal connected to an output terminal of the subtracter SUB, an operational amplifier OP having an inverting input terminal connected to an output terminal of the multiplier MUL, a resistor RF2 connected to a negative electrode of the subtracter SUB, a clamp circuit A4 connected to an output terminal of the operational amplifier OP and the other end of the resistor RF2, a switch S1 connected between the clamp circuit A3 and a gate G of an NMOS transistor Q3 in the charge pump circuit, a switch S2 connected to the clamp circuit A4, a gate G and a drain D both connected to a switch S2 and a source S connected to a common terminal of the resistor RF2 and the clamp circuit A4, the passive current limiting circuit is connected with the drain electrode of an NMOS tube Q3 and the drain electrode of an NMOS tube Q4 on the charge pump chip, and the off-chip capacitor CBT is connected between the BT pin and the CFH pin of the charge pump chip; the MOS tube switch S is connected with a BT pin of the charge pump chip, the positive input end of the operational amplifier OP is connected with a reference voltage P _ REF, the positive electrode of the subtracter SUB is connected with a VIN pin of the charge pump chip, and the other ends of the clamping circuits A1, A2, A3 and A4 are respectively and correspondingly connected with grid electrodes G of NMOS tubes Q1, Q2, Q3 and Q4.
Further, the clamping circuit a1 includes an NMOS clamping tube Q _ clamp1 having a drain D connected to the BT pin of the charge pump chip, a parasitic diode D1 having a cathode connected to the gate G of the NMOS clamping tube Q _ clamp1, and an input buffer BUF1 having a positive phase input connected to the source S of the NMOS clamping tube Q _ clamp1 and a negative phase input connected to the anode of the diode D1; the output end of the input buffer BUF1 is connected with the gate G of the NMOS tube Q1 on the charge pump chip.
Furthermore, the circuit structures of the clamping circuit A2 and the clamping circuit A3 are the same as that of the clamping circuit A1; the output ends of the input buffers BUF2 and BUF3 are respectively connected with the gates G of NMOS transistors Q2 and Q3 on the charge pump chip.
Further, the clamp circuit a4 includes an NMOS clamp tube Q _ clamp4 having a drain D connected to the VIN pin of the charge pump chip, a parasitic diode D4 having a cathode connected to the gate G of the NMOS clamp tube Q _ clamp4, a current source Is1 and a switch S3 both connected to the source S of the NMOS clamp tube Q _ clamp4, and an input buffer BUF4 having a positive phase input connected to the other end of the switch S3 and a negative phase input connected to the positive electrode of the diode D4; the anode of the parasitic diode D4 Is connected to the common terminal of the resistor RF2 and the NMOS transistor Q, and the control terminal of the current source Is1 Is further connected to the output terminal of the operational amplifier OP and the input buffer BUF 4.
Further, the passive current limiting circuit comprises a PMOS transistor Q3b with a source S connected with a drain D of an NMOS transistor Q3 and a source S of an NMOS transistor Q2 of the charge pump chip, a PMOS transistor Q3c with a source S connected with a source S of a PMOS transistor Q3b and a gate G connected with a gate G of the PMOS transistor Q3b, an input buffer BUF5 with an output end connected with both the gate G and the drain D of a PMOS transistor Q3c, a current source Is2 with an input end connected with a negative phase input end of the input buffer BUF5, an NMOS clamp tube Q _ clamp5 with a source S connected with an output end of the current source Is2 and a drain D connected with a source S of the NMOS transistor Q, and a parasitic diode D5 with a negative electrode connected with a VIN pin of the charge pump chip and a positive electrode connected with a gate G of the NMOS clamp Q _ clamp 5; the source electrodes S of the PMOS tube Q3b and the PMOS tube Q3c are connected with the VIN pin of the charge pump chip, the drain electrode D of the PMOS tube Q3b Is connected with the CFL pin of the charge pump chip, and the control end of the current source Is2 Is also connected with the output end of the operational amplifier OP.
The present invention also provides a method for 1: 2-method for implementing soft start and drive circuit of reverse charge pump, using the above-mentioned method for 1:2 a soft start and drive circuit for an inverted charge pump comprising the steps of:
(1) NMOS transistors Q1, Q2 and Q3 are turned off all the time, so that a switch S2 is kept on, and switches S1 and S3 are kept off; the VIN power supply enables the NMOS transistor Q4 and the PMOS transistor Q3b to be normally driven;
(2) the body diodes of the NMOS transistors Q1 and Q2 are used for charging the CFLY/CBT capacitor, the voltage drop of the body diodes is subtracted to obtain the final steady-state voltage, and the PMOS transistor Q3b and the NMOS transistor Q4 work in a saturation region to limit the conduction current;
(3) the whole circuit enters a steady state, the drive circuits of the NMOS tubes Q1, Q2 and Q3 work normally, the NMOS tube Q1 and the NMOS tube Q2 are conducted normally, the NMOS tube Q3 is kept off, and the steady state is damaged;
(4) the PMOS tube Q3b and the NMOS tube Q4 keep current mirror current limiting, and the NMOS tubes Q1 and Q2 are respectively conducted and disconnected with the PMOS tube Q3b and the NMOS tube Q4 in the same phase;
(5) and the whole circuit enters a steady state again, the no-load steady-state values of VOUT voltage, CFLY capacitor voltage and CBT capacitor voltage are respectively 2 VIN, VIN and VIN, the soft start process is finished, and the charge pump chip is normally conducted in a reverse direction of 1: 2.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, the PMOS tube Q3b and the NMOS tube Q4 are used for current limiting as current mirrors, and no additional QB tube is required to be connected in series to realize soft start, so that the chip cost is reduced, the heat loss generated when the QB tube works is avoided, and the voltage conversion efficiency is improved.
(2) The product of the current limiting values of the PMOS transistor Q3b and the NMOS transistor Q4 and (VIN-VOUT/2) is used as negative feedback quantity, and the negative feedback quantity and a reference P _ REF are integrated to control the current limiting values of the Q3b and the Q4, so that the current limiting values of the Q3b and the Q4 are ensured to be the maximum value under the premise that the heat loss of a chip is smaller than the P _ REF, and the maximum load carrying capacity is realized.
Drawings
Fig. 1 is a circuit schematic of a charge pump.
Fig. 2 is a circuit schematic of a prior art charge pump drive circuit.
Fig. 3 is a schematic circuit diagram of the driving circuit of the present invention.
FIG. 4 is a schematic diagram of voltages at each main node of the driving circuit of the present invention during steady-state operation.
Fig. 5 is a schematic diagram of the loaded soft start process of the driving circuit of the present invention.
Detailed Description
The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.
Examples
As shown in fig. 3, the present invention discloses a method for 1: a soft start and drive circuit of a 2-phase charge pump includes a voltage dividing resistor RF1, a MOS transistor switch S and a clamp circuit A3 which are connected to a VOUT pin of a charge pump chip, a clamp circuit A1 and a clamp circuit A2 which are connected to a BT pin of the charge pump chip, a subtractor SUB whose negative electrode is connected to the voltage dividing resistor RF1, a multiplier MUL whose voltage input terminal is connected to an output terminal of the subtractor SUB, an operational amplifier OP whose inverting input terminal is connected to an output terminal of the multiplier MUL and whose output terminal is connected to an output terminal of the multiplier MUL, a resistor RF2 connected to a negative electrode of the subtractor SUB, a clamp circuit A4 which is connected to an output terminal of the operational amplifier OP1 and the other end of the resistor RF2, a switch S1 connected between the clamp circuit A3 and a gate G of an NMOS transistor Q3 in the charge pump circuit, a switch S2 connected to the clamp circuit A4, a gate G and a drain connected to a switch S2 and a source S3985 and a common terminal Q4 of the clamp circuit A3638, the passive current limiting circuit is connected with the drain electrode of an NMOS tube Q3 and the drain electrode of an NMOS tube Q4 on the charge pump chip, and the off-chip capacitor CBT is connected between the BT pin and the CFH pin of the charge pump chip; the MOS tube switch S is connected with a BT pin of the charge pump chip, the positive input end of the operational amplifier OP is connected with a reference voltage P _ REF, the positive electrode of the subtracter SUB is connected with a VIN pin of the charge pump chip, and the other ends of the clamping circuits A1, A2, A3 and A4 are respectively and correspondingly connected with grid electrodes G of NMOS tubes Q1, Q2, Q3 and Q4.
The clamping circuit A1 comprises an NMOS clamping tube Q _ clamp1 with a drain D connected with a BT pin of the charge pump chip, a parasitic diode D1 with a cathode connected with a grid G of the NMOS clamping tube Q _ clamp1, and an input buffer BUF1 with a positive phase input end connected with a source S of the NMOS clamping tube Q _ clamp1 and a negative phase input end connected with a positive electrode of a diode D1. The output end of the input buffer BUF1 is connected with the gate G of the NMOS tube Q1 on the charge pump chip. The clamp circuit a2, the clamp circuit A3 and the clamp circuit a1 have the same circuit configuration; the output terminals of the input buffers BUF2 and OP3 are respectively connected to the gates G of NMOS transistors Q2 and Q3 of the charge pump chip.
The clamp circuit A4 comprises an NMOS clamp tube Q _ clamp4 with a drain D connected with a VIN pin of the charge pump chip, a parasitic diode D4 with a negative electrode connected with a grid G of the NMOS clamp tube Q _ clamp4, a current source Is1 and a switch S3 which are both connected with a source S of the NMOS clamp tube Q _ clamp4, and an input buffer BUF4 with a positive phase input end connected with the other end of the switch S3 and a negative phase input end connected with the positive electrode of the diode D4; the anode of the parasitic diode D4 Is connected to the common terminal of the resistor RF2 and the NMOS transistor Q, and the control terminal of the current source Is1 Is further connected to the output terminal of the operational amplifier OP and the input buffer BUF 4.
The passive current limiting circuit comprises a PMOS tube Q3b, a source S of which Is connected with a drain D of an NMOS tube Q3 and a source S of an NMOS tube Q2 of the charge pump chip, a PMOS tube Q3c, a source S of which Is connected with a source S of the PMOS tube Q3b and a grid G of which Is connected with a grid G of a PMOS tube Q3b, an input buffer BUF5, an output end of which Is connected with the grid G and the drain D of the PMOS tube Q3c, a current source Is2, an input end of which Is connected with a negative phase input end of the input buffer BUF5, an NMOS clamp tube Q _ clamp5, a VIN diode D5, one end of which Is connected with a VIN pin of the charge pump chip and the other end of which Is connected with the grid G of the NMOS clamp tube Q _ clamp 5; the source electrodes S of the PMOS tube Q3b and the PMOS tube Q3c are connected with the VIN pin of the charge pump chip, the drain electrode D of the PMOS tube Q3b Is connected with the CFL pin of the charge pump chip, and the control end of the current source Is2 Is also connected with the output end of the operational amplifier OP.
In a steady state, the average voltage of the off-chip capacitor CBT is VOUT-VIN approximately equal to VIN, and the ripple of the BT node can be ignored as long as the capacitance value of the CBT is large enough. When the NMOS transistors Q2 and Q4 are conducted, the voltages of the capacitors CFH and CFL are VIN and GND respectively, and the voltage of the BT node is VOUT; NMOS transistors Q1, Q2 and Q3 can obtain enough high voltage from the BT node to drive a power tube, and the required clamping tube Q _ clamp is clamped if the voltage is too high; at the same time, the off-chip capacitance CBT supplements the charge in this phase. When the NMOS transistors Q1 and Q3 are conducted, the voltages of CFH and CFL are VOUT and VIN respectively, and the voltage of the BT node is pushed to 2-VOUT-VIN which is approximately equal to 3-VIN because the voltage of the off-chip CBT is kept unchanged; the NMOS transistors Q1, Q2 and Q3 can obtain enough high voltage from the BT node to drive the power transistor, and if the voltage is too high, the voltage is required to be clamped by a clamp pipe Q _ clamp; meanwhile, the off-chip capacitor CBT discharges charges when power is supplied to the NMOS transistors Q1, Q2 and Q3 driving circuit.
And, the circuit pump is divided into two stages during the soft start process. Initially, VOUT voltage is clamped by the body diodes of the NMOS transistors Q1 and Q2 at a voltage not lower than VIN-2 × Vdiode, the voltages at CFLY and CBT are uncertain, and the driving circuits of the NMOS transistors Q1, Q2, and Q3 cannot guarantee operation. Meanwhile, in the two phases of the soft start, S2 in fig. 3 remains on, and S1, S3 remain off.
As shown in fig. 4, in the first phase, the NMOS transistors Q1, Q2, Q3 are always turned off. Due to the VIN supply, the NMOS transistor Q4 and the PMOS transistor Q3b can be driven normally. And the PMOS transistor Q3b and the NMOS transistor Q4 are alternately switched on, and although the NMOS transistors Q1 and Q2 are switched off, the COUT, CFLY and CBT capacitors can be charged by using the body diodes, the voltage drop of the body diodes is subtracted from the final steady-state voltage, and the no-load steady-state values of the VOUT voltage, the CFLY capacitor voltage and the CBT capacitor voltage are 2 (VIN-V _ diode), VIN-Vdiode and VIN-2 Vdiode. It should be noted that this stage requires the PMOS transistor Q3b and the NMOS transistor Q4 to operate in the saturation region to limit the on-current. The current mirror current limiting is carried out on the PMOS tube Q3b and the NMOS tube Q4 through a passive current limiting circuit.
When the first phase enters a steady state, the driving circuits of the NMOS transistors Q1, Q2 and Q3 can work normally, and then the second phase is entered. In the second stage, the NMOS transistor Q3 is kept off, the PMOS transistor Q3b and the NMOS transistor Q4 keep the current-mirror current-limiting, and the NMOS transistors Q1 and Q2 are turned on and off in the same phase as the PMOS transistor Q3b and the NMOS transistor Q4, respectively. Since NMOS transistors Q1 and Q2 can be turned on normally, there is no longer a body diode drop. When the second stage enters a steady state, the no-load steady state values of VOUT voltage, CFLY capacitor voltage and CBT capacitor voltage are respectively 2 VIN, VIN and VIN, the soft start process is finished, and the chip can be normally conducted in a reverse 1:2 mode.
In addition, as shown in fig. 5, VOUT has a load during the start-up process, so that the charge pump needs to have a certain load carrying capability, and for this embodiment, the current limiting values of the PMOS transistor Q3b and the NMOS transistor Q4 are required to be greater than twice the load of VOUT:
Ilim_Q3b=Ilim_Q4>2*I_VOUT （1）
in practice, the current limiting values of the PMOS transistor Q3b and the NMOS transistor Q4 cannot be set too large, otherwise too much heat loss is generated on the chip, thereby triggering chip thermal protection and even burning out the chip. The heat loss can be calculated by the following formula:
Ploss=(2*VIN-VOUT)*IOUT （2）
using ambient temperature TambientThermal resistance R of the chipthermalTemperature T of the chipdieIt can be determined that:
Tdie=Tambient+Rthermal*Ploss（3）
the ambient temperature is usually fixed, and the maximum heat loss P can be determined by the maximum safe temperature allowed by the chiploss，PlossIs a fixed value. Therefore, as the VOUT voltage increases, the allowable IOUT may become larger. Therefore, the optimal current limiting values of the PMOS transistor Q3b and the NMOS transistor Q4 are:
Ilim_max=2*Ploss_max/(2*VIN-VOUT)=2*(Tdie_max-Tambient)/(Rthermal*(2*VIN-VOUT)) （4）
according to the invention, the PMOS tube Q3b and the NMOS tube Q4 are used for current limiting as current mirrors, and no additional QB tube is required to be connected in series to realize soft start, so that the chip cost is reduced, the heat loss generated when the QB tube works is avoided, and the voltage conversion efficiency is improved. Meanwhile, the product of the current limiting values of the PMOS tube Q3b and the NMOS tube Q4 and (VIN-VOUT/2) is used as negative feedback quantity, and the negative feedback quantity and a reference P _ REF are integrated to control the current limiting values of the Q3b and the Q4, so that the current limiting values of the Q3b and the Q4 are ensured to meet the maximum value on the premise that the heat loss of a chip is smaller than the P _ REF, and the maximum load carrying capacity is realized. Therefore, the method has high use value and popularization value.
The above-mentioned embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or changes made within the spirit and scope of the main design of the present invention, which still solve the technical problems consistent with the present invention, should be included in the scope of the present invention.

Claims (6)

1. A method for use in a 1: the soft starting and driving circuit of the 2-direction charge pump comprises a charge pump chip, four NMOS tubes Q1, Q2, Q3 and Q4 which are connected to the charge pump chip, and a capacitor CFLY; the source electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2, the source electrode of the NMOS tube Q2 is connected with the drain electrode of the NMOS tube Q3, the source electrode of the NMOS tube Q3 is connected with the drain electrode of the NMOS tube Q4, the drain electrode of the NMOS tube Q1 is connected with a VOUT pin of the charge pump chip, the drain electrode of the NMOS tube Q3 is also connected with a VIN pin of the charge pump chip, the drain electrode of the NMOS tube Q4 is also connected with a CFL pin of the charge pump chip, and a capacitor CFLY is connected between the CFH pin and the CFL pin of the charge pump chip; it is characterized by also comprising a divider resistor RF1, a MOS tube switch S and a clamp circuit A3 which are all connected with the VOUT pin of the charge pump chip, a clamp circuit A1, a clamp circuit A2, a subtracter SUB, the cathode of which is connected with the divider resistor RF1, a multiplier MUL, the output end of which is connected with the output end of the subtracter SUB, an operational amplifier OP, the inverting input end of which is connected with the output end of the multiplier MUL and the output end of which is connected with the output end of the multiplier MUL, a resistor RF2, the output end of which is connected with the cathode of the subtracter SUB, a clamp circuit A4, the output end of which is connected with the operational amplifier OP and the other end of which is connected with one end of a resistor RF2, a switch S1, one end of which is connected between the clamp circuit A3 and the grid of an NMOS tube Q3 in the charge pump circuit, a switch S2, the grid of which is connected with the other end of the grid and a source electrode D2, and a source electrode S is connected with the clamp circuit A85 A passive current limiting circuit connected with the drain of the NMOS tube Q3 and the drain of the NMOS tube Q4 on the charge pump chip, and an off-chip capacitor CBT connected between the BT pin and the CFH pin of the charge pump chip; the MOS tube switch S is connected with a BT pin of the charge pump chip, a positive input end of the operational amplifier OP is connected with a reference voltage P _ REF, a positive electrode of the subtracter SUB is connected with a VIN pin of the charge pump chip, and output ends of the clamping circuits A1, A2, A3 and A4 are respectively and correspondingly connected with grid electrodes G of NMOS tubes Q1, Q2, Q3 and Q4.
2. The method of claim 1 for use in a 1: the soft starting and driving circuit of the 2-direction charge pump is characterized in that the clamping circuit A1 comprises an NMOS clamping tube Q _ clamp1 with a drain D connected with a BT pin of a charge pump chip, a parasitic diode D1 with a negative pole connected with a grid G of the NMOS clamping tube Q _ clamp1, and an input buffer BUF1 with a positive phase input end connected with a source S of the NMOS clamping tube Q _ clamp1 and a negative phase input end connected with a positive pole of a diode D1; the output end of the input buffer BUF1 is connected with the gate G of the NMOS tube Q1 on the charge pump chip.
3. The method of claim 2 for use in 1:2, the soft starting and driving circuit of the reverse charge pump is characterized in that the circuit structures of the clamp circuit A2, the clamp circuit A3 and the clamp circuit A1 are the same; the output ends of the input buffers BUF2 and BUF3 are respectively connected with the gates G of NMOS transistors Q2 and Q3 on the charge pump chip.
4. The method of claim 3 for use in 1: the soft starting and driving circuit of the 2-direction charge pump Is characterized in that the clamping circuit A4 comprises an NMOS clamping tube Q _ clamp4, a parasitic diode D4, a current source IS1 and a switch S3, wherein the drain D of the NMOS clamping tube Q _ clamp4 Is connected with the VIN pin of a charge pump chip, the cathode of the parasitic diode D4 Is connected with the grid G of the NMOS clamping tube Q _ clamp4, the positive phase input end of the current source IS1 Is connected with the source S of the NMOS clamping tube Q _ clamp4, and the negative phase input end of the input buffer BUF2 Is connected with the other end of the switch S3 and the anode 4 of the diode D4; the anode of the parasitic diode D4 Is connected with the common end of the resistor RF2 and the NMOS tube Q, the control end of the current source Is1 Is also connected with the output end of the operational amplifier OP, and the output end of the current source Is1 Is connected with the input end of the input buffer BUF 4.
5. The method of claim 4 for use in 1: the soft starting and driving circuit of the 2-phase charge pump Is characterized in that the passive current limiting circuit comprises a PMOS pipe Q3b, a source S of which Is connected with a drain D of an NMOS pipe Q3 and a source S of an NMOS pipe Q2 of a charge pump chip, a PMOS pipe Q3c, a source S of which Is connected with the source S of the PMOS pipe Q3b and a grid G of which Is connected with a grid G of the PMOS pipe Q3b, an input buffer BUF5, an input end of which Is connected with the grid G and the drain D of the PMOS pipe Q3c, a current source IS2, a source S of which Is connected with the output end of the current source IS2 and a drain D of which Is connected with the source S of the NMOS pipe Q, an NMOS clamp pipe Q _ clamp5, and a parasitic diode D5, a cathode of which Is connected with a pin of the charge pump chip and a grid G of the NMOS clamp pipe Q _ clamp 5; the source electrodes S of the PMOS tube Q3b and the PMOS tube Q3c are connected with the VIN pin of the charge pump chip, the drain electrode D of the PMOS tube Q3b Is connected with the CFL pin of the charge pump chip, and the control end of the current source Is2 Is also connected with the output end of the operational amplifier OP.
6. A method for use in a 1: the implementation method of the soft starting and driving circuit of the reverse charge pump is characterized by comprising the following steps:
(1) NMOS transistors Q1, Q2 and Q3 are turned off all the time, so that a switch S2 is kept on, and switches S1 and S3 are kept off; the VIN power supply enables the NMOS transistor Q4 and the PMOS transistor Q3b to be normally driven;
(2) the body diodes of the NMOS transistors Q1 and Q2 are used for charging the CFLY/CBT capacitor, the voltage drop of the body diodes is subtracted to obtain the final steady-state voltage, and the PMOS transistor Q3b and the NMOS transistor Q4 work in a saturation region to limit the conduction current;
(3) the whole circuit enters a steady state, the drive circuits of the NMOS tubes Q1, Q2 and Q3 work normally, the NMOS tube Q1 and the NMOS tube Q2 are conducted normally, the NMOS tube Q3 is kept off, and the steady state is damaged;
(4) the PMOS tube Q3b and the NMOS tube Q4 keep current mirror current limiting, and the NMOS tubes Q1 and Q2 are respectively conducted and disconnected with the PMOS tube Q3b and the NMOS tube Q4 in the same phase;
(5) and the whole circuit enters a steady state again, the no-load steady-state values of VOUT voltage, CFLY capacitor voltage and CBT capacitor voltage are respectively 2 VIN, VIN and VIN, the soft start process is finished, and the charge pump chip is normally conducted in a reverse direction of 1: 2.
CN201910855259.7A 2019-09-11 2019-09-11 For a 1: soft start and drive circuit of 2-direction charge pump and realization method thereof Active CN110445364B (en)

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US10135432B2 (en) * 2016-09-07 2018-11-20 Texas Instruments Incorporated Methods and apparatus for low current control for a power connection
CN107147282A (en) * 2017-05-27 2017-09-08 普诚创智（成都）科技有限公司 A kind of efficient pair of capacitance charge pump

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