CN110429680A - The power supply circuit of double chargers - Google Patents
The power supply circuit of double chargers Download PDFInfo
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- CN110429680A CN110429680A CN201910739233.6A CN201910739233A CN110429680A CN 110429680 A CN110429680 A CN 110429680A CN 201910739233 A CN201910739233 A CN 201910739233A CN 110429680 A CN110429680 A CN 110429680A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The present invention provides a kind of power supply circuit of double chargers, including the first charging chip, the second charging chip, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first control module, the second control module and link block.The power supply circuit of double chargers provided by the invention, when not connecing charger and only connecing battery, i.e., the voltage of the voltage of the first charger and the second charger is 0, and system voltage comes from battery；When having connect the first charger and/or the second charger and connect battery simultaneously, the voltage of voltage and/or second charger of the system voltage from the first charger.In this way, two chargers for realizing different capacity work at the same time, two-way charger can be realized the function of quick charge, and cost is relatively low and charge efficiency is high for power supply circuit.
Description
[technical field]
The present invention relates to electronic equipment charging technique field more particularly to a kind of power supply circuits of double chargers.
[background technique]
Currently, there is usually one charge ports for electronic equipment such as laptop, it, can only if to realize quick charge
It is realized by way of improving charger power, improving charger power cost will increase, and lead to the function of entire power supply circuit
Consume larger and higher cost.Some electronic equipments include two charge ports, when two chargers access simultaneously, are only allowed
High-power charger is to system power supply and charges the battery, and the small charger operation of power, still cannot be real in light condition
Existing two chargers charge simultaneously, and charge efficiency is low.
In consideration of it, it is really necessary to provide a kind of power supply circuit of novel double chargers to overcome drawbacks described above.
[summary of the invention]
The object of the present invention is to provide a kind of power supply circuits of double chargers, can be realized two chargers of different capacity
It works at the same time, can be realized the function of quick charge, cost is relatively low and charge efficiency is high for power supply circuit.
To achieve the goals above, the present invention provides a kind of power supply circuit of double chargers, including the first charging chip,
Two charging chips, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first control module, the second control module
And link block；First charging chip includes first voltage input pin, first voltage output pin, first enabled draws
Foot, the first driving pin, the first current detecting anode pin and the first current detecting negative pin；The first voltage input is drawn
Foot connects the pole S of first metal-oxide-semiconductor, first driving for connecting the first charger, the first voltage output pin
Pin connects the pole G of first metal-oxide-semiconductor, and the first current detecting anode pin connects the pole D of first metal-oxide-semiconductor, institute
It states and is connected with first resistor between the first current detecting anode pin and the first current detecting negative pin, the first electric current inspection
Negative pin is surveyed to be also used to connect battery；The first voltage output pin is also connected with the pole D of the third metal-oxide-semiconductor, and described
The pole S of three metal-oxide-semiconductors connects first control module for connecting System on Chip/SoC, the pole G of the third metal-oxide-semiconductor；Described second
Charging chip includes second voltage input pin, second voltage output pin, the second enabled pin, the second driving pin, second
Current detecting anode pin and the second current detecting negative pin；The second voltage input pin is for connecting the second charging
Device, the second voltage output pin connect the pole S of second metal-oxide-semiconductor, and the second driving pin connects the 2nd MOS
The pole G of pipe, the second current detecting anode pin connect the pole D of second metal-oxide-semiconductor, and the second current detecting anode draws
Second resistance is connected between foot and the second current detecting negative pin, the second current detecting negative pin is also used to connect
The battery；The second voltage output pin is also connected with the pole D of the 4th metal-oxide-semiconductor, and the pole S of the 4th metal-oxide-semiconductor is used for
The System on Chip/SoC is connected, the pole G of the 4th metal-oxide-semiconductor connects second control module；First control module includes
First enable signal input terminal and the first enable signal output end, the first enable signal input terminal connection second charging
The enabled pin of the second of chip, the first enable signal output end connect the pole G of the third metal-oxide-semiconductor；Second control
Module includes the second enable signal input terminal and the second enable signal output end, described in the second enable signal input terminal connection
The enabled pin of the first of first charging chip, the second enable signal output end connect the pole G of the 4th metal-oxide-semiconductor；It is described
Link block includes the first control terminal, the second control terminal and third control terminal, and the first control terminal connection described first is enabled
Signal input part, second control terminal connect the second enable signal input terminal, and the third control terminal is for connecting EC
Chip.
In a preferred embodiment, first control module includes the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, third electricity
Resistance, the 4th resistance, the 5th resistance；Draw the first enable signal input terminal, the 5th MOS in the pole G of 5th metal-oxide-semiconductor
The pole S of pipe is grounded, and the pole D of the 5th metal-oxide-semiconductor connects the pole G of the 6th metal-oxide-semiconductor, and the pole S of the 6th metal-oxide-semiconductor is grounded,
Draw the first enable signal output end in the pole D of 6th metal-oxide-semiconductor；One end connection of the 3rd resistor first electricity
Output pin is pressed, the other end of the 3rd resistor connects the pole D of the 5th metal-oxide-semiconductor；One end of 4th resistance connects
The pole D of 5th metal-oxide-semiconductor, the other end ground connection of the 4th resistance；One end of 5th resistance connects the 6th MOS
The other end of the pole D of pipe, the 5th resistance connects the pole S of the third metal-oxide-semiconductor.
In a preferred embodiment, second control module includes the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 6th electricity
Resistance, the 7th resistance, the 8th resistance；Draw the second enable signal input terminal, the 7th MOS in the pole G of 7th metal-oxide-semiconductor
The pole S of pipe is grounded, and the pole D of the 7th metal-oxide-semiconductor connects the pole G of the 8th metal-oxide-semiconductor, and the pole S of the 8th metal-oxide-semiconductor is grounded,
Draw the second enable signal output end in the pole D of 8th metal-oxide-semiconductor；One end connection of 6th resistance second electricity
Output pin is pressed, the other end of the 6th resistance connects the pole D of the 7th metal-oxide-semiconductor；One end of 7th resistance connects
The pole D of 7th metal-oxide-semiconductor, the other end ground connection of the 7th resistance；One end of 8th resistance connects the 8th MOS
The other end of the pole D of pipe, the 8th resistance connects the pole S of the 4th metal-oxide-semiconductor.
In a preferred embodiment, the link block includes the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 9th resistance and the
Ten resistance；First control terminal is drawn in the pole D of 9th metal-oxide-semiconductor, and the pole S of the 9th metal-oxide-semiconductor is grounded, and the described 9th
The pole G of metal-oxide-semiconductor connects one end of the 9th resistance, and the other end of the 9th resistance connects the pole D of the tenth metal-oxide-semiconductor,
One end of tenth resistance connects the pole D of the tenth metal-oxide-semiconductor, and the other end of the tenth resistance draws second control
End, the pole the S ground connection of the tenth metal-oxide-semiconductor, the third control terminal is drawn in the pole G of the tenth metal-oxide-semiconductor.
In a preferred embodiment, the pole G of the third metal-oxide-semiconductor and S interpolar are also connected with first capacitor；Described
The pole G of four metal-oxide-semiconductors and S interpolar are also connected with the second capacitor.
In a preferred embodiment, the pole G of the 6th metal-oxide-semiconductor and S interpolar are also connected with third capacitor；Described
The pole G of eight metal-oxide-semiconductors and S interpolar are also connected with the 4th capacitor.
In a preferred embodiment, the first voltage input pin is also connected with the 5th capacitor, first electricity
Pressure output pin is also connected with the 6th capacitor；The second voltage input pin is also connected with the 7th capacitor, the second voltage
Output pin is also connected with the 8th capacitor.
In a preferred embodiment, it is connected with first diode between the pole D and the pole S of the third metal-oxide-semiconductor, it is described
The anode of first diode connects the pole D of the third metal-oxide-semiconductor, and the cathode of the first diode connects the third metal-oxide-semiconductor
The pole S；The second diode is connected between the pole D and the pole S of 4th metal-oxide-semiconductor, the anode of second diode connects institute
The pole D of the 4th metal-oxide-semiconductor is stated, the cathode of second diode connects the pole S of the 4th metal-oxide-semiconductor.
Compared with the prior art, the power supply circuit of double chargers provided by the invention only connects battery when not connecing charger
When, i.e., the voltage of the voltage of the first charger and the second charger is 0, and system voltage comes from battery；When having connect the first charger
And/or second charger and connect battery simultaneously, the electricity of voltage and/or second charger of the system voltage from the first charger
Pressure.In this way, two chargers for realizing different capacity work at the same time, two-way charger can be realized the function of quick charge,
Cost is relatively low and charge efficiency is high for power supply circuit.
For enable invention above objects, features, and advantages be clearer and more comprehensible, present pre-ferred embodiments are cited below particularly, and
Cooperate appended attached drawing, is described in detail below.
[Detailed description of the invention]
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the functional block diagram of the power supply circuit of double chargers provided by the invention；
Fig. 2 is the circuit diagram of the power supply circuit of double chargers shown in FIG. 1.
[specific embodiment]
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
Also referring to Fig. 1 and Fig. 2, Fig. 1 is the functional block diagram of the power supply circuit 100 of double chargers provided by the invention,
Fig. 2 is the circuit diagram of the power supply circuit 100 of double chargers shown in FIG. 1.The power supply circuit of double chargers provided by the invention
100, including the first charging chip U1, the second charging chip U2, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3,
Four metal-oxide-semiconductor Q4, the first control module 10, the second control module 20 and link block 30.
First charging chip U1 includes first voltage input pin VIN1, first voltage output pin VOUT1, first enabled
Pin EN1, the first driving pin BATDRV1, the first current detecting anode pin SRP1 and the first current detecting negative pin
SRN1；First voltage input pin VIN1 is for connecting the first charger 40, first voltage output pin VOUT1 connection first
The pole S of metal-oxide-semiconductor Q1, the pole G of first driving the first metal-oxide-semiconductor of pin BATDRV1 connection Q1, the first current detecting anode pin SRP1
The pole D of the first metal-oxide-semiconductor Q1 is connected, is connected between the first current detecting anode pin SRP1 and the first current detecting negative pin SRN1
It is connected to first resistor R1, the first current detecting negative pin SRN1 is also used to connect battery VBATT；First voltage output pin
VOUT1 is also connected with the pole D of third metal-oxide-semiconductor Q3, and the pole S of third metal-oxide-semiconductor Q3 is for connecting System on Chip/SoC 50, the G of third metal-oxide-semiconductor Q3
Pole connects the first control module 10.
Second charging chip U2 includes second voltage input pin VIN2, second voltage output pin VOUT2, second enabled
Pin EN2, the second driving pin BATDRV2, the second current detecting anode pin SRP2 and the second current detecting negative pin
SRN2；Second voltage input pin VIN2 is for connecting the second charger 60, second voltage output pin VOUT2 connection second
The pole S of metal-oxide-semiconductor Q2, the pole G of second driving the second metal-oxide-semiconductor of pin BATDRV2 connection Q2, the second current detecting anode pin SRP2
The pole D of the second metal-oxide-semiconductor Q2 is connected, is connected between the second current detecting anode pin SRP2 and the second current detecting negative pin SRN2
It is connected to second resistance R2, the second current detecting negative pin SRN2 is also used to connect the battery VBATT；Second voltage output is drawn
Foot VOUT2 is also connected with the pole D of the 4th metal-oxide-semiconductor Q4, and the pole S of the 4th metal-oxide-semiconductor Q4 is for connecting System on Chip/SoC 50, the 4th metal-oxide-semiconductor Q4
The pole G connect the second control module 20.
Specifically, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4 are p-type metal-oxide-semiconductor.
The size of first resistor R1 and second resistance R2 are 0.01 Ω.
First control module 10 includes the first enable signal input terminal ACOK1 and the first enable signal output terminals A COUT1,
The second enabled pin EN2 of first enable signal input terminal ACOK1 the second charging chip of connection U2, the first enable signal output end
The pole G of ACOUT1 connection third metal-oxide-semiconductor Q3.
Second control module 20 includes the second enable signal input terminal ACOK2 and the second enable signal output terminals A COUT2,
First enabled the second enable signal of pin EN1 output end of second enable signal input terminal ACOK2 the first charging chip of connection U1
The pole G of the 4th metal-oxide-semiconductor Q4 of ACOUT2 connection.
Link block 30 includes the first control terminal 31, the second control terminal 32 and third control terminal 33, and the first control terminal 31 connects
The first enable signal input terminal ACOK1 is met, the second control terminal 32 connects the second enable signal input terminal ACOK2, the third control
End processed is for connecting EC chip 70.
100 principle of power supply circuit of double chargers provided by the invention is as follows:
1, when first voltage input pin VIN1 is not connected with the first charger 40 and second voltage input pin VIN2 does not connect
When connecing the second charger 60, the first enabled enabled pin EN2 of pin EN1 and second is low level, the first driving pin
The driving of BATDRV1 and second pin BATDRV2 is low level, and the first metal-oxide-semiconductor Q1 conducting, first voltage VSYS1 is equal to battery
The voltage of VBATT, the second metal-oxide-semiconductor Q2 conducting, second voltage VSYS2 are equal to the voltage of battery VBATT；Also, EC chip 70 is controlled
The third control terminal 33 of link block 30 processed is low level, the first enable signal input terminal ACOK1 and the input of the second enable signal
End ACOK2 is low level, and the first control terminal 31 and the second control terminal 32 of link block 30 are low level, the first control module 10
The first enable signal output terminals A COUT1 be low level, i.e. the G of third metal-oxide-semiconductor Q3 extremely low level, third metal-oxide-semiconductor Q3 lead
Logical, the second enable signal output terminals A COUT2 of the second control module 20 is low level, the i.e. extremely low electricity of the G of the 4th metal-oxide-semiconductor Q4
It is flat, the 4th metal-oxide-semiconductor Q4 conducting.Therefore, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4 are led
It is logical, at this point, first voltage VSYS1, second voltage VSYS2 and system voltage VSYS are equal to the voltage of battery VBATT, by battery
VBATT is the power supply of System on Chip/SoC 50.
2, when the first charger of first voltage input pin VIN1 connection 40 and second voltage input pin VIN2 is not connected
When the second charger 60, the first enabled pin EN1 is high level, and the third control terminal 33 that EC chip 70 controls link block 30 is
Low level, three kinds of situations of this time-division:
Before (1) first charger 40 starts to charge, the first driving pin BATDRV1 is high level, and the first metal-oxide-semiconductor Q1 is closed
It is disconnected；Second driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；First enabled pin EN1 be high level, i.e., second
Enable signal input terminal ACOK2 is high level, and the second control terminal 32 of link block 30 is high level, the second control module 20
Second enable signal output terminals A COUT2 is high level, i.e. the G extremely high level of the 4th metal-oxide-semiconductor Q4, the 4th metal-oxide-semiconductor Q4 shutdown；
Second enabled pin EN2 is low level, i.e. the first enable signal input terminal ACOK1 is low level, the first control of link block 30
End 31 processed is low level, and the first enable signal output terminals A COUT1 of the first control module 10 is low level, i.e. third metal-oxide-semiconductor Q3
G extremely low level, third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 shutdown, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor
Q3 conducting and the 4th metal-oxide-semiconductor Q4 shutdown, at this point, second voltage VSYS2 be equal to battery VBATT voltage, first voltage VSYS1 with
System voltage VSYS is equal and is slightly larger than the voltage of battery VBATT, specifically, first voltage VSYS1 and system voltage VSYS ratio
The size of the voltage of battery VBATT big 160mV, 160mV are determined by the first charging chip U1.
After (2) first chargers 40 start to charge, the first driving pin BATDRV1 is low level, and the first metal-oxide-semiconductor Q1 is led
It is logical；Second driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；First enabled pin EN1 be high level, i.e., second
Enable signal input terminal ACOK2 is high level, and the second control terminal 32 of link block 30 is high level, the second control module 20
Second enable signal output terminals A COUT2 is high level, i.e. the G extremely high level of the 4th metal-oxide-semiconductor Q4, the 4th metal-oxide-semiconductor Q4 shutdown；
Second enabled pin EN2 is low level, i.e. the first enable signal input terminal ACOK1 is high level, the first control of link block 30
End 31 processed is low level, and the first enable signal output terminals A COUT1 of the first control module 10 is low level, i.e. third metal-oxide-semiconductor Q3
G extremely low level, third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 conducting, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor
Q3 conducting and the 4th metal-oxide-semiconductor Q4 shutdown, at this point, first voltage VSYS1, second voltage VSYS2 and system voltage VSYS are equal.
(3) after battery VBATT is full of, the first driving pin BATDRV1 is high level, the first metal-oxide-semiconductor Q1 shutdown；Second
Driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；First enabled pin EN1 is high level, i.e., the second enabled letter
Number input terminal ACOK2 is high level, and the second control terminal 32 of link block 30 is high level, and the second of the second control module 20 makes
Energy signal output end ACOUT2 is high level, i.e. the G extremely high level of the 4th metal-oxide-semiconductor Q4, the 4th metal-oxide-semiconductor Q4 shutdown；Second makes
Energy pin EN2 is low level, i.e. the first enable signal input terminal ACOK1 is high level, the first control terminal 31 of link block 30
For low level, the first enable signal output terminals A COUT1 of the first control module 10 is low level, the i.e. pole G of third metal-oxide-semiconductor Q3
For low level, third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 shutdown, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor Q3 conducting
And the 4th metal-oxide-semiconductor Q4 shutdown, at this point, second voltage VSYS2 be equal to battery VBATT voltage, first voltage VSYS1 and system electricity
It presses VSYS equal and is slightly larger than the voltage of battery VBATT, specifically, first voltage VSYS1 and system voltage VSYS compare battery
The big 160mV of the voltage of VBATT.
3, when first voltage input pin VIN1 is not connected with the first charger 40 and the VIN2 connection of second voltage input pin
When the second charger 60, the second enabled pin EN2 is high level, and the third control terminal 33 that EC chip 70 controls link block 30 is
Low level, three kinds of situations of this time-division:
Before (1) second charger 60 starts to charge, the second driving pin BATDRV2 is high level, and the second metal-oxide-semiconductor Q2 is closed
It is disconnected；First driving pin BATDRV1 is low level, the first metal-oxide-semiconductor Q1 conducting；Second enabled pin EN2 be high level, i.e., first
Enable signal input terminal ACOK1 is high level, and the first control terminal 31 of link block 30 is high level, the first control module 10
First enable signal output terminals A COUT1 is high level, the i.e. G of third metal-oxide-semiconductor Q3 extremely high level, third metal-oxide-semiconductor Q3 shutdown；
First enabled pin EN1 is low level, i.e. the second enable signal input terminal ACOK2 is low level, the second control of link block 30
End 32 processed is low level, and the second enable signal output terminals A COUT2 of the second control module 20 is low level, i.e. the 4th metal-oxide-semiconductor Q4
G extremely low level, the 4th metal-oxide-semiconductor Q4 conducting.Therefore, the first metal-oxide-semiconductor Q1 conducting, the second metal-oxide-semiconductor Q2 shutdown, third metal-oxide-semiconductor
Q3 shutdown and the 4th metal-oxide-semiconductor Q4 conducting, at this point, first voltage VSYS1 be equal to battery VBATT voltage, second voltage VSYS2 with
System voltage VSYS is equal and is slightly larger than the voltage of battery VBATT, specifically, second voltage VSYS2 and system voltage VSYS ratio
The big 160mV of the voltage of battery VBATT.
After (2) second chargers 60 start to charge, the second driving pin BATDRV2 is low level, and the second metal-oxide-semiconductor Q2 is led
It is logical；First driving pin BATDRV1 is low level, the first metal-oxide-semiconductor Q1 conducting；Second enabled pin EN2 be high level, i.e., first
Enable signal input terminal ACOK1 is high level, and the first control terminal 31 of link block 30 is high level, the first control module 10
First enable signal output terminals A COUT1 is high level, the i.e. G of third metal-oxide-semiconductor Q3 extremely high level, third metal-oxide-semiconductor Q3 shutdown；
First enabled pin EN1 is low level, i.e. the second enable signal input terminal ACOK2 is low level, the second control of link block 30
End 32 processed is low level, and the second enable signal output terminals A COUT2 of the second control module 20 is low level, i.e. the 4th metal-oxide-semiconductor Q4
G extremely low level, the 4th metal-oxide-semiconductor Q4 conducting.Therefore, the first metal-oxide-semiconductor Q1 conducting, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor
Q3 shutdown and the 4th metal-oxide-semiconductor Q4 conducting, at this point, first voltage VSYS1, second voltage VSYS2 and system voltage VSYS are equal.
(3) after battery VBATT is full of, the second driving pin BATDRV2 is high level, the second metal-oxide-semiconductor Q2 shutdown；First
Driving pin BATDRV1 is low level, the first metal-oxide-semiconductor Q1 conducting；Second enabled pin EN2 is high level, i.e., the first enabled letter
Number input terminal ACOK1 is high level, and the first control terminal 31 of link block 30 is high level, and the first of the first control module 10 makes
Energy signal output end ACOUT1 is high level, the i.e. G of third metal-oxide-semiconductor Q3 extremely high level, third metal-oxide-semiconductor Q3 shutdown；First makes
Energy pin EN1 is low level, i.e. the second enable signal input terminal ACOK2 is low level, the second control terminal 32 of link block 30
For low level, the second enable signal output terminals A COUT2 of the second control module 20 is low level, the i.e. pole G of the 4th metal-oxide-semiconductor Q4
For low level, the 4th metal-oxide-semiconductor Q4 conducting.Therefore, the first metal-oxide-semiconductor Q1 conducting, the second metal-oxide-semiconductor Q2 shutdown, third metal-oxide-semiconductor Q3 shutdown
And the 4th metal-oxide-semiconductor Q4 conducting, at this point, first voltage VSYS1 be equal to battery VBATT voltage, second voltage VSYS2 and system electricity
It presses VSYS equal and is slightly larger than the voltage of battery VBATT, specifically, second voltage VSYS2 and system voltage VSYS compare battery
The big 160mV of the voltage of VBATT.
4, when the first charger of first voltage input pin VIN1 connection 40 and second voltage input pin VIN2 connection
When two chargers 60, if the power P 1 of the first charger 40 is greater than or equal to the power P 2 of the second charger 60, EC chip 70 is controlled
The third control terminal 33 of link block 30 processed is low level (default), and system voltage VSYS is provided by first voltage VSYS1.If the
The power P 1 of one charger 40 is less than the power P 2 of the second charger 60, and EC chip 70 is by the third control terminal 33 of link block 30
Current potential draw high, system voltage VSYS is provided by second voltage VSYS2.
Specifically, when EC chip 70 detects that EC is filled according to the first charger 40 and second there are two when charger access
Charging current, the Icharge1=charging current* of two chargers is respectively configured in the power of electric appliance 60
P1/(P1+P2)；Icharge2=charging current*P2/ (P1+P2), wherein Icharge1 indicates the first charger
40 charging current, Icharge2 indicate 60 charging current of the second charger, and charging current indicates that battery VBATT permits
Perhaps maximum charging current.For example, when the first charger 40 is charging and the access of the second charger 60, if P1 > P2, third control
End 33 i.e. VSYS_SEL is low, the voltage of first voltage VSYS1 and system power supply VSYS equal to battery VBATT, second voltage
VSYS2 is 160mv higher than the voltage of battery VBATT, at this point, first voltage VSYS1 is supplied by third metal-oxide-semiconductor Q3 to System on Chip/SoC 50
Electricity；Also, second voltage VSYS2 powers possibly through Q4 power feeding system chip 50；When the second charger 60 starts to charge,
One voltage VSYS1 and system voltage VSYS are equal with second voltage VSYS2 voltage, if P1 < P2, VSYS_SEL are height, the first electricity
VSYS1 is pressed to be equal to the voltage of battery VBATT, second voltage VSYS2 and system voltage VSYS are higher than the voltage of battery VBATT
160mv, second voltage VSYS2 are powered by the 4th metal-oxide-semiconductor Q4 to System on Chip/SoC 50.
To sum up, the power supply circuit 100 of double chargers provided by the invention, there are two sources by system voltage VSYS, and one is
Battery VBATT, the other is the voltage VBUS2 of the voltage VBUS1 of the first charger 40 and/or the second charger 60.When not having
When connecing charger and only connecing battery, i.e. the voltage VBUS2 of the voltage VBUS1 of the first charger 40 and the second charger 60 is 0, system
Voltage VSYS comes from battery VBATT；When having connect the first charger 40 and/or the second charger 60 and met battery VBATT simultaneously,
The voltage VBUS2 of voltage VBUS1 and/or second charger 60 of the system voltage VSYS from the first charger 40.In this way, realizing
Two chargers of different capacity work at the same time, and two-way charger can be realized the function of quick charge, power supply circuit at
This is lower and charge efficiency is high.
Further, the first control module 10 includes the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6,3rd resistor R3, the 4th electricity
Hinder R4, the 5th resistance R5；The first enable signal input terminal ACOK1 is drawn in the pole G of 5th metal-oxide-semiconductor Q5, the 5th metal-oxide-semiconductor Q5's
The pole S ground connection, the pole D of the 5th metal-oxide-semiconductor Q5 connect the pole G of the 6th metal-oxide-semiconductor Q6, the pole the S ground connection of the 6th metal-oxide-semiconductor Q6, the 6th metal-oxide-semiconductor Q6
The pole D draw the first enable signal output terminals A COUT1；One end of 3rd resistor R3 connects first voltage output pin VOUT1,
The other end of 3rd resistor R3 connects the pole D of the 5th metal-oxide-semiconductor Q5；One end of 4th resistance R4 connects the pole D of the 5th metal-oxide-semiconductor Q5,
The other end of 4th resistance R4 is grounded；One end of 5th resistance R5 connects the pole D of the 6th metal-oxide-semiconductor Q6, and the 5th resistance R5's is another
The pole S of end connection third metal-oxide-semiconductor Q3.
Specifically, the 5th metal-oxide-semiconductor Q5 and the 6th metal-oxide-semiconductor Q6 is N-type metal-oxide-semiconductor；3rd resistor R3, the 4th resistance R4, the 5th
The size of resistance R5 respectively corresponds as 200k Ω, 100k Ω, 100k Ω.
Second control module 20 includes the 7th metal-oxide-semiconductor Q7, the 8th metal-oxide-semiconductor Q8, the 6th resistance R6, the 7th resistance R7, the 8th
Resistance R8；The pole S that the second enable signal input terminal ACOK2, the 7th metal-oxide-semiconductor Q7 is drawn in the pole G of 7th metal-oxide-semiconductor Q7 is grounded, and the 7th
The pole D of metal-oxide-semiconductor Q7 connects the pole G of the 8th metal-oxide-semiconductor Q8, and the pole the S ground connection of the 8th metal-oxide-semiconductor Q8, institute is drawn in the pole D of the 8th metal-oxide-semiconductor Q8
State the second enable signal output terminals A COUT2；One end of 6th resistance R6 connects second voltage output pin VOUT2, the 6th resistance
The other end of R6 connects the pole D of the 7th metal-oxide-semiconductor Q7；One end of 7th resistance Q7 connects the pole D of the 7th metal-oxide-semiconductor, the 7th resistance R7
The other end ground connection；One end of 8th resistance R8 connects the pole D of the 8th metal-oxide-semiconductor Q8, the other end connection the 4th of the 8th resistance R8
The pole S of metal-oxide-semiconductor Q4.
Specifically, the 7th metal-oxide-semiconductor Q7 and the 8th metal-oxide-semiconductor Q8 is N-type metal-oxide-semiconductor；6th resistance R6, the 7th resistance R7, the 8th
The size of resistance R8 respectively corresponds as 200k Ω, 100k Ω, 100k Ω.
Link block 30 includes the 9th metal-oxide-semiconductor Q9, the tenth metal-oxide-semiconductor Q10, the 9th resistance R9 and the tenth resistance R10；9th
First control terminal 31 is drawn in the pole D of metal-oxide-semiconductor Q9, the pole the S ground connection of the 9th metal-oxide-semiconductor Q9, the pole the G connection of the 9th metal-oxide-semiconductor Q9 the
One end of nine resistance R9, the other end of the 9th resistance R9 connect the pole D of the tenth metal-oxide-semiconductor Q10, one end connection of the tenth resistance R10
The other end of the pole D of tenth metal-oxide-semiconductor Q10, the tenth resistance R10 draws second control terminal 32, and the pole S of the tenth metal-oxide-semiconductor Q10 connects
Draw third control terminal 33 in the pole G on ground, the tenth metal-oxide-semiconductor Q10.
Specifically, the 9th metal-oxide-semiconductor Q9 and the tenth metal-oxide-semiconductor Q10 is N-type metal-oxide-semiconductor, the 9th resistance R9 is reserved resistance, can be with
The adjustment of resistance value is carried out according to actual needs, and the size of the tenth resistance R10 is 100k Ω.
In the following, right again in conjunction with the circuit element in the first control module 10, the second control module 20 and link block 30
100 principle of power supply circuit of double chargers provided by the invention is illustrated:
1, when first voltage input pin VIN1 is not connected with the first charger 40 and second voltage input pin VIN2 does not connect
When connecing the second charger 60, the first enabled enabled pin EN2 of pin EN1 and second is low level, the first driving pin
The driving of BATDRV1 and second pin BATDRV2 is low level, and the first metal-oxide-semiconductor Q1 conducting, first voltage VSYS1 is equal to battery
The voltage of VBATT, the second metal-oxide-semiconductor Q2 conducting, second voltage VSYS2 are equal to the voltage of battery VBATT；Also, EC chip 70 is controlled
The third control terminal 33 of link block 30 processed is low level, i.e. VSYS_SEL low level, and the tenth metal-oxide-semiconductor Q10 shutdown, second is enabled
Signal input part ACOK2 is low level, i.e. VSYS_SEL# is also low level, and the 7th metal-oxide-semiconductor Q7 is turned off, and second voltage VSYS2
Equal to the voltage of battery VBATT, the 6th resistance R6 and the 7th resistance R7 partial pressure, the high level on the 7th resistance R7 allow the 8th MOS
Pipe Q8 conducting, so that the current potential of the pole G of the 4th metal-oxide-semiconductor Q4 is lower than the pole S, the 4th metal-oxide-semiconductor Q4 conducting.Equally, VSYS_SEL# is low
Level, the 9th metal-oxide-semiconductor Q9 shutdown, the first enable signal input terminal ACOK1 are low level, and the 5th metal-oxide-semiconductor Q5 is turned off, and the first electricity
VSYS1 is pressed to be equal to the voltage of battery VBATT, 3rd resistor R3 and the 4th resistance R4 partial pressure, the high level on the 4th resistance R4 allows
6th metal-oxide-semiconductor Q6 conducting, so that the current potential of the pole G of third metal-oxide-semiconductor Q3 is lower than the pole S, third metal-oxide-semiconductor Q3 conducting.Therefore, first
Metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4 are both turned on, at this point, first voltage VSYS1, the second electricity
Pressure VSYS2 and system voltage VSYS is equal to the voltage of battery VBATT, is that System on Chip/SoC 50 is powered by battery VBATT.
2, when the first charger of first voltage input pin VIN1 connection 40 and second voltage input pin VIN2 is not connected
When the second charger 60, the first enabled pin EN1 is high level, and the third control terminal 33 that EC chip 70 controls link block 30 is
Low level, three kinds of situations of this time-division:
Before (1) first charger 40 starts to charge, the first driving pin BATDRV1 is high level, and the first metal-oxide-semiconductor Q1 is closed
It is disconnected；Second driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；The third control terminal 33 of link block 30 is low electricity
Flat, i.e., VSYS_SEL low level, the tenth metal-oxide-semiconductor Q10 are turned off, and the first enabled pin EN1 is high level, i.e. the second enable signal is defeated
Entering to hold ACOK2 is high level, and VSYS_SEL# is also high level, the 7th metal-oxide-semiconductor Q7 conducting, extremely 0 electricity of G of the 8th metal-oxide-semiconductor Q8
Position, the 8th metal-oxide-semiconductor Q8 shutdown, the pole G of the 4th metal-oxide-semiconductor Q4 is pulled upward to system voltage VSYS, the 4th metal-oxide-semiconductor Q4 by the 8th resistance R8
The pole G it is equal with S pole tension, the 4th metal-oxide-semiconductor Q4 shutdown；Second enabled pin EN2 is low level, i.e. the first enable signal input
End ACOK1 is low level, and VSYS_SEL# is high level, and the 9th metal-oxide-semiconductor Q9 is connected, the G of the 5th metal-oxide-semiconductor Q5 extremely 0 current potential, the
Five metal-oxide-semiconductor Q5 shutdown, first voltage VSYS1 is after 3rd resistor R3 and the 4th resistance R4 partial pressure, the both ends of the 4th resistance R4
For high level, i.e. the G extremely high level of the 6th metal-oxide-semiconductor Q6, the 6th metal-oxide-semiconductor Q6 conducting, i.e. extremely 0 electricity of the G of third metal-oxide-semiconductor Q3
Position, third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 shutdown, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor Q3 conducting and the 4th
Metal-oxide-semiconductor Q4 shutdown, at this point, second voltage VSYS2 is equal to the voltage of battery VBATT, first voltage VSYS1 and system voltage VSYS
Voltage that is equal and being slightly larger than battery VBATT, specifically, first voltage VSYS1 and electricity of the system voltage VSYS than battery VBATT
Big 160mV is pressed, the size of 160mV is determined by the first charging chip U1.
After (2) first chargers 40 start to charge, the first driving pin BATDRV1 is low level, and the first metal-oxide-semiconductor Q1 is led
It is logical；Second driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；The third control terminal 33 of link block 30 is low electricity
Flat, i.e., VSYS_SEL low level, the tenth metal-oxide-semiconductor Q10 are turned off, and the first enabled pin EN1 is high level, i.e. the second enable signal is defeated
Entering to hold ACOK2 is high level, and VSYS_SEL# is also high level, the 7th metal-oxide-semiconductor Q7 conducting, extremely 0 electricity of G of the 8th metal-oxide-semiconductor Q8
Position, the 8th metal-oxide-semiconductor Q8 shutdown, the pole G of the 4th metal-oxide-semiconductor Q4 is pulled upward to system voltage VSYS, the 4th metal-oxide-semiconductor Q4 by the 8th resistance R8
The pole G it is equal with S pole tension, the 4th metal-oxide-semiconductor Q4 shutdown；Second enabled pin EN2 is low level, i.e. the first enable signal input
End ACOK1 is low level, and VSYS_SEL# is high level, and the 9th metal-oxide-semiconductor Q9 is connected, the G of the 5th metal-oxide-semiconductor Q5 extremely 0 current potential, the
Five metal-oxide-semiconductor Q5 shutdown, first voltage VSYS1 is after 3rd resistor R3 and the 4th resistance R4 partial pressure, the both ends of the 4th resistance R4
For high level, i.e. the G extremely high level of the 6th metal-oxide-semiconductor Q6, the 6th metal-oxide-semiconductor Q6 conducting, i.e. extremely 0 electricity of the G of third metal-oxide-semiconductor Q3
Position, third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 conducting, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor Q3 conducting and the 4th
Metal-oxide-semiconductor Q4 shutdown, at this point, first voltage VSYS1, second voltage VSYS2 and system voltage VSYS are equal.
(3) after battery VBATT is full of, the first driving pin BATDRV1 is high level, the first metal-oxide-semiconductor Q1 shutdown；Second
Driving pin BATDRV2 is low level, the second metal-oxide-semiconductor Q2 conducting；The third control terminal 33 of link block 30 is low level, i.e.,
VSYS_SEL low level, the tenth metal-oxide-semiconductor Q10 shutdown, the first enabled pin EN1 are high level, i.e. the second enable signal input terminal
ACOK2 is high level, and VSYS_SEL# is also high level, and the 7th metal-oxide-semiconductor Q7 is connected, the G of the 8th metal-oxide-semiconductor Q8 extremely 0 current potential, the
Eight metal-oxide-semiconductor Q8 shutdown, the pole G of the 4th metal-oxide-semiconductor Q4 is pulled upward to system voltage VSYS, the pole G of the 4th metal-oxide-semiconductor Q4 by the 8th resistance R8
It is equal with S pole tension, the 4th metal-oxide-semiconductor Q4 shutdown；Second enabled pin EN2 is low level, i.e. the first enable signal input terminal
ACOK1 is low level, and VSYS_SEL# is high level, and the 9th metal-oxide-semiconductor Q9 is connected, the G of the 5th metal-oxide-semiconductor Q5 extremely 0 current potential, the 5th
Metal-oxide-semiconductor Q5 shutdown, after 3rd resistor R3 and the 4th resistance R4 partial pressure, the both ends of the 4th resistance R4 are first voltage VSYS1
High level, i.e. the G extremely high level of the 6th metal-oxide-semiconductor Q6, the 6th metal-oxide-semiconductor Q6 conducting, i.e. the G of third metal-oxide-semiconductor Q3 extremely 0 current potential,
Third metal-oxide-semiconductor Q3 conducting.Therefore, the first metal-oxide-semiconductor Q1 shutdown, the second metal-oxide-semiconductor Q2 conducting, third metal-oxide-semiconductor Q3 conducting and the 4th MOS
Pipe Q4 shutdown, at this point, second voltage VSYS2 is equal to the voltage of battery VBATT, first voltage VSYS1 and system voltage VSYS phase
Deng and be slightly larger than the voltage of battery VBATT, specifically, first voltage VSYS1 and voltage of the system voltage VSYS than battery VBATT
Big 160mV.
It is appreciated that being not connected with the first charger 40 and second voltage input pin in first voltage input pin VIN1
The case where VIN2 connection the second charger 60 and the first charger of first voltage input pin VIN1 connection 40 and second voltage is defeated
In the case where entering the second charger of pin VIN2 connection 60, the first control module 10, the second control module 20 and link block 30
Circuit element state change principle it is same as described above, details are not described herein again.
In present embodiment, the pole G of third metal-oxide-semiconductor Q3 and S interpolar are also connected with first capacitor C1, the G of the 4th metal-oxide-semiconductor Q4
The size that pole and S interpolar are also connected with the second capacitor C2, first capacitor C1 and the second capacitor C2 is 1000pF, first capacitor C1 and
Second capacitor C2 is used to filter out the signal interference at its both ends, stablizes the voltage at its both ends.The pole G of 6th metal-oxide-semiconductor Q6 and S interpolar are also
It is connected with third capacitor C3, the pole G of the 8th metal-oxide-semiconductor Q8 and S interpolar are also connected with the 4th capacitor C4, the electricity of third capacitor C3 and the 4th
The size for holding C4 is 0.1 μ F, third capacitor C3 and the 4th capacitor C4 for filtering out the signal interference at its both ends, stablizes its both ends
Voltage.
Specifically, first voltage input pin VIN1 is also connected with the 5th capacitor C5, first voltage output pin VOUT1 is also
The size for being connected with the 6th capacitor C6, the 5th capacitor C5 and the 6th capacitor C6 is respectively 0.47 μ F and 47 μ F, the 5th capacitor C5 and
6th capacitor C6 is respectively used to stablize the voltage of first voltage input pin VIN1 and first voltage output pin VOUT1.Second
Voltage input pin VIN2 is also connected with the 7th capacitor C7, and second voltage output pin VOUT2 is also connected with the 8th capacitor C8, the
The size of seven capacitor C7 and the 8th capacitor C8 is respectively 0.47 μ F and 47 μ F, and the 7th capacitor C7 and the 8th capacitor C8 are respectively used to surely
Determine the voltage of second voltage input pin VIN2 and second voltage output pin VOUT2.
In present embodiment, first diode D1, first diode D1 are connected between the pole D and the pole S of third metal-oxide-semiconductor Q3
Anode connection third metal-oxide-semiconductor Q3 the pole D, first diode D1 cathode connection third metal-oxide-semiconductor Q3 the pole S.4th metal-oxide-semiconductor Q4
The pole D and the pole S between be connected with the anode of the second diode D2, the second diode D2 and connect the pole D of the 4th metal-oxide-semiconductor Q4, the two or two
The cathode of pole pipe D2 connects the pole S of the 4th metal-oxide-semiconductor Q4.First diode D1 and the second diode D2 is respectively third metal-oxide-semiconductor Q3
And the 4th metal-oxide-semiconductor Q4 parasitic diode, it is parasitic specifically, in overtension for preventing overtension from burning out metal-oxide-semiconductor
Diode reverse breakdown draws high current to ground, so that metal-oxide-semiconductor be avoided to burn out.
The power supply circuit 100 of double chargers provided by the invention, when not connecing charger and only connecing battery, i.e., the first charging
The voltage VBUS2 of the voltage VBUS1 of device 40 and the second charger 60 is 0, and system voltage VSYS comes from battery VBATT；When connecing
First charger 40 and/or the second charger 60 and battery VBATT has been met simultaneously, system voltage VSYS comes from the first charger 40
Voltage VBUS1 and/or the second charger 60 voltage VBUS2.In this way, realizing two chargers while work of different capacity
Make, two-way charger can be realized the function of quick charge, and cost is relatively low and charge efficiency is high for power supply circuit.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (8)
1. a kind of power supply circuit of double chargers, which is characterized in that including the first charging chip, the second charging chip, the first MOS
Pipe, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first control module, the second control module and link block；
First charging chip includes first voltage input pin, first voltage output pin, the first enabled pin, the first drive
Dynamic pin, the first current detecting anode pin and the first current detecting negative pin；The first voltage input pin is for connecting
The first charger is connect, the first voltage output pin connects the pole S of first metal-oxide-semiconductor, the first driving pin connection
The pole G of first metal-oxide-semiconductor, the first current detecting anode pin connect the pole D of first metal-oxide-semiconductor, first electricity
Stream detects and is connected with first resistor between positive pin and the first current detecting negative pin, and the first current detecting cathode draws
Foot is also used to connect battery；The first voltage output pin is also connected with the pole D of the third metal-oxide-semiconductor, the third metal-oxide-semiconductor
The pole S connects first control module for connecting System on Chip/SoC, the pole G of the third metal-oxide-semiconductor；
Second charging chip includes second voltage input pin, second voltage output pin, the second enabled pin, the second drive
Dynamic pin, the second current detecting anode pin and the second current detecting negative pin；The second voltage input pin is for connecting
The second charger is connect, the second voltage output pin connects the pole S of second metal-oxide-semiconductor, the second driving pin connection
The pole G of second metal-oxide-semiconductor, the second current detecting anode pin connect the pole D of second metal-oxide-semiconductor, second electricity
Stream detects and is connected with second resistance between positive pin and the second current detecting negative pin, and the second current detecting cathode draws
Foot is also used to connect the battery；The second voltage output pin is also connected with the pole D of the 4th metal-oxide-semiconductor, the 4th MOS
The pole S of pipe connects second control module for connecting the System on Chip/SoC, the pole G of the 4th metal-oxide-semiconductor；
First control module includes the first enable signal input terminal and the first enable signal output end, the described first enabled letter
Number input terminal connects the second enabled pin of second charging chip, and the first enable signal output end connects the third
The pole G of metal-oxide-semiconductor；
Second control module includes the second enable signal input terminal and the second enable signal output end, the described second enabled letter
Number input terminal connects the first enabled pin of first charging chip, the second enable signal output end connection the described 4th
The pole G of metal-oxide-semiconductor；
The link block includes the first control terminal, the second control terminal and third control terminal, described in first control terminal connection
First enable signal input terminal, second control terminal connect the second enable signal input terminal, and the third control terminal is used
In connection EC chip.
2. the power supply circuit of double chargers as described in claim 1, which is characterized in that first control module includes the 5th
Metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, 3rd resistor, the 4th resistance, the 5th resistance；It is enabled that the pole G of 5th metal-oxide-semiconductor draws described first
Signal input part, the pole the S ground connection of the 5th metal-oxide-semiconductor, the pole D of the 5th metal-oxide-semiconductor connects the pole G of the 6th metal-oxide-semiconductor, institute
The pole the S ground connection of the 6th metal-oxide-semiconductor is stated, the first enable signal output end is drawn in the pole D of the 6th metal-oxide-semiconductor；The third electricity
One end of resistance connects the first voltage output pin, and the other end of the 3rd resistor connects the pole D of the 5th metal-oxide-semiconductor；
One end of 4th resistance connects the pole D of the 5th metal-oxide-semiconductor, the other end ground connection of the 4th resistance；5th electricity
One end of resistance connects the pole D of the 6th metal-oxide-semiconductor, and the other end of the 5th resistance connects the pole S of the third metal-oxide-semiconductor.
3. the power supply circuit of double chargers as claimed in claim 2, which is characterized in that second control module includes the 7th
Metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 6th resistance, the 7th resistance, the 8th resistance；It is enabled that the pole G of 7th metal-oxide-semiconductor draws described second
Signal input part, the pole the S ground connection of the 7th metal-oxide-semiconductor, the pole D of the 7th metal-oxide-semiconductor connects the pole G of the 8th metal-oxide-semiconductor, institute
The pole the S ground connection of the 8th metal-oxide-semiconductor is stated, the second enable signal output end is drawn in the pole D of the 8th metal-oxide-semiconductor；6th electricity
One end of resistance connects the second voltage output pin, and the other end of the 6th resistance connects the pole D of the 7th metal-oxide-semiconductor；
One end of 7th resistance connects the pole D of the 7th metal-oxide-semiconductor, the other end ground connection of the 7th resistance；8th electricity
One end of resistance connects the pole D of the 8th metal-oxide-semiconductor, and the other end of the 8th resistance connects the pole S of the 4th metal-oxide-semiconductor.
4. the power supply circuit of double chargers as claimed in claim 3, which is characterized in that the link block includes the 9th MOS
Pipe, the tenth metal-oxide-semiconductor, the 9th resistance and the tenth resistance；The pole D extraction first control terminal of 9th metal-oxide-semiconductor, the described 9th
The pole S of metal-oxide-semiconductor is grounded, and the pole G of the 9th metal-oxide-semiconductor connects one end of the 9th resistance, the other end of the 9th resistance
The pole D of the tenth metal-oxide-semiconductor is connected, one end of the tenth resistance connects the pole D of the tenth metal-oxide-semiconductor, the tenth resistance
The other end draw second control terminal, the pole the S ground connection of the tenth metal-oxide-semiconductor, described in the pole G of the tenth metal-oxide-semiconductor is drawn
Third control terminal.
5. the power supply circuit of double chargers as claimed in claim 4, which is characterized in that the pole G and the pole S of the third metal-oxide-semiconductor
Between be also connected with first capacitor；The pole G of 4th metal-oxide-semiconductor and S interpolar are also connected with the second capacitor.
6. the power supply circuit of double chargers as claimed in claim 5, which is characterized in that the pole G and the pole S of the 6th metal-oxide-semiconductor
Between be also connected with third capacitor；The pole G of 8th metal-oxide-semiconductor and S interpolar are also connected with the 4th capacitor.
7. the power supply circuit of double chargers as claimed in claim 6, which is characterized in that the first voltage input pin also connects
It is connected to the 5th capacitor, the first voltage output pin is also connected with the 6th capacitor；The second voltage input pin is also connected with
There is the 7th capacitor, the second voltage output pin is also connected with the 8th capacitor.
8. the power supply circuit of double chargers as claimed in claim 7, which is characterized in that the pole D and the pole S of the third metal-oxide-semiconductor
Between be connected with first diode, the anode of the first diode connects the pole D of the third metal-oxide-semiconductor, the one or two pole
The cathode of pipe connects the pole S of the third metal-oxide-semiconductor；It is connected with the second diode between the pole D and the pole S of 4th metal-oxide-semiconductor, institute
The anode for stating the second diode connects the pole D of the 4th metal-oxide-semiconductor, and the cathode of second diode connects the 4th MOS
The pole S of pipe.
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| CN112886656A (en) * | 2021-01-15 | 2021-06-01 | 维沃移动通信有限公司 | Conversion device and charging system |
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| CN108964216A (en) * | 2018-09-26 | 2018-12-07 | 深圳市超力源科技有限公司 | Discharge after a kind of over-charging of battery and over-discharge after charging detecting circuit and detection method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112886656A (en) * | 2021-01-15 | 2021-06-01 | 维沃移动通信有限公司 | Conversion device and charging system |
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