CN110427337A - Processor cores and its operation method based on field programmable gate array - Google Patents

Processor cores and its operation method based on field programmable gate array Download PDF

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Publication number
CN110427337A
CN110427337A CN201910930708.XA CN201910930708A CN110427337A CN 110427337 A CN110427337 A CN 110427337A CN 201910930708 A CN201910930708 A CN 201910930708A CN 110427337 A CN110427337 A CN 110427337A
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register
input
state
value
data
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CN110427337B (en
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徐庆嵩
刘锴
刘建华
王铜铜
范召
杜金凤
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Guangdong High Cloud Semiconductor Technologies Ltd Co
Gowin Semiconductor Corp
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
    • G06F2015/768—Gate array

Abstract

The present invention discloses a kind of processor cores and its operation method based on field programmable gate array.The processor cores include input/output module, decoding module and execution module；Input/output module carries out transmission operation according to the address signal of core external equipment and core external equipment, core external equipment includes command memory and data storage for connecting core external equipment uniformly as processor cores to transmit the unique transport interface of data and instruction；The instruction that decoding module is used to read input/output module from command memory carries out decoded operation, generates decoding result；Execution module is used to carry out processing operation according to decoding result.The technical program connects core external equipment uniformly using input/output module as processor cores to transmit the unique transport interface of data and instruction, uniform transmission logic control is carried out to input/output module, reduce the use of logical resource, reduce core design difficulty, inner core can be simplified, reduce kernel power consumption.

Description

Processor cores and its operation method based on field programmable gate array
Technical field
The present invention relates to processor cores technical field more particularly to a kind of processors based on field programmable gate array Kernel and its operation method.
Background technique
With the quick hair of field programmable gate array (Field-Programmable Gate Array, FPGA) technology Exhibition, the processor cores based on FPGA are using more and more extensive, compared with conventional processors kernel, in the processor based on FPGA Core has good scalability, and designer can be conducive to according to the function of different application scene spread processor cores Quickly design and reuse.
The existing processor cores based on FPGA include instruction fetch module, data read-write module, decoding module and execution Module.Instruction fetch module reads the instruction in the command memory outside core, sends commands to decoding module；Data read-write module The data in the data storage outside core are read, are write the data in general register, or read the data in general register, It writes the data in the data storage devices outside core；Execution module carries out processing operation according to the decoding result of decoding module. The prior art has two coffrets of instruction fetch module and data read-write module, need to design two sets of transmission logics and controls respectively and takes Instruction module and data read-write module, this is needed using more logical resource, and core design difficulty is larger.
Summary of the invention
The embodiment of the present invention provides a kind of processor cores and its operation method based on field programmable gate array, can The use of logical resource is reduced, core design difficulty is reduced.
The embodiment of the present invention uses following technical scheme:
In a first aspect, the embodiment of the present invention provides a kind of processor cores based on field programmable gate array, including input defeated Module, decoding module and execution module out；Input/output module is used to connect core external equipment uniformly as processor cores to pass The unique transport interface of transmission of data and instruction carries out transmission operation according to the address signal of core external equipment and core external equipment, outside core Equipment includes command memory and data storage；Decoding module is used for the finger read to input/output module from command memory It enables and carries out decoded operation, generate decoding result；Execution module is used to carry out processing operation according to decoding result.
Wherein, input/output module includes address register, the effective register of data, output data register, data word Save effective register and input data register；
Input/output module is specifically used for:
When executing output operation, the output data useful signal being written in the effective register of data is second value, in address The address signal that core external equipment is written in register, is written output data in output data register, effective in data byte The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；
When executing input operation, the output data useful signal being written in the effective register of data is the first value, in address The address signal of core external equipment is written in register, so that address signal corresponds to core external equipment and input instruction or input data are write Enter in input data register.
As optional embodiment, processor cores use finite states machine control instruction processing pipeline, finite state The Status Type of machine includes reading instruction state, decoded state, obtains operand and instruction type state, execution state and post Storage writes back state；
When the Status Type of finite state machine is reading instruction state, control input/output module carries out reading instruction operation；When having When the Status Type for limiting state machine is decoded state, control decoding module carries out decoded operation；When the state class of finite state machine Type is when obtaining operand and instruction type state, and control execution module carries out obtaining operand and instruction type operation；When having When the Status Type for limiting state machine is execution state, control execution module carries out execution operation；When the state class of finite state machine When type is that register writes back state, control execution module carries out register writeback operations.
As optional embodiment, execution module is specifically used for receiving instruction type, the source deposit that decoding module generates Device number, destination register number and immediate, the value for obtaining corresponding position in the corresponding general register of source register number are made For source operand, the sub- state of the execution state of finite state machine is determined according to instruction type, executes the corresponding place of the sub- state Reason operation；Wherein, the sub- state for executing state includes arithmetic logical operation state, read operation state, write operation state, condition point Branch state and unconditional jump state, this little state respectively correspond arithmetic logical operation operation, read operation, write operation, item Part branch operation and unconditional jump operation.
As optional embodiment, execution module includes that register group administrative unit, register writeback unit, arithmetic are patrolled Unit and I/O management unit are collected, register group administrative unit is equipped with general register and program pointer register；
Execute the corresponding processing operation of the sub- state, comprising:
When executing arithmetic logical operation operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, it will The result of operation is saved in destination register and numbers in corresponding general register；
When executing conditional branch operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, according to fortune The result of calculation determines the offset that jumps of program pointer next step, the value of the program pointer in reading program pointer register, by Value and the value that jumps program pointer offset calculating jump after of the arithmetic logic unit according to program pointer, pass through register write Receipt member writes back the value of the program pointer after jumping in program pointer register；
When executing unconditional jump operation, offset is jumped using source operand or immediate as program pointer next step, The value of program pointer in reading program pointer register according to the value of program pointer and jumps offset by arithmetic logic unit The value of program pointer after jumping, is write back program pointer by register writeback unit by the value for calculating the program pointer after jumping In register；
When performing writes, by I/O management unit being written in the effective register of data in input/output module Output data useful signal be set to second value, in the address register of input/output module be written core external equipment address letter Number, output data is written in the output data register of input/output module, it is effective in the data byte of input/output module The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；The operating result that input/output module returns is saved in purpose to post Storage is numbered in corresponding general register；
When executing read operation, the address signal of core external equipment is written in the address register of input/output module, so that ground Location signal corresponds to core external equipment in the input data register of input instruction or input data write-in input/output module；Defeated The operating result for entering output module return is saved in destination register and numbers in corresponding general register.
As optional embodiment, processor cores further include interrupt management module, and interrupt management module includes interrupting Enabled register, interrupt latency register, interrupt return address register and interruption idle state register；
Interrupt management module is used for, will be in interrupt request singal and interrupt enable register when receiving interrupt request singal Value is compared, and judges whether interrupt request singal is in enabled state；If it is not, shielding interrupt request singal；If so, will interrupt The value of waiting register interrupt request singal corresponding position is set to second value；
If being handled according to the confirmation of idle state register is interrupted currently without interrupt request singal, terminate in present instruction execution Afterwards, present procedure pointer is saved in interrupt return address register, the value for interrupting idle state register is set to first Value, is saved in stack space for the current value in the general register of execution module register group administrative unit, present procedure is referred to Needle jumps to interrupt processing function entrance, executes the corresponding interrupt function of value in interrupt latency register；Break letter in commission After number, the scene before executing is interrupted by the current value reduction of stack space, the value for interrupting idle state register is set to second Value jumps to the next instruction interrupted before executing according to the present procedure pointer in interrupt return address register.
As optional embodiment, interrupt management module is also used to, if working as according to the confirmation of idle state register is interrupted Before there is interrupt request singal handling, waiting current interrupt request singal, processing terminate, continues with receipts in after treatment The interrupt request singal arrived.
As optional embodiment, interrupt enable register, interrupt latency register, interrupt return address register are set In the register group administrative unit of execution module, in register group administrative unit general register and program pointer deposit Device Unified number, unified addressing, unified Read-write Catrol.
As optional embodiment, core external equipment further includes peripheral hardware register, peripheral hardware register, command memory sum number According to memory Unified number, unified addressing.
As optional embodiment, processor cores are the processor cores of the 5th generation reduced instruction set computer framework.
Second aspect, the embodiment of the present invention provide a kind of operation side of processor cores based on field programmable gate array Method, processor cores include input/output module, decoding module and execution module；
Input/output module connects core external equipment uniformly as processor cores to transmit the unique transport interface of data and instruction, Transmission operation is carried out according to the address signal of core external equipment and core external equipment, core external equipment includes command memory and data storage Device；Decoding module carries out decoded operation to the instruction that input/output module is read from command memory, generates decoding result；It executes Module carries out processing operation according to decoding result.
As optional embodiment, input/output module includes address register, the effective register of data, output data The effective register of register, data byte and input data register；
Transmission operation is carried out according to the address signal of core external equipment and core external equipment, comprising:
When executing output operation, the output data useful signal being written in the effective register of data is second value, in address The address signal that core external equipment is written in register, is written output data in output data register, effective in data byte The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；
When executing input operation, the output data useful signal being written in the effective register of data is the first value, in address The address signal of core external equipment is written in register, so that address signal corresponds to core external equipment and input instruction or input data are write Enter in input data register.Wherein, input operation includes operating or the reading instruction of command memory to data storage Read data manipulation.
As optional embodiment, processor cores use finite states machine control instruction processing pipeline, finite state The Status Type of machine includes reading instruction state, decoded state, obtains operand and instruction type state, execution state and post Storage writes back state；
When the Status Type of finite state machine is reading instruction state, control input/output module carries out reading instruction operation；
When the Status Type of finite state machine is decoded state, control decoding module carries out decoded operation；
When the Status Type of finite state machine is to obtain operand and instruction type state, control execution module carries out acquisition behaviour It counts and is operated with instruction type；
When the Status Type of finite state machine is execution state, control execution module carries out execution operation；
When the Status Type of finite state machine is that register writes back state, control execution module carries out register writeback operations.
As optional embodiment, execution module carries out processing operation according to decoding result, comprising: execution module receives Instruction type, source register number, destination register number and the immediate that decoding module generates, obtain source register number pair It answers the value of corresponding position in general register as source operand, the execution state of finite state machine is determined according to instruction type Sub- state executes the corresponding processing operation of the sub- state；
Wherein, the sub- state for executing state includes arithmetic logical operation state, read operation state, write operation state, conditional branching State and unconditional jump state, this little state respectively correspond arithmetic logical operation operation, read operation, write operation, condition Branch operation and unconditional jump operation.
As optional embodiment, execution module includes that register group administrative unit, register writeback unit, arithmetic are patrolled Unit and I/O management unit are collected, register group administrative unit is equipped with general register and program pointer register；
Execute the corresponding processing operation of the sub- state, comprising:
When executing arithmetic logical operation operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, it will The result of operation is saved in destination register and numbers in corresponding general register；
When executing conditional branch operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, according to fortune The result of calculation determines the offset that jumps of program pointer next step, the value of the program pointer in reading program pointer register, by Value and the value that jumps program pointer offset calculating jump after of the arithmetic logic unit according to program pointer, pass through register write Receipt member writes back the value of the program pointer after jumping in program pointer register；
When executing unconditional jump operation, offset is jumped using source operand or immediate as program pointer next step, The value of program pointer in reading program pointer register according to the value of program pointer and jumps offset by arithmetic logic unit The value of program pointer after jumping, is write back program pointer by register writeback unit by the value for calculating the program pointer after jumping In register；
When performing writes, by I/O management unit being written in the effective register of data in input/output module Output data useful signal be set to second value, in the address register of input/output module be written core external equipment address letter Number, output data is written in the output data register of input/output module, it is effective in the data byte of input/output module The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；The operating result that input/output module returns is saved in purpose to post Storage is numbered in corresponding general register；
When executing read operation, the address signal of core external equipment is written in the address register of input/output module, so that ground Location signal corresponds to core external equipment in the input data register of input instruction or input data write-in input/output module；Defeated The operating result for entering output module return is saved in destination register and numbers in corresponding general register.
As optional embodiment, processor cores further include interrupt management module, and interrupt management module includes interrupting Enabled register, interrupt latency register, interrupt return address register and interruption idle state register；
Operation method further include:
When receiving interrupt request singal, interrupt request singal is compared with the value in interrupt enable register, in judgement Whether disconnected request signal is in enabled state；If it is not, shielding interrupt request singal；If so, interrupt latency register interrupts are asked The value of signal corresponding position is asked to be set to second value；
If being handled according to the confirmation of idle state register is interrupted currently without interrupt request singal, terminate in present instruction execution Afterwards, present procedure pointer is saved in interrupt return address register, the value for interrupting idle state register is set to first Value, is saved in stack space for the current value in the general register of execution module register group administrative unit, present procedure is referred to Needle jumps to interrupt processing function entrance, executes the corresponding interrupt function of value in interrupt latency register；Break letter in commission After number, the scene before executing is interrupted by the current value reduction of stack space, the value for interrupting idle state register is set to second Value jumps to the next instruction interrupted before executing according to the present procedure pointer in interrupt return address register.
As optional embodiment, the value of interrupt latency register interrupts request signal corresponding position is set to second value Later, further includes:
If currently thering is interrupt request singal handling according to the confirmation of idle state register is interrupted, current interrupt requests is waited to believe Number processing terminate, and the interrupt request singal received is continued in after treatment.
As optional embodiment, interrupt enable register, interrupt latency register, interrupt return address register are set In the register group administrative unit of execution module, in register group administrative unit general register and program pointer deposit Device Unified number, unified addressing, unified Read-write Catrol.
As optional embodiment, core external equipment further includes peripheral hardware register, peripheral hardware register, command memory sum number According to memory Unified number, unified addressing.
As optional embodiment, processor cores are the processor cores of the 5th generation reduced instruction set computer framework.
Compared with prior art, the embodiment of the present invention has the advantages that
In the technical program, core external equipment is connected uniformly using input/output module as processor cores to transmit data and instruction Unique transport interface, core external equipment including command memory and data storage is connected, according to address signal and core External equipment is read out the transmission operations such as instruction, read-write data, and processor cores carry out uniform transmission to input/output module and patrol Control is collected, the use of logical resource is reduced, reduces core design difficulty；Moreover, externally there was only unique transport interface, can simplify interior Nuclear structure optimizes interior long term voyage, reduces kernel power consumption.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is processor cores schematic diagram disclosed by the embodiments of the present invention；
Fig. 2 is input/output module schematic diagram disclosed by the embodiments of the present invention；
Fig. 3 is decoding module schematic diagram disclosed by the embodiments of the present invention；
Fig. 4 is finite state machine status transition diagram disclosed by the embodiments of the present invention；
Fig. 5 is execution module schematic diagram disclosed by the embodiments of the present invention；
Fig. 6 is interrupt management module diagram disclosed by the embodiments of the present invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Processor cores based on FPGA are the most important component parts of processor, can be made of monocrystalline silicon, for handling Various operations.
It is processor cores schematic diagram disclosed by the embodiments of the present invention referring to Fig. 1.The present embodiment based on field-programmable The processor cores of gate array, including input/output module 10, decoding module 20 and execution module 30；Input/output module 10 is used In uniformly connecting core external equipment as processor cores to transmit the unique transport interface of data and instruction, according to core external equipment Address signal and core external equipment carry out transmission operation, and core external equipment includes command memory and data storage.The coffret Unified connection core external equipment, transmits the various data and instructions handled by execution module 30；The coffret does not forward interruption phase OFF signal interrupts coherent signal and is handled by interrupt management module 40.Address signal, input and output mould are arranged to core external equipment in advance Block 10 can be interacted according to the address signal with the core external equipment of address signal.Decoding module 20 is used for input and output The instruction that module 10 is read from command memory carries out decoded operation, generates decoding result.Execution module 30 is used for according to decoding As a result processing operation is carried out.Execution module 30 carries out processing operation corresponding with the decoding result to various decoding results；Except this Except, execution module 30 can also carry out each generic operation.
The processor cores of the present embodiment may include interrupt management module 40；As another alternative, in processor Core may not include interrupt management module 40, and interrupt management module 40 can be set in the outside of processor cores, interrupt management mould Block 40 from core extroversion core program pointer register 306 and execution module 30 send interrupt coherent signal.Interrupt management module 40 interrupt coherent signal for handling, and can be used as interrupt interface；If interrupt management module 40 sends interruption out of core extroversion core Coherent signal, then in core it is settable receive the interruption coherent signal interrupt interface.The execution module 30 of the embodiment of the present invention is wrapped General register 305 and program pointer register 306 are included, is arranged in the register group administrative unit 301 of execution module 30 logical With register 305 and program pointer register 306；As another alternative, execution module 30 may not include general register 305 and/or program pointer register 306, they can be used as the standalone module in processor cores.
The external equipment of core external equipment finger processor kernel, it may include inside same processor and in the processor External equipment except core or the outside the processor external equipment in portion.For example, external equipment includes but is not limited to: instruction storage Device, data storage, peripheral hardware register, audio processor, wireless processor etc.；In addition, when the technical program is applied to multicore When processor, external equipment may additionally include and carry out data and/or instruction friendship with present processor kernel inside same processor Other mutual processor cores.Certain core external equipments can be by controlling with the affiliated processor of present processor kernel, certain core peripheral hardwares It is standby to be controlled by other processors.
Alternatively, command memory and data storage Unified number, unified addressing.As a kind of optional Mode, core external equipment further include peripheral hardware register, peripheral hardware register, command memory and data storage Unified number, uniformly Addressing.There are more set transmission logics to control multiple modules in the prior art and is separately connected different core external equipments, it is each to cover logic respectively Independent operating, therefore core external equipment Unified number, unified addressing are not required.And the input/output module 10 of the technical program uniformly connects Core external equipment is connect, therefore core external equipment Unified number, unified addressing, processor cores realize efficient management core external equipment, improve fortune Line efficiency.
Input/output module 10 connects core external equipment uniformly as processor cores to transmit unique biography of data and instruction Defeated interface, the coffret transmit data and instruction (or signal), including from the command memory outside core read instruction (or Claim program instruction), to core outside data storage reading and writing data (or operational data).It should be noted that can be program Instruction is used as special data, using operational data as general data, they belong to be stored in the two of memory relevant device into Information processed is referred to as data that is, the data of the instruction and data memory in command memory；Then input/output module 10 is made It connects core external equipment uniformly for processor cores to transmit the unique transport interface of data and instruction, can be expressed as, input defeated Module 10 connects core external equipment uniformly as processor cores to transmit the unique data coffret of data out；Processor cores In the data of different phase processing, which may include operational data and/or program instruction, at processor cores different phase The data of reason are operational data or program instruction, this belongs to the prior art or those skilled in the art can according to the prior art To obtain.
In the present embodiment, processor cores can be the 5th generation reduced instruction set computer (Reduced Instruction Set Computing FIVE, RISC-V) framework processor cores, i.e. processor cores application RISC-V framework.RISC-V framework It is a kind of open source instruction set architecture based on reduced instruction set computer, has the characteristics that framework is simple, modularized design, is easy to transplant, The instruction set of RISC-V is externally increased income, anyone, any tissue can freely use the instruction set of RISC-V, is used for RISC-V frame The processor cores of structure design and software development.In the present embodiment, processor cores combination RISC-V framework is simple, increases income completely The characteristics of and FPGA it is programmable, easily extension the characteristics of, have that structure is simple, area is small, low in energy consumption, easy extension, easily transplanting etc. are excellent Point meets the data processing needs of various lightweights, depth insertion.
In addition, the processor cores of the embodiment of the present invention can also be using the reduced instruction set computer frame in other generations in addition to the 5th generation Structure processor cores.Alternatively, the processor cores of the embodiment of the present invention can also apply complex instruction set (Complex Instruction Set Computing, CISC) framework, explicit parallel instruction set (Explicitly Parallel Instruction Computing, EPIC) framework, very long instruction word, instruction set (VLIW) framework etc. other Structure.
As an embodiment, the operation method of processor cores includes: input/output module 10 as in processor Core uniformly connects core external equipment to transmit the unique transport interface of data and instruction, according to outside the address signal and core of core external equipment Equipment carries out transmission operation, and core external equipment includes command memory and data storage；Decoding module 20 is to input/output module 10 instructions read from command memory carry out decoded operation, generate decoding result；Execution module 30 is carried out according to decoding result Processing operation.
In the embodiment of above-mentioned operation method, input/output module 10 uniformly connects core external equipment as processor cores To transmit the unique transport interface of data and instruction, indicate that present processor kernel only has this coffret of input/output module, It can unify connection core external equipment, transmit data and instruction with core external equipment.According to the address signal of core external equipment and core peripheral hardware Standby to carry out transmission operation, address signal is arranged to core external equipment in advance in Ke Yiwei, according to address signal energy and address signal Core external equipment interact；It is passed from different or identical core external equipment according to processor cores in different working stages The corresponding data of the defeated working stage and/or instruction including but not limited to read instruction from the command memory outside core, to core Outer data storage reading and writing data.Command memory and data storage can realize by independent two memories, can also To be realized by the same memory with instruction and data store function.Execution module remove for according to decoding result at Reason operation is outer, can be also used for each generic operation.Above-mentioned operation method is in the different operating stage, can be with by input/output module It only reads and instructs from command memory, data or handle can also be read from data storage before or after the instruction of reading Data storage is written in data, this belongs to the prior art, and this will not be repeated here；When the embodiment of the present invention is not intended to limit using defeated Enter output module transmission data or instruction.
Processor cores only have this unified connection core external equipment of input/output module 10 to transmit data and instruction only One coffret, only need to input/output module 10 carry out uniform transmission logic control, compared with the existing technology have it is multiple not The coffret of congenerous and need to design cover transmission logics, the technical program need to only design a set of transmission logic, reduce FPGA The use of logical resource reduces core design difficulty；Externally there was only unique transport interface, inner core can be simplified, so that kernel Layout is simple, optimizes interior long term voyage, so that interior long term voyage becomes smaller, reduces input power, so that reducing kernel power consumption.
It should be noted that the embodiment of the present invention is implementing this skill to multiple modules, unit, register definitions title When art scheme, those of ordinary skill in the art can modify to the title；As long as modifying the module after title, unit, deposit The realization function of device is identical as the module of the embodiment of the present invention, unit, the realization function of register or equivalent, belongs to the present invention The range of protection.
It referring to fig. 2, is 10 schematic diagram of input/output module disclosed by the embodiments of the present invention.In the present embodiment, input and output Module 10 is effectively deposited including address register 101, the effective register 102 of data, output data register 103, data byte Device 104 and input data register 105.
Input/output module 10 is specifically used for: when executing output operation, being written in the effective register 102 of data defeated Data valid signal is second value out, and the address signal of core external equipment is written in address register 101, is deposited in output data Output data is written in device 103, the byte useful signal of output data is written in the effective register 104 of data byte, so that ground The core external equipment that location signal corresponds to reads output number according to the byte useful signal of output data from output data register 103 According to；When executing input operation, the output data useful signal being written in the effective register 102 of data is the first value, on ground The address signal of core external equipment is written in location register 101, input is instructed or inputted so that address signal corresponds to core external equipment Data are written in input data register 105.Wherein, input operation includes operating or the reading instruction of command memory to data The reading data manipulation of memory.Here second value is 1, and the first value is 0；It certainly, can basis as an optional embodiment Second value, the first value are set to other values by practical application scene, for example, second value is 0, the first value is 1.
When output data useful signal is second value, Notify Address signal corresponds to core external equipment and can deposit from output data Output data is read in device 103；Core external equipment is read when reading output data according to the byte useful signal of output data It takes, for example, the byte useful signal of output data is 1, reads the correspondence byte of output data, the byte of output data is effectively believed Number be 0, do not read the correspondence byte of output data.When output data useful signal is the first value, address signal corresponds to core peripheral hardware It is standby input data to be written in input data register 105.
Address above mentioned signal corresponds to core external equipment according to the byte useful signal of output data from output data register Output data is read, Ke Yiwei, address signal corresponds to core external equipment, according to the output data in the effective register of data byte Byte useful signal reads output data from output data register.
Address above mentioned signal corresponds to core external equipment in input instruction or input data write-in input data register, can be with For when input operation operates for the reading instruction to command memory, address signal corresponding instruction memory is input instruction write-in In input data register, when input operation is the reading data manipulation to data storage, address signal corresponding data memory In input data write-in input data register；In addition to this it is possible to be, input operation is the reading to peripheral hardware register When according to operation, address signal corresponds to peripheral hardware register in input data write-in input data register.
Above-mentioned input operation is including but not limited to the reading instruction operation of command memory or to the reading of data storage According to operation；Input operation can also include to other types core external equipment, such as to reading data manipulation of peripheral hardware register etc..When When executing input operation each time, this time input operation can be reading instruction operation or read data manipulation.It is executing several times During input operation, it can successively execute several and the reading instruction of command memory is operated, or successively to execute several right The reading data manipulation of data storage, or intersect and execute the operation of several reading instructions and read data manipulation.
Each register of input/output module 10 has following function, and address register 101 is for storing core external equipment Address signal；The effective register 102 of data is for storing output data useful signal；Output data register 103 is for storing Output data；The effective register 104 of data byte is used to store the byte useful signal of output data；Input data register 105 for storing the input data of core external equipment.
Wherein, the output data useful signal being written in the effective register 102 of data is second value, specifically, can be with When executing output operation, the output data useful signal of second value is written as in the effective register 102 of data；It can also be Before executing output operation, the output data useful signal of second value is written as in the effective register 102 of data.It is effective in data The output data useful signal being written in register 102 is the first value, specifically, can be when executing input operation, in data It is written as the output data useful signal of the first value in effective register 102, can also have before executing input operation in data The output data useful signal of the first value is written as in effect register 102.
In the present embodiment, output data is written in output data register 103, in the effective register 104 of data byte The byte useful signal that output data is written, so that address signal corresponds to core external equipment according to the byte useful signal of output data Output data is read from output data register 103.When byte useful signal be it is effective, it is effective that core external equipment reads the byte The byte of the corresponding output data of signal, when byte useful signal be it is invalid, core external equipment does not read the byte useful signal pair The byte for the output data answered；The byte useful signal of output data provides effective shielding/enabled information for core external equipment, keeps away Exempt from the mistake write operation that may occur, guarantees the accuracy of operation.
The present embodiment is instructed using 32 RISC-V, the coffret that input/output module 10 is 32；It certainly, can root According to the bit wide of practical application scene setting input/output module 10, module interface signal is corresponding to be changed.Input/output module 10 Currently interactive core external equipment is determined according to address signal, if interacting with command memory, is sent to decoding mould instruction is read Block 20 transmits data between data storage and execution module 30 if interacting with data storage.
10 interface signal of input/output module of the present embodiment is as follows:
Address signal: bit wide 32, the core external equipment for core peripheral storage device, processor peripheral etc. as target provide reading Writing address signal.
Output data useful signal: bit wide 1, Ke Yiwei is ready in the output data and address signal of output operation Afterwards, output data useful signal is set to 1, and the address signal as target is notified to correspond to core external equipment and can read output data. After output operation, as an implementation, after end of output, output data useful signal sets 0 automatically；As another reality Mode is applied, in input data, output data useful signal is set 0.When useful signal sets 0, notice core external equipment can be executed Input operation.
Outputting data signals: bit wide 32 is the output data for needing to be written the core external equipment as target.
The byte useful signal of output data: 32 data of bit wide 4, output signal are divided into 4 bytes, output data 4 positions of byte useful signal be respectively intended to indicate the validity of this 4 bytes, 1 word of every 1 corresponding output data Section.When a certain position of the byte useful signal of output data is 1, indicating that it corresponds to the byte of output data is valid data, Core external equipment needs to read the byte in outputting data signals；When a certain position of the byte useful signal of output data is 0, Indicating that it corresponds to the byte of output data is invalid signals, and core external equipment does not need to read the byte in outputting data signals.
Input data useful signal: bit wide 1 can be sent out after the core external equipment as target gets out data to be entered A signal is sent, input data useful signal is set 1, notifier processes device kernel reads the data in input data register 105.
Input data signal: bit wide 32 is the input data sent as the core external equipment of target.
As an embodiment, input/output module 10 is passed according to the address signal of core external equipment with core external equipment Defeated operation, comprising: when executing output operation, the output data useful signal that is written in the effective register 102 of data is the The address signal of core external equipment is written in two-value in address register 101, the write-in output number in output data register 103 According in the byte useful signal of the effective write-in of register 104 output data of data byte, so that address signal corresponds to core external equipment Output data is read from output data register 103 according to the byte useful signal of output data；When executing input operation, The output data useful signal being written in the effective register 102 of data is the first value, is written outside core in address register 101 The address signal of equipment, so that address signal, which corresponds to core external equipment, is written input data register input instruction or input data In 105.Wherein, input operation includes the reading instruction operation to command memory or the reading data manipulation to data storage.
The present embodiment is effectively deposited by the value of the setting effective register 102 of data using address register 101, data The cooperation of device 102, output data register 103, data byte effective register 104 and input data register 105, control exist The a certain moment executes output or input operation, is interacted using time-multiplexed mode to core external equipment, including deposit to instruction Reservoir is read out instruction, is written and read data to data storage, data can also be written and read to peripheral hardware register, significantly Logical resource occupancy is reduced, interior long term voyage is optimized.
It is 20 schematic diagram of decoding module disclosed by the embodiments of the present invention referring to Fig. 3.Decoding module 20 is posted including input data Storage 201, instruction type table and immediate decoding logic module 202, decoding module 20 pass through input/output module for receiving 10 instructions read from command memory generate instruction type, source register number, destination register number and immediate etc. and translate Decoding result as a result, be simultaneously sent to execution module 30 by code.
The instruction set of RISC-V is used in the present embodiment, decoding module 20 is regular according to the instruction set encoding of RISC-V, right The instruction of reading carries out decoded operation, is first split according to 32 bit instructions of the coding rule to reading, then according to operation code Content determine the meaning and decoded mode of each yard of section, finally decoded and reconfigured, thus extract instruction type, The information such as source register number, destination register number and immediate.Decoding module 20 and input/output module 10 can have Oneself independent input data register.
It referring to fig. 4, is finite state machine status transition diagram disclosed by the embodiments of the present invention.The processor of the present embodiment Kernel uses finite states machine control instruction processing pipeline, and the Status Type of finite state machine includes reading instruction state, decoding shape State, acquisition operand and instruction type state, execution state and register write back state；When the state class of finite state machine When type is reading instruction state, control input/output module 10 carries out reading instruction operation；When the Status Type of finite state machine is to translate When code state, control decoding module 20 carries out decoded operation；When the Status Type of finite state machine is to obtain operand and instruction When type state, control execution module 30 carries out obtaining operand and instruction type operation, which can obtain operand, instruction Type can also obtain the information such as source register number, destination register number；When the Status Type of finite state machine is to execute When state, control execution module 30 carries out execution operation；When the Status Type of finite state machine is that register writes back state, control Execution module 30 processed carries out register writeback operations.
Structure of the present embodiment based on finite state machine is designed using hardware description language and is realized.Finite state machine is divided into Five Status Types: reading instruction state, decoded state, acquisition operand and instruction type state, execution state, register write back State；Wherein reading instruction state is executed by input/output module 10, and decoded state is executed by decoding module 20, obtain operand and Instruction type, execution, register write back these three states and are executed by execution module 30；This framework avoids using between the modules The degree of coupling between module can be improved in synchronous logic functional module, to substantially reduce the logical resource of processor cores Usage amount.
It is 30 schematic diagram of execution module disclosed by the embodiments of the present invention referring to Fig. 5.The execution module 30 of the present embodiment includes Register group administrative unit 301, register writeback unit 302, arithmetic logic unit 303 and I/O management unit 304, are posted Storage group administrative unit 301 is equipped with general register 305 and program pointer register 306.
Execution module 30 is specifically used for receiving instruction type, the source register number, purpose deposit that decoding module 20 generates Device number and immediate obtain source register and number the value of corresponding position in corresponding general register 305 as source operand, root The sub- state that the execution state of finite state machine is determined according to instruction type executes the corresponding processing operation of the sub- state；Wherein, it holds The sub- state of row state includes arithmetic logical operation state, read operation state, write operation state, conditional branching state, Yi Jiwu Conditional jump state, this little state respectively correspond arithmetic logical operation operation, read operation, write operation, conditional branch operation, with And unconditional jump operation.
As an optional embodiment, the corresponding processing operation of the sub- state is executed, comprising:
When executing arithmetic logical operation operation, source operand and immediate are transmitted to arithmetic logic unit 303 and carry out operation, The result of operation is saved in destination register to number in corresponding general register 305；
When executing conditional branch operation, source operand and immediate are transmitted to arithmetic logic unit 303 and carry out operation, according to The result of operation determines the offset that jumps of program pointer next step, the program pointer in reading program pointer register 306 Value, the value by arithmetic logic unit 303 according to program pointer and the value for jumping the program pointer after offset calculating jumps, pass through Register writeback unit 302 jump after the value of program pointer write back in program pointer register 306；
When executing unconditional jump operation, offset is jumped using source operand or immediate as program pointer next step, The value of program pointer in reading program pointer register 306 according to the value of program pointer and is jumped by arithmetic logic unit 303 Offset calculates the value of the program pointer after jumping, and the value of the program pointer after being jumped by register writeback unit 302 is write In backhaul sequence pointer register 306；
When performing writes, by I/O management unit 304 the effective register of data in input/output module 10 The output data useful signal being written in 102 is set to second value, and core is written in the address register 101 of input/output module 10 Output data is written in the output data register 103 of input/output module 10, in input and output in the address signal of external equipment The byte useful signal of output data is written in the effective register 104 of the data byte of module 10, so that address signal corresponds to outside core Equipment reads output data from output data register 103 according to the byte useful signal of output data；Input and output mould The operating result that block 10 returns is saved in destination register and numbers in corresponding general register 305；
When executing read operation, the address signal of core external equipment is written in the address register 101 of input/output module 10, with Address signal is set to correspond to core external equipment input instruction or the input data register of input data write-in input/output module 10 In 105；The operating result that input/output module 10 returns is saved in destination register to number in corresponding general register 305.
When executing read operation, if output data useful signal sets 0 automatically after output data, then do not need to lead to Crossing I/O management unit 304 has the output data being written in the effective register 102 of data in input/output module 10 Effect signal is set to 0(i.e. the first value)；If output data useful signal does not set 0 automatically, pass through I/O management unit 304 The output data useful signal being written in the effective register 102 of data in input/output module 10 is set to 0.
According to the value of program pointer and the program pointer after offset calculating jumps is jumped by arithmetic logic unit 303 Value, concretely, by arithmetic logic unit 303, is added the value of program pointer with offset is jumped, additive value is made For the value of the program pointer after jumping.It should be noted that each module of processor cores is related to instructing in the process of running Collection, for example instruction type, source register number, destination register number and immediate are generated, source operand and immediate are passed It is delivered to arithmetic logic unit 303 and carries out operation etc., carrying out practically process can refer to the prior art of processor, such as frame of reference Specified content is not described herein.
Determine that the sub- state of the execution state of finite state machine concretely pre-establishes instruction class according to instruction type Type table, according to the sub- state of the execution state of the corresponding finite state machine of instruction type table inquiry instruction type；It can also be, refer to The sub- status information in type comprising execution state is enabled, finite state machine is determined according to the sub- status information for including in instruction type Execution state sub- state.
In the present embodiment, execution state is divided into five sub- states as shown in Figure 4, finite state is determined according to instruction type The sub- state of the execution state of machine executes the corresponding operation of sub- state, to optimize the processing logic of execution module 30, significantly subtracts The logical resource usage amount of few processor cores.It should be pointed out that it is used as an optional embodiment, it can be state machine point For greater than five types, or less than five types；The execution state of finite state machine can also be divided into greater than five sub- states, Or less than five sub- states.
Execution module 30 is the nucleus module of processor cores, is responsible for executing arithmetic logical operation operation, conditional branching behaviour Make, unconditional jump operation, pass through the completion various processing operations such as read operation and write operation of input/output module 10.Wherein, it holds Row module 30 can also handle interruption dependent instruction, such as processing interrupt return instruction；When executing interrupt return instruction, journey is executed Sequence skip operation makes programming jump numerical value into interrupt return address register 403 indicate the address of next instruction of address, And an interruption return signal is generated, notice interruption control module Current interrupt processing has terminated.
As an embodiment, execution module 30 carries out processing operation according to decoding result, comprising: execution module 30 connects Instruction type, source register number, destination register number and immediate that decoding module 20 generates are received, source register is obtained and compiles The value of corresponding position determines holding for finite state machine according to instruction type as source operand in number corresponding general register 305 The sub- state of row state executes the corresponding processing operation of the sub- state, wherein the sub- state for executing state includes arithmetical logic fortune Calculation state, read operation state, write operation state, conditional branching state and unconditional jump state, this little state are right respectively Answer arithmetic logical operation operation, read operation, write operation, conditional branch operation and unconditional jump operation；It is patrolled when executing arithmetic When collecting arithmetic operation, source operand and immediate are transmitted to arithmetic logic unit 303 and carry out operation, the result of operation is saved It is numbered in corresponding general register 305 to destination register；When executing conditional branch operation, source operand and immediate are passed It is delivered to arithmetic logic unit 303 and carries out operation, the offset that jumps of program pointer next step is determined according to the result of operation, read The value of program pointer in program pointer register 306 according to the value of program pointer and jumps offset by arithmetic logic unit 303 Amount calculates the value of the program pointer after jumping, and the value of the program pointer after being jumped by register writeback unit 302 writes back journey In sequence pointer register 306；When executing unconditional jump operation, using source operand or immediate as program pointer next step Jump offset, the value of the program pointer in reading program pointer register 306, by arithmetic logic unit 303 according to program The value of pointer and the value for jumping the program pointer that offset calculates after jumping, after being jumped by register writeback unit 302 The value of program pointer writes back in program pointer register 306；When performing writes, pass through I/O management unit 304 The output data useful signal being written in the effective register 102 of data of input/output module 10 is set to second value, is inputting The address signal that core external equipment is written in the address register 101 of output module 10, in the output data of input/output module 10 Output data is written in register 103, output data is written in the effective register 104 of the data byte of input/output module 10 Byte useful signal, so that address signal corresponds to core external equipment and deposited according to the byte useful signal of output data from output data Output data is read in device 103；It is corresponding logical that the operating result that input/output module 10 returns is saved in destination register number With in register 305；When executing read operation, core external equipment is written in the address register 101 of input/output module 10 Address signal, so that address signal corresponds to core external equipment input instruction or the input of input data write-in input/output module 10 In data register 105；The operating result that input/output module 10 returns is saved in destination register number and corresponds to general post In storage 305.
For the present embodiment in executing the corresponding processing operation of sub- state, corresponding five operations of five sub- states pass through deposit Device writeback unit 302, arithmetic logic unit 303, I/O management unit 304, the general deposit of register group administrative unit 301 The cooperation of device 305 and program pointer register 306, efficiently completes the operation of different sub- states, between simplified element/register Operation logic improves kernel overall operation efficiency.
It is 40 schematic diagram of interrupt management module disclosed by the embodiments of the present invention referring to Fig. 6.The processor cores of the present embodiment Further include interrupt management module 40, interrupt management module 40 include interrupt enable register 401, interrupt latency register 402, in Disconnected return address register 403 and interruption idle state register 404.
Interrupt management module 40 is used for, and when receiving interrupt request singal, by interrupt request singal and interrupts enabled deposit Value in device 401 is compared, and judges whether interrupt request singal is in enabled state；If it is not, shielding interrupt request singal；If It is that the value of 402 interrupt request singal corresponding position of interrupt latency register is set to second value.If being posted according to idle state is interrupted The confirmation of storage 404 is being handled currently without interrupt request singal, and after present instruction executes, present procedure pointer is saved Into interrupt return address register 403, the value for interrupting idle state register 404 is set to the first value, by execution module 30 Current value in the general register 305 of register group administrative unit 301 is saved in stack space, and present procedure pointer is jumped to Interrupt processing function entrance executes the corresponding interrupt function of value in interrupt latency register 402；In commission after disconnected function, The scene before executing is interrupted by the current value reduction of stack space, the value for interrupting idle state register 404 is set to second value, It is jumped to according to the present procedure pointer in interrupt return address register 403 and interrupts next instruction before executing；To complete Cheng Yici interrupt processing operation.Here second value is 1, and the first value is 0；Certainly, can according to practical application scene second value, First value is set to other values.
If current processor kernel present is disconnected, the value for interrupting idle state register 404 is 0, otherwise for 1.Interrupting idle state register 404 can not be written and read by instruction.Confirm according to idle state register 404 is interrupted It is being handled currently without interrupt request singal, concretely, is reading the value for interrupting idle state register 404, if value is 1, Confirmation is being handled currently without interrupt request singal.
As an optional embodiment, interrupt management module 40 is also used to, if according to idle state register 404 is interrupted Confirmation currently has interrupt request singal handling, and waiting current interrupt request singal, processing terminate, continues in after treatment Handle the interrupt request singal received.Certainly, currently there is interrupt request singal handling in confirmation, its other party can also be used Formula, if being priority signal then priority processing than received interrupt request singal.
As an optional embodiment, interrupt enable register 401, interrupt latency register 402, interrupt return address Register 403 is set in the register group administrative unit 301 of execution module 30, and general in register group administrative unit 301 306 Unified number of register 305 and program pointer register, unified addressing, unified Read-write Catrol.Corresponding RISC-V framework, is posted Storage group administrative unit 301 is provided with 32 general register 305(x0 ~ x31 of 32 RISC-V frameworks), 1 32 program In 32 interrupt enable register 401,1 403,1 32,32 interrupt return address registers of pointer register 306,1 Disconnected enabled register 401；Interrupt management module 40 can support the interrupt requests management and response of 32 interrupt sources.It is enabled interrupting Register 401, interrupt latency register 402, interrupt return address register 403 are set to the register group management of execution module 30 In unit 301, and controlled with other register Unified numbers in register group administrative unit 301, unified addressing, unified read-write System, number and addressing are Unified number, unified addressing, unified Read-write Catrol for managing and controlling, can optimal control, raising Access speed improves the real-time of interrupt management.
In the present embodiment, interruption control module realizes the real-time management and response of interrupt request singal outwardly and inwardly. Interruption control module includes interrupt enable register 401, interrupt latency register 402, interrupt return address register 403, is These three registers are managed, according to the space encoder retained in RISC-V framework, define one group of interrupt control instruction, Including interrupting enabled instruction, interrupt register read write command, interrupt return instruction.Wherein, enabled instruction is interrupted: by interruption The write operation of enabled register 401, realization are shielded or are enabled to the interruption of specified number；Make for example, can be used and interrupt It can instruct and be compared interrupt request singal with the value in interrupt enable register 401.Interrupt register read write command: it reads Or the value of modification interrupt latency register 402, to realize some specific functions；Refer to for example, can be read and write by interrupt register It enables and the value of 402 interrupt request singal corresponding position of interrupt latency register is set to second value.Interrupt return instruction: interruption is returned The value for returning address register 403 passes to program pointer, thus the position before jumping back to interrupt processing, it can be to the idle shape of interruption State register 404 sets 1, indicates that processor core currently can receive new interrupt requests；For example, can be incited somebody to action by interrupt return instruction The value for interrupting idle state register 404 is set to second value, and the value of interrupt return address register 403 is passed to present procedure Pointer jumps to the next instruction interrupted before executing.
As an embodiment, the operation method of interruption control module, comprising:, will when receiving interrupt request singal Interrupt request singal is compared with the value in interrupt enable register 401, judges whether interrupt request singal is in enabled shape State；If it is not, shielding interrupt request singal；If so, the value of 402 interrupt request singal corresponding position of interrupt latency register is set to Second value；If being handled according to the confirmation of idle state register 404 is interrupted currently without interrupt request singal, held in present instruction After row, present procedure pointer is saved in interrupt return address register 403, idle state register 404 will be interrupted Value be set to the first value, the current value in the general register 305 of 30 register group administrative unit 301 of execution module is saved in Present procedure pointer is jumped to interrupt processing function entrance by stack space, and the value executed in interrupt latency register 402 is corresponding Interrupt function；Break after function in commission, the scene before executing is interrupted by the current value reduction of stack space, idle shape will be interrupted The value of state register 404 is set to second value, jumps to interruption according to the present procedure pointer in interrupt return address register 403 Next instruction before execution.
The present embodiment passes through the interrupt enable register 401 to interruption control module, interrupt latency register 402, interruption Return address register 403, interruption idle state register 404 are controlled, and are improved Response time, are simplified and interrupt control Logic is provided convenience for embedded development.
The above is only a preferred embodiment of the present invention, for those of ordinary skill in the art, according to the present invention Thought, there will be changes in the specific implementation manner and application range, and the content of the present specification should not be construed as to the present invention Limitation.

Claims (18)

1. a kind of processor cores based on field programmable gate array, which is characterized in that including input/output module, decoding mould Block and execution module；
Input/output module is for connecting core external equipment uniformly as processor cores to transmit the unique transport of data and instruction Interface carries out transmission operation according to the address signal of core external equipment and core external equipment, and core external equipment includes command memory sum number According to memory；
The instruction that decoding module is used to read input/output module from command memory carries out decoded operation, generates decoding knot Fruit；
Execution module is used to carry out processing operation according to decoding result；
Wherein, the input/output module includes address register, the effective register of data, output data register, data word Save effective register and input data register；
The input/output module is specifically used for:
When executing output operation, the output data useful signal being written in the effective register of data is second value, in address The address signal that core external equipment is written in register, is written output data in output data register, effective in data byte The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；
When executing input operation, the output data useful signal being written in the effective register of data is the first value, in address The address signal of core external equipment is written in register, so that address signal corresponds to core external equipment and input instruction or input data are write Enter in input data register.
2. processor cores according to claim 1, which is characterized in that the processor cores use finite state machine control Instruction processing pipeline processed, the Status Type of finite state machine include reading instruction state, decoded state, obtain operand and instruction class Type state, execution state and register write back state；
When the Status Type of finite state machine is reading instruction state, control input/output module carries out reading instruction operation；
When the Status Type of finite state machine is decoded state, control decoding module carries out decoded operation；
When the Status Type of finite state machine is to obtain operand and instruction type state, control execution module carries out acquisition behaviour It counts and is operated with instruction type；
When the Status Type of finite state machine is execution state, control execution module carries out execution operation；
When the Status Type of finite state machine is that register writes back state, control execution module carries out register writeback operations.
3. processor cores according to claim 1, which is characterized in that the execution module is specifically used for receiving decoding mould Instruction type, source register number, destination register number and the immediate that block generates, it is general to obtain source register number correspondence The value of corresponding position determines the sub- shape of the execution state of finite state machine according to instruction type as source operand in register State executes the corresponding processing operation of the sub- state；
Wherein, the sub- state for executing state includes arithmetic logical operation state, read operation state, write operation state, conditional branching State and unconditional jump state, this little state respectively correspond arithmetic logical operation operation, read operation, write operation, condition Branch operation and unconditional jump operation.
4. processor cores according to claim 3, which is characterized in that the execution module includes that register group management is single Member, register writeback unit, arithmetic logic unit and I/O management unit, register group administrative unit are equipped with general deposit Device and program pointer register；
It is described to execute the corresponding processing operation of the sub- state, comprising:
When executing arithmetic logical operation operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, it will The result of operation is saved in destination register and numbers in corresponding general register；
When executing conditional branch operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, according to fortune The result of calculation determines the offset that jumps of program pointer next step, the value of the program pointer in reading program pointer register, by Value and the value that jumps program pointer offset calculating jump after of the arithmetic logic unit according to program pointer, pass through register write Receipt member writes back the value of the program pointer after jumping in program pointer register；
When executing unconditional jump operation, offset is jumped using source operand or immediate as program pointer next step, The value of program pointer in reading program pointer register according to the value of program pointer and jumps offset by arithmetic logic unit The value of program pointer after jumping, is write back program pointer by register writeback unit by the value for calculating the program pointer after jumping In register；
When performing writes, by I/O management unit being written in the effective register of data in input/output module Output data useful signal be set to second value, in the address register of input/output module be written core external equipment address letter Number, output data is written in the output data register of input/output module, it is effective in the data byte of input/output module The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；The operating result that input/output module returns is saved in purpose to post Storage is numbered in corresponding general register；
When executing read operation, the address signal of core external equipment is written in the address register of input/output module, so that ground Location signal corresponds to core external equipment in the input data register of input instruction or input data write-in input/output module；Defeated The operating result for entering output module return is saved in destination register and numbers in corresponding general register.
5. processor cores according to claim 1, which is characterized in that the processor cores further include interrupt management mould Block, interrupt management module include interrupt enable register, interrupt latency register, interrupt return address register and interrupt idle Status register；
Interrupt management module is used for, will be in interrupt request singal and interrupt enable register when receiving interrupt request singal Value is compared, and judges whether interrupt request singal is in enabled state；If it is not, shielding the interrupt request singal；If so, will The value of interrupt request singal corresponding position described in interrupt latency register is set to second value；
If being handled according to the confirmation of idle state register is interrupted currently without interrupt request singal, terminate in present instruction execution Afterwards, present procedure pointer is saved in interrupt return address register, the value for interrupting idle state register is set to first Value, is saved in stack space for the current value in the general register of execution module register group administrative unit, present procedure is referred to Needle jumps to interrupt processing function entrance, executes the corresponding interrupt function of value in interrupt latency register；Break letter in commission After number, the scene before executing is interrupted by the current value reduction of stack space, the value for interrupting idle state register is set to second Value jumps to the next instruction interrupted before executing according to the present procedure pointer in the interrupt return address register.
6. processor cores according to claim 5, which is characterized in that the interrupt management module is also used to, if according to Interrupting the confirmation of idle state register currently has interrupt request singal handling, and current interrupt request singal is waited to handle knot Beam continues with the interrupt request singal received in after treatment.
7. processor cores according to claim 5, which is characterized in that the interrupt enable register, interrupt latency are posted Storage, interrupt return address register are set in the register group administrative unit of execution module, in register group administrative unit General register and program pointer register Unified number, unified addressing, unified Read-write Catrol.
8. processor cores according to claim 1, it is characterised in that: the core external equipment further includes peripheral hardware register, The peripheral hardware register, command memory and data storage Unified number, unified addressing.
9. according to claim 1 to processor cores described in 8 any one, it is characterised in that: the processor cores are the The processor cores of five generation reduced instruction set computer frameworks.
10. a kind of operation method of the processor cores based on field programmable gate array, which is characterized in that in the processor Core includes input/output module, decoding module and execution module；
Input/output module connects core external equipment uniformly as processor cores to transmit the unique transport interface of data and instruction, Transmission operation is carried out according to the address signal of core external equipment and core external equipment, core external equipment includes command memory and data storage Device；
Decoding module carries out decoded operation to the instruction that input/output module is read from command memory, generates decoding result；
Execution module carries out processing operation according to decoding result；
Wherein, the input/output module includes address register, the effective register of data, output data register, data word Save effective register and input data register；
The address signal according to core external equipment and core external equipment carry out transmission operation, comprising:
When executing output operation, the output data useful signal being written in the effective register of data is second value, in address The address signal that core external equipment is written in register, is written output data in output data register, effective in data byte The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；
When executing input operation, the output data useful signal being written in the effective register of data is the first value, in address The address signal of core external equipment is written in register, so that address signal corresponds to core external equipment and input instruction or input data are write Enter in input data register.
11. operation method according to claim 10, which is characterized in that the processor cores use finite state machine control Instruction processing pipeline processed, the Status Type of finite state machine include reading instruction state, decoded state, obtain operand and instruction class Type state, execution state and register write back state；
When the Status Type of finite state machine is reading instruction state, control input/output module carries out reading instruction operation；
When the Status Type of finite state machine is decoded state, control decoding module carries out decoded operation；
When the Status Type of finite state machine is to obtain operand and instruction type state, control execution module carries out acquisition behaviour It counts and is operated with instruction type；
When the Status Type of finite state machine is execution state, control execution module carries out execution operation；
When the Status Type of finite state machine is that register writes back state, control execution module carries out register writeback operations.
12. operation method according to claim 10, which is characterized in that the execution module according to decoding result at Reason operation, comprising: execution module receive decoding module generate instruction type, source register number, destination register number and Immediate obtains source register and numbers the value for corresponding to corresponding position in general register as source operand, according to instruction type The sub- state for determining the execution state of finite state machine executes the corresponding processing operation of the sub- state；
Wherein, the sub- state for executing state includes arithmetic logical operation state, read operation state, write operation state, conditional branching State and unconditional jump state, this little state respectively correspond arithmetic logical operation operation, read operation, write operation, condition Branch operation and unconditional jump operation.
13. operation method according to claim 12, which is characterized in that the execution module includes that register group management is single Member, register writeback unit, arithmetic logic unit and I/O management unit, register group administrative unit are equipped with general deposit Device and program pointer register；
It is described to execute the corresponding processing operation of the sub- state, comprising:
When executing arithmetic logical operation operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, it will The result of operation is saved in destination register and numbers in corresponding general register；
When executing conditional branch operation, source operand and immediate are transmitted to arithmetic logic unit and carry out operation, according to fortune The result of calculation determines the offset that jumps of program pointer next step, the value of the program pointer in reading program pointer register, by Value and the value that jumps program pointer offset calculating jump after of the arithmetic logic unit according to program pointer, pass through register write Receipt member writes back the value of the program pointer after jumping in program pointer register；
When executing unconditional jump operation, offset is jumped using source operand or immediate as program pointer next step, The value of program pointer in reading program pointer register according to the value of program pointer and jumps offset by arithmetic logic unit The value of program pointer after jumping, is write back program pointer by register writeback unit by the value for calculating the program pointer after jumping In register；
When performing writes, by I/O management unit being written in the effective register of data in input/output module Output data useful signal be set to second value, in the address register of input/output module be written core external equipment address letter Number, output data is written in the output data register of input/output module, it is effective in the data byte of input/output module The byte useful signal of output data is written in register, so that address signal corresponds to core external equipment and had according to the byte of output data Effect signal reads output data from output data register；The operating result that input/output module returns is saved in purpose to post Storage is numbered in corresponding general register；
When executing read operation, the address signal of core external equipment is written in the address register of input/output module, so that ground Location signal corresponds to core external equipment in the input data register of input instruction or input data write-in input/output module；Defeated The operating result for entering output module return is saved in destination register and numbers in corresponding general register.
14. operation method according to claim 10, which is characterized in that the processor cores further include interrupt management mould Block, interrupt management module include interrupt enable register, interrupt latency register, interrupt return address register and interrupt idle Status register；
The operation method further include:
When receiving interrupt request singal, interrupt request singal is compared with the value in interrupt enable register, in judgement Whether disconnected request signal is in enabled state；If it is not, shielding the interrupt request singal；If so, by interrupt latency register The value of the interrupt request singal corresponding position is set to second value；
If being handled according to the confirmation of idle state register is interrupted currently without interrupt request singal, terminate in present instruction execution Afterwards, present procedure pointer is saved in interrupt return address register, the value for interrupting idle state register is set to first Value, is saved in stack space for the current value in the general register of execution module register group administrative unit, present procedure is referred to Needle jumps to interrupt processing function entrance, executes the corresponding interrupt function of value in interrupt latency register；Break letter in commission After number, the scene before executing is interrupted by the current value reduction of stack space, the value for interrupting idle state register is set to second Value jumps to the next instruction interrupted before executing according to the present procedure pointer in the interrupt return address register.
15. operation method according to claim 14, which is characterized in that described to be interrupted described in interrupt latency register The value of request signal corresponding position is set to after second value, further includes:
If currently thering is interrupt request singal handling according to the confirmation of idle state register is interrupted, current interrupt requests is waited to believe Number processing terminate, continues with the interrupt request singal received in after treatment.
16. operation method according to claim 14, which is characterized in that the interrupt enable register, interrupt latency are posted Storage, interrupt return address register are set in the register group administrative unit of execution module, in register group administrative unit General register and program pointer register Unified number, unified addressing, unified Read-write Catrol.
17. operation method according to claim 10, it is characterised in that: the core external equipment further includes peripheral hardware register, The peripheral hardware register, command memory and data storage Unified number, unified addressing.
18. operation method described in 0 to 17 any one according to claim 1, it is characterised in that: the processor cores are the The processor cores of five generation reduced instruction set computer frameworks.
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