CN110417242B

CN110417242B - High side gate driver for GaN integrated circuits

Info

Publication number: CN110417242B
Application number: CN201910490627.2A
Authority: CN
Inventors: 李湛明; 刘雁飞; 傅玥; 吴伟东
Original assignee: Individual
Current assignee: Suzhou Liangxin Microelectronics Co ltd
Priority date: 2018-06-08
Filing date: 2019-06-06
Publication date: 2021-06-22
Anticipated expiration: 2039-06-06
Also published as: CN110417242A

Abstract

The embodiment of the invention provides a grid driving circuit for a GaN power transistor, which comprises an RS trigger and an amplifier. The S input end of the RS trigger is used for receiving the first pulse sequence, and the R input end of the RS trigger is used for receiving the second pulse sequence and then generating an output pulse sequence; the amplifier is used to amplify the output pulse train to generate a gate driver signal for the GaN power transistor. The present invention not only avoids some of the disadvantages of the prior art hybrids (e.g., Si-GaN), such as parasitic inductance from the bonding wires and metal traces on the board, especially parasitic inductance generated under high frequency operation; but also can reduce the implementation cost and improve the performance.

Description

High side gate driver for GaN integrated circuits

RELATED APPLICATIONS

This patent application claims priority from U.S. patent application No. 62/682,542 filed on 8.6.2018, the disclosure of U.S. patent application No. 62/682,542 being incorporated herein by reference in its entirety.

Technical Field

The invention relates to a GaN device, in particular to a grid driver for a GaN power transistor and application of the grid driver in a GaN integrated circuit.

Background

Gallium nitride (GaN) has been considered as the next generation semiconductor material for power electronics with high efficiency and high power density. The high frequency switching characteristics of GaN power devices relative to silicon-Si materials allow them to be used as small on-board passive components, thereby reducing parasitic losses and cost. Although discrete GaN power devices have demonstrated superior characteristics, most peripheral control/driver modules are constructed by combining these discrete GaN devices using Si technology. Such a hybrid drive scheme is inevitably challenged by parasitic inductances from the bond wires and the on-board metal traces, especially at high operating frequencies. Also, such hybrid driving systems require additional discrete components for isolation and gate driving, which requires more space on a Printed Circuit Board (PCB), thereby increasing costs.

Disclosure of Invention

One embodiment of the invention provides a gate driver for a GaN power transistor, comprising an RS flip-flop and an amplifier. The S input end of the RS trigger is used for receiving the first pulse sequence, and the R input end of the RS trigger is used for receiving the second pulse sequence and then generating an output pulse sequence; the amplifier is used for amplifying the output pulse sequence and generating a grid driving signal for the GaN power transistor.

In an embodiment of the invention, the RS flip-flop and the amplifier are integrated on the same GaN monolithic integrated circuit.

In one embodiment of the invention, the amplifier comprises one or more stages (stages), and wherein each stage is a direct coupled field effect transistor logic (DCFL) amplifier.

In an embodiment of the present invention, each of the one or more stages of the DCFL amplifier includes: a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point and an amplifier output point; wherein, the first stage input point is connected with the high side input point of the second stage; the first stage output point is connected to the second stage low side input point.

In an embodiment of the invention, the GaN power transistor, the RS flip-flop and the amplifier are integrated together in a GaN monolithic integrated circuit.

In one embodiment of the invention, the GaN power transistor is packaged together with the RS trigger and the amplifier in a combined manner.

In an embodiment of the present invention, the GaN power transistor is a high-side switch of a half-bridge circuit.

In an embodiment of the invention, the RS flip-flop is applied to a GaN monolithic integrated circuit. This RS flip-flop includes four enhancement mode high electron mobility transistors (EHEMT) and two depletion mode high electron mobility transistors (DHEMT). Two EHEMTs are wide channels and are arranged back to serve as main RS trigger transistors, the other two EHEMTs are narrow channels and serve as R and S input transistors, and the two DHEMTs serve as nonlinear loads of the main RS trigger transistors.

In one embodiment of the invention, the wide channel EHEMT and the narrow channel EHEMT and the ratio of the channel widths between those two DHEMTs are 100:30:1, respectively, and each value of this ratio can be independently varied by adding or subtracting 50% of itself.

In an embodiment of the present invention, the gate driving circuit may further include a device capable of outputting a first pulse sequence and a second pulse sequence, and a pulse width of the first pulse sequence is between 5ns and 15 ns; the pulse width of the second pulse sequence is between 5 to 15 ns.

In an embodiment of the invention, the gate driver may further include a first converter for coupling the first pulse train to the S input of the RS flip-flop and a second converter for coupling the second pulse train to the R input of the RS flip-flop.

In one embodiment of the invention, the ratio of magnetizing inductances between the first and second transducers is about 7 muh to 7 muh for a pulse width of 10ns, and this ratio can be varied independently by increasing or decreasing the first and second transducers by 50% of each.

Another embodiment of the present invention provides a GaN monolithic integrated circuit including a gate driver, the GaN monolithic integrated circuit consisting of an RS flip-flop, an amplifier and GaN power transistors.

Another embodiment of the present invention provides a method of implementing a gate drive circuit for a GaN power transistor, comprising: receiving the first pulse sequence by using an S input end of the RS trigger, and receiving the second pulse sequence by using an R input end to generate an output pulse sequence; amplifying this output pulse train generates a gate drive signal for the GaN power transistor.

The method according to an embodiment of the invention includes integrating the RS flip-flop and the amplifier together on a GaN monolithic integrated circuit.

The method of one embodiment of the invention comprises the step of integrating the GaN power transistor, the RS trigger and the amplifier on a GaN monolithic integrated circuit.

The method according to one embodiment of the invention includes co-packaging a GaN power transistor with an RS flip-flop and an amplifier.

In one embodiment of the present invention, the GaN power transistor is a high-side switch of a half-bridge circuit.

The method of the embodiment of the invention comprises the step of applying the RS trigger to a GaN monolithic integrated circuit. This RS flip-flop includes four enhancement mode high electron mobility transistors (EHEMT) and two depletion mode high electron mobility transistors (DHEMT). Two of the EHEMTs are wide channels and arranged back-to-back to serve as main RS flip-flop transistors, the other two EHEMTs are narrow channels and serve as R and S input transistors, and the two DHEMTs serve as nonlinear loads for the main RS flip-flop transistors.

In an embodiment of the present invention, the pulse width of the first pulse sequence is between 5ns and 15 ns; the pulse width of the second pulse sequence is between 5 to 15 ns.

The method of embodiments of the present invention includes coupling a first pulse train to an S input of an RS flip-flop with a first converter; a second inverter is used to couple the second pulse train to the R input of the RS flip-flop.

In one embodiment of the invention, the ratio of magnetizing inductances between the first and second transducers is about 7 muh to 7 muh for a pulse width of 10ns, and this ratio can be varied independently by increasing or decreasing the first transducer and the second transducer by 50% of each.

Another embodiment of the invention provides a switching power supply system comprising a control and gate driver circuit for half-bridge high-side switching, wherein two narrow pulse trains activate RS flip-flops through the coupling of two micro-inverters, the output of which is the input of an amplifier of a gate driver for driving a high-side power transistor.

In an embodiment of the invention, the high-side power transistor may be a GaN power transistor.

In an embodiment of the present invention, the amplifier and the high-side power transistor may be integrated in a single chip, such as a GaN monolithic integrated circuit, or may be packaged together in a single device.

In one embodiment of the present invention, the RS flip-flop is contained in a single chip, such as a GaN monolithic integrated circuit, or in a single device through co-packaging.

In an embodiment of the invention, the RS flip-flop is monolithically integrated and includes four EHEMTs and two DHEMTs. The two EHEMTs are wide channels and are arranged back to be used as main trigger transistors; the other two EHEMTs are narrow channels and are used as input transistors; those two DHEMTs are used as the nonlinear load and their channel widths are relatively shortest.

In the invention, the two wide channel EHEMTs comprise two metal layers, and the source electrode is positioned below the drain electrode; two RS trigger transistors with side grid bars are oppositely arranged, one side grid bar is provided with an open part at the top for metal connection; the other side rail has an open portion in the middle thereof for obtaining a through connection.

In one embodiment of the present invention, the two narrow channel EHEMTs are arranged as follows: one EHEMT is located directly under the bars of the first two wide-channel EHEMTs by its drain; the other EHEMT is arranged in a vertical orientation so that there is sufficient space around it to allow the baseline to pass.

In one embodiment of the invention, for two DHEMTs, one is aligned horizontally to allow an auxiliary voltage source line to pass over and through.

In one embodiment of the present invention, the EHEMT and DHEMT are configured such that the drain is positioned below the source, and the transistors are arranged in a 180 degree rotated manner.

In the present invention, the ratio of the wide channel EHEMT to the narrow channel EHEMT and the channel width between those two DHEMTs is 100:30:1, respectively, and each value of this ratio can be independently varied by adding or subtracting 50% of itself.

In the present invention, the input capacitance and micro-transformer values are 0.2nF and 7 muH: 7 muH for a 10ns pulse, and these three parameters can be adjusted by increasing or decreasing by 50%.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic diagram of a high side gate driving circuit for a GaN power transistor according to the present invention.

FIG. 2 is a schematic diagram of an RS-flip-flop of the present invention for use in GaN E-mode and D-mode High Electron Mobility Transistors (HEMTs).

FIG. 3 is a schematic layout of a GaN D-mode HEMT according to the prior art.

FIG. 4 is a schematic layout diagram of a D-mode HEMT with a two-layer metal process according to the present invention.

Fig. 5A is a schematic layout diagram of the RS flip-flop according to the present invention, and fig. 5B is a schematic diagram thereof.

Fig. 6A is a detailed layout diagram of two input E-mode transistors of the RS flip-flop shown in fig. 5, and fig. 6B is a schematic diagram thereof.

Fig. 7A is a detailed layout diagram of two main E-mode transistors of the RS flip-flop shown in fig. 5, and fig. 7B is a schematic diagram thereof.

Fig. 8A is a detailed layout diagram of two D-mode transistors of the RS flip-flop shown in fig. 5, and fig. 8B is a schematic diagram thereof.

FIG. 9 is a circuit diagram of a directly coupled field effect transistor logic (DCFL) circuit for use as an amplifier according to the present invention.

The graphs in fig. 10A and 10B depict two narrow pulse sequences from one Micro Control Unit (MCU) used in circuit simulations to trigger the RS flip-flop shown in fig. 5.

Fig. 11 is a graph showing the output characteristics of the RS flip-flop shown in fig. 5 in a circuit simulation.

Fig. 12A and 12B are output voltage and current curves, respectively, for a mid-high side GaN power transistor in a circuit simulation.

FIG. 13 is a plot of MCU output voltage and current for the circuit of FIG. 1 in a simulation.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure as recited in the claims below.

Some aspects of the invention relate to a gate drive circuit suitable for monolithic integration implemented using GaN technology. According to embodiments of the present invention, the integrated circuit can be implemented entirely in GaN, without the need to implement it by means of peripheral control and/or driver modules made using different technologies, such as Si technology. The integrated circuit implemented with GaN described in the embodiments of the present invention, on the one hand, avoids some disadvantages in the existing hybrid technologies, such as parasitic resistance from bonding wires and metal traces on the board at high frequency; on the other hand, the implementation cost can be reduced, and the performance of the product is improved.

In an embodiment of the invention, the gate driving circuit is used for a GaN power transistor. Such GaN power transistors may be used as the high-side or main switch of an air bridge switching circuit. Fig. 1 shows an embodiment in which the gate drive circuit includes an RS flip-flop 112 and an amplifier 114 for driving the gate of the high-side power transistor M11. Various implementations may be found in GaN monolithic Integrated Circuits (ICs). For example, RS flip-flops are used alone, or in combination with amplifiers, or applied simultaneously on GaN monolithic ICs. In fig. 1, the RS flip-flop, amplifier and GaN power transistor M11 are commonly implemented on a GaN monolithic IC 110, as shown by the rectangular dashed area. In other embodiments, different components such as one or more RS flip-flops, amplifiers, and GaN power transistors may be applied separately and packaged together with GaN.

The embodiment shown in fig. 1 includes a Micro Control Unit (MCU)120 or other suitable device, such as a Pulse Width Modulator (PWM), for generating the pulse trains 122, 124. The pulse train 122 and the pulse train 124 are coupled through two transformers Tx1 and Tx2 to activate the RS flip-flop 112. Pulse train 122 and pulse train 124 are in anti-phase. For example, pulse train 122 and pulse train 124 may be 180 degrees out of phase in some embodiments; in other embodiments, other values of phase difference are possible. The magnitude of the phase difference may be selected by the duty cycle of the pulses. The frequency of each pulse sequence is between 100kHz and 30MHz, and the amplitude is between 3V and 15V. The output Q of the RS flip-flop is the input of amplifier 114, which drives the main GaN power transistor M11. In this embodiment, low side GaN power transistor M12 is not used in GaN integrated circuit 110. However, in other embodiments, the low-side GaN power transistor may also be implemented in an integrated IC or packaged together with the driver and the high-side GaN power switch.

In embodiments of the present invention, the terms "transistor" and "switch" are equivalent and may be used interchangeably.

The embodiment shown in fig. 1 employs two inverters (Tx1 and Tx2) to enable the RS-flip-flop 112 located in the GaN power Integrated Circuit (IC) 110. The two inverters can transfer the pulse train signal to the gate driver while providing the required isolation (or level shifting) for the high side of the half bridge circuit. Taking a narrow pulse width of 10ns (+ -50%) as an example, the required converter is small, the occupied area on a Printed Circuit Board (PCB) can be reduced, and the cost can be reduced.

According to the embodiment shown in fig. 1, RS flip-flop 112, amplifier 114, and primary GaN power transistor M11 are monolithically integrated, and in other embodiments, other elements may also be monolithically integrated into the monolithic IC. The application of RS flip-flops in GaN ICs is based on enhancement mode (E-mode) and depletion mode (D-mode) high electron mobility transistor technology. One embodiment of an RS flip-flop is shown in fig. 2, which also includes an amplifier 114 and GaN power transistor M11.

In FIG. 2, E-mode HEMTs (EHEMTs) M2 and M5 are two main transistors connected back-to-back. M1 and M4 are two small EHEMTs, serving as input isolators for the R and S inputs, respectively. As described herein, the terms "small" and "large" with respect to EHEMT and DHEMT (HEMTs) refer to the width of the gate or channel. For example, a small HEMT has a channel width of about 20 microns, while a large HEMT has a channel width of about 200-2000 microns. M3 and M6 are two DHEMTs switched in to ensure that the nonlinear saturation velocity of the two-dimensional electron gas (2DEG) can be used as a variable load. The dimensions of M3 and M6 must be carefully selected to provide the proper load to M2 and M5. By "properly loaded" is meant that the effective resistance of M3 and M6 must be much greater than the effective resistance of M2 and M5. The sizes of M3 and M6 should be similar, for example, the size difference between M3 and M6 needs to be less than 50%.

In one embodiment of the invention, for a 650V silicon substrate GaN process, the E-mode HEMT can be obtained from the p-type GaN layer or from other sources, such as deep etching of the AlGaN layer above the channel.

In the embodiment of the invention, a two-layer metal process is adopted. For example, FIG. 3 illustrates an EHEMT layout made using the prior art, which is readily applicable to EHEMTs (e.g., M1, M4) in the practice of the present invention. Other types of layouts are of course possible. This figure shows various layer structures in the process. Metal1 and Metal2 are the two top Metal layers above the device for making the electrodes; via is an opening through the insulation between Metal1 and Metal2, which is filled with Metal to connect Metal1 and Metal 2; pad-opening is an opening in the top protective film through which the electrode contacts pass. According to the layout shown in FIG. 3, the gate Metal can communicate through Metal1 and Metal2(G-M1 and G-M2), while the source and drain can communicate only through the G-M2 Metal layer.

Fig. 4 shows an example of a layout of a D-mode HEMT, in this example, the gate length is smaller than the source length in order to be able to provide a stable bias state for the conducting channel. This arrangement may be advantageously used with DHEMTs (e.g., M3, M6) in the described embodiments of the invention. Other types of layouts are of course possible. During fabrication, the p-type GaN step can be omitted to obtain normal D-mode operation for the HEMT, as shown in fig. 3.

Fig. 5A shows a layout of an RS flip-flop having six transistors, and fig. 5B is a schematic diagram thereof. The principle is as described in figure 3. In this embodiment, pads R, S correspond to the gates of switches M1 and M4, respectively, and are placed at opposite ends of the layout (i.e., on the top and bottom of the cell in FIG. 5A) for ease of packaging. It should be noted that this embodiment has two important design features: the two metal layers are not crossed and save space.

Fig. 6A is a general view of the layout of the two input transistors (M1, M4) in fig. 5, and fig. 6B is a schematic diagram. It can be seen that the layout positions of those two small-sized EHEMTs M1 and M4 are located below the main RS flip-flop transistor, occupying less space, and crossing of metal lines can be avoided. The drains (D) of the input transistors M1 and M4 are located directly below the main RS flip-flop transistor gates (represented by

nodes

5 and 7 in fig. 6B). This placement allows enough room on both sides to place baselines connecting the RS flip-flop transistors M2, M5 with the sources of the inputs EHEMT M1, M4.

Fig. 7A is a general view of the layout of the two input transistors (M2, M5) in fig. 5A, and fig. 7B is a schematic diagram. It can be seen that gate Metal line Metal2 of the left EHEMT M2 is located to the right of this EHEMT M2, and similarly for the right EHEMT M5. The gates of the two RS flip-flops are thus facing each other. To avoid cross-over, the gate Metal line Metal2 is open to allow the output (drain) of each transistor to be connected to the input (gate) of the other transistor. Since the gates of the transistors M2, M5 must be connected to the drains of the underlying input transistors M1 and M4, an area of the gate metal strip must be open to allow connection. That is, in fig. 7A, an area is opened in the top 701 of the left gate bar (M2), and an area is opened in the middle 702 of the right gate bar (M5).

Fig. 8A is a full view of the layout of the two input D-mode HEMTs M3, M6 of fig. 5A, and fig. 8B is a schematic diagram. The right side DHEMT M6 gate bar (Metal2) is to the right of the active area compared to the left side DHEMT M3, and the device is rotated 90 degrees. This rotation leaves enough space above the right DHEMT M6 for the Vcc metal layer to pass through to both DHEMTs.

To facilitate operation of the RS flip-flop, the relative size of the device width (i.e., the width of the gate (or channel)) must conform to a certain ratio. For example, for a 0.5 micron, 6 inch wafer technology, the following parameter ranges may be used: the channel width of the master RS flip-flops EHEMT M2, M5 is between 800 and 2000 microns; the channel width of the input EHEMT M1, M4 is between 200 and 500 microns; the channel width of the DHEMT M3, M6 was between 7 and 20 microns. In the above order, the channel widths of the three pairs of transistors may be varied from 100:30: a ratio of 1 is selected wherein the channel width of each pair can be varied by increasing or decreasing by 50%. This ratio can also be used when the technology and current drive rate are varied.

As described above, the amplifier may be used independently and packaged in conjunction with a GaN IC, or may also be used with at least one of an RS flip-flop and a high-side GaN power switch in a monolithic integrated circuit. For a GaN monolithically integrated IC application, a Directly Coupled FET Logic (DCFL) circuit may be used as the amplifier. Fig. 9 is a very suitable design example. Depending on the drive requirements, a single or multiple stages of DCFL can be used to obtain a current gain of 50-5000.

In prior DCFL designs, the second stage high side input is connected as a load to the first stage and the second stage low side input is connected to the input of the first stage. However, in the embodiment shown in FIG. 9, the input connections of the second stage are the reverse of those of the prior art design. That is, the first stage input point 5 is connected to the gate of D7 and the second stage high side input point (i.e., the gate of D10); the first stage output point 4 is connected to the second stage low side input point (i.e., the gate of D9). This is an optimization of the ability of the DCFL amplifier to achieve a normal off state, which is a great advantage in power electronics applications.

Simulation calculations were performed for one embodiment of the present invention using APSYS software (Crosslight software inc. wengowa, canada, www.crosslight.com). This embodiment is constructed based on the circuit shown in fig. 1 and the RS flip-flop layout shown in fig. 5A using the DCFL amplifier shown in fig. 9. Fig. 10A and 10B show two input pulse sequences with a pulse width of 10 ns. FIG. 11 shows the simulation output of the RS flip-flop. It can be seen that fig. 11 very clearly illustrates the switching signals that are desired by embodiments of the present invention.

For simplicity, a 600V high voltage bias, 300Ohm payload is placed at the output of the main (i.e., high side) GaN power transistor (M11), as shown in fig. 2. Fig. 12A and 12B show waveform diagrams of output voltage and current. It can be seen that fig. 12A and 12B clearly demonstrate the switching characteristics of the high-side GaN power transistor M11. FIG. 13 is a reproduction curve from an oscilloscope screen shot showing the output voltage and current characteristics of the MCU in the simulation.

According to the described embodiment of the invention, the magnetization induction of the converter should be chosen large enough so that the magnetization current can be limited to a reasonable level, thereby reducing the overall power loss. The DC blocking capacitors (C1 and C2 as shown in fig. 1) should be chosen to ensure that a DC voltage must pass through them. In the simulation, C1 ═ C2 ═ 0.2nF, and magnetization induction Lmag ═ 7 μ H. In practical applications, of course, other values may be used. For example, for a 10ns pulse, the values of C1-C2-nF and Tx 1-Tx 2-7 μ H can be varied by increasing or decreasing by 50%. With the above parameters, the RMS value of the MCU current is limited to below 1mA and meets design requirements. It should be noted that a micro-transformer with 7 muh: 7 muh primary and secondary windings is relatively small, which facilitates PCB assembly and may reduce cost. If small pulse widths are used, such as 10ns, then a small size converter can be used.

The above-mentioned embodiments are only for illustrating the technical ideas and features of the present invention, and the purpose of the present invention is to enable one skilled in the art to understand the contents of the present invention and to implement the same, and the scope of the present invention is not limited to the above-mentioned embodiments, i.e. all equivalent changes or modifications made in the spirit of the present invention are covered by the protection scope of the present invention.

Claims

1. A gate drive circuit for a GaN power transistor, comprising:

an RS flip-flop having an S input for receiving the first pulse train and an R input for receiving the second pulse train and generating an output pulse train;

an amplifier for amplifying the output pulse train to generate a gate drive signal for the GaN power transistor;

the amplifier includes a DCFL amplifier including:

a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point and an amplifier output point;

wherein, the first-stage input point is connected with the second-stage high-side input point; the first stage output point is connected to the second stage low side input point.

2. A gate drive circuit as claimed in claim 1, wherein the RS flip-flop and the amplifier are integrated on a GaN monolithic integrated circuit.

3. A gate drive circuit as claimed in claim 1 wherein the amplifier comprises one or more stages, and wherein each stage is a directly coupled field effect transistor logic (DCFL) amplifier.

4. A gate drive circuit as claimed in claim 1 wherein the GaN power transistor is co-integrated with the RS flip-flop and the amplifier in a GaN monolithic integrated circuit.

5. A gate drive circuit as claimed in claim 1 wherein the GaN power transistor is packaged together in conjunction with an RS flip-flop and amplifier.

6. A gate drive circuit as claimed in claim 1 wherein the GaN power transistor is a high side switch of a half bridge circuit.

7. The gate driving circuit of claim 1, wherein the RS flip-flop is implemented in a GaN monolithic integrated circuit; the RS flip-flop includes: four EHEMTs and two DHEMTs; the two EHEMTs are wide channels and are arranged together back to serve as main RS trigger transistors; the other two EHEMTs are narrow channels and are used as an R input transistor and an S input transistor; two DHEMTs are used as nonlinear loads for the main RS flip-flop transistors.

8. A gate drive circuit as claimed in claim 7, wherein the ratio of the channel widths between the wide channel EHEMT, the narrow channel EHEMT and the two DHEMTs is 100:30:1, respectively, each of which can be varied independently by adding or subtracting 50% of itself.

9. The gate driving circuit of claim 7, wherein the gate driving circuit comprises: a device capable of outputting a first pulse train and a second pulse train, wherein the pulse width of the first pulse train is between 5 and 15 ns; the pulse width of the second pulse sequence is between 5 to 15 ns.

10. A gate drive circuit as claimed in claim 9, wherein the gate drive circuit comprises: a first converter that can couple a first pulse train to the S input of the RS flip-flop and a second converter that can couple a second pulse train to the R input of the RS flip-flop.

11. A gate drive circuit as claimed in claim 10 wherein the ratio of magnetizing inductances between the first and second transformers is approximately 7 muh to 7 muh for a pulse width of 10ns, and this ratio can be varied independently by increasing or decreasing itself by 50%.

12. A GaN monolithic integrated circuit including a gate driver, comprising: the power amplifier comprises an RS trigger, an amplifier and a GaN power transistor;

the amplifier includes a DCFL amplifier including:

13. A method of implementing a gate drive circuit for a GaN power transistor, comprising:

receiving the first pulse sequence by using an S input end of the RS trigger, and receiving the second pulse sequence by using an R input end and generating an output pulse sequence;

amplifying the output pulse train to generate a gate driver signal for the GaN power transistor;

applying an RS trigger to a GaN monolithic integrated circuit; the RS trigger comprises four EHEMTs and two DHEMTs; the two EHEMTs are wide channels and are arranged together back to serve as main RS trigger transistors; the other two EHEMTs are narrow channels and are used as an R input transistor and an S input transistor; two DHEMTs are used as nonlinear loads for the main RS flip-flop transistors.

14. The method of claim 13, comprising: the RS trigger and the amplifier are jointly integrated on a GaN monolithic integrated circuit.

15. The method of claim 13, comprising: the GaN power transistor, the RS trigger and the amplifier are jointly integrated on a GaN monolithic integrated circuit.

16. The method of claim 13, comprising: the GaN power transistor and the RS flip-flop and amplifier are packaged together.

17. The method of claim 13, wherein the GaN power transistor is a high-side switch of a half-bridge circuit.

18. The method of claim 13, wherein the ratio of channel widths between the wide channel EHEMT and the narrow channel EHEMT and DHEMT is 100:30:1, respectively, and each value of this ratio can be independently varied by adding or subtracting 50% of itself.

19. The method of claim 13, wherein the first pulse train has a pulse width of between 5 and 15 ns; the pulse width of the second pulse sequence is between 5 to 15 ns.

20. The method of claim 13, comprising: coupling a first pulse train to the S input of the RS flip-flop with a first inverter; a second inverter is used to couple a second pulse train to the R input of the RS flip-flop.

21. The method of claim 20 wherein the ratio of magnetizing inductances between the first and second transducers is about 7 muh to 7 muh for a pulse width of 10ns, and the ratio is independently variable by increasing or decreasing itself by 50%.