CN110416214A - Otp memory part and preparation method thereof, electronic device - Google Patents
Otp memory part and preparation method thereof, electronic device Download PDFInfo
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- CN110416214A CN110416214A CN201810404701.XA CN201810404701A CN110416214A CN 110416214 A CN110416214 A CN 110416214A CN 201810404701 A CN201810404701 A CN 201810404701A CN 110416214 A CN110416214 A CN 110416214A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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Abstract
The present invention provides a kind of otp memory part and preparation method thereof, electronic device, it include: semiconductor substrate, it is formed with the active area and isolation structure extended in a first direction in the semiconductor substrate, it is formed with several storage units on the active area, the adjacent storage unit is in mirror-image arrangement on the same active area；It is also formed with barrier layer on the semiconductor substrate, the barrier layer includes the first covering part extended in a second direction and the second covering part extended in a first direction, the isolation structure between the floating gate and the adjacent floating gate that the first covering part covering is located along the same line, second covering part cover the isolation structure between the adjacent bit line.Otp memory part according to the present invention can bridge the problem of interconnecting and causing component failure to avoid adjacent bit line contact hole, improve the yield and reliability of device.The production method of the otp memory part has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of and otp memory part and preparation method thereof, electricity
Sub-device.
Background technique
OTP (one time Programmable, disposable programmable) memory is a kind of common non-volatile holographic storage
Device can be realized by various structures, such as coupled capacitor type, series crystal type and dielectric breakdown type etc..Series crystal
Cast otp memory is due to being a kind of common otp memory with the small advantage at low cost of area.As shown in Figure 1, series connection is brilliant
The storage unit (cell) of body cast otp memory is made of 2 concatenated PMOS devices, one of them is used as selecting pipe, separately
Outer one is used as the storage tube of storing data, and the corresponding grid of selecting pipe is selection grid SG (Select gate), and storage tube is corresponding
Grid be floating gate FG (floating Gate), and the floating gate of each storage tube is not attached to each other.The source electrode of selecting pipe is used as
Source line SL (applies source line voltage VSL) thereon, and the drain electrode of storage tube is used as bit line BL (applying bit-line voltage VBL thereon), selection
The drain electrode of pipe and the source electrode of storage tube are connected to each other.
The course of work of series crystal type otp memory is for example are as follows: under programming state, if to store to some OTP
Unit programming is programmed, and chooses corresponding storage unit by selection grid SG and bit line BL first, selecting pipe is opened (corresponding
Selection grid SG on connect high negative potential (such as -5V), NWell and source line SL meet GND), that then increases on bit line BL is negative
Current potential (such as -5V) can generate in such channel and hale electric current, and due to hot carrier's effect, the electrons of some are gone to
(1 state) is gone above floating gate FG, if do not programmed, does not have electronics (0 state) above floating gate FG.Under normal reading state, choosing
It selects grid SG and bit line BL and only adds relatively low current potential such as -1.8V, if there is charge above floating gate FG, at this moment storage unit is just had
Bigger electric current, if no charge on floating gate FG, the electric current very little of whole memory cell judges OTP in this way
The storage unit of memory is 1 or 0.
As described above, having charge on floating gate FG after programming, we are defined as 1, but over time, on floating gate FG
The charge in face can slowly run away, and in order to delay this process, needing to deposit one layer thicker on floating gate FG prevents charge
The barrier layer (SAB) of escape, barrier layer can add silicon oxynitride or silicon nitride layer to form again with oxide skin(coating), general barrier layer
It is thicker, prevent the effect of electron escape better, said from the angle of reliability, usually with data keep (Data retention,
DR) this term indicates ability that OTP saves charge, i.e. barrier layer is thicker, and it is better that the data of memory, which keep effect,.
However, this otp memory for being deposited with barrier layer is easy to appear because contact hole bridges (bridge), and cause device
The problem of part fails, reduces the yield and reliability of product.
It is above-mentioned at least partly to solve it is therefore desirable to propose a kind of otp memory part and preparation method thereof, electronic device
Problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as presently, there are at least one, one aspect of the present invention provides a kind of otp memory part, comprising:
Semiconductor substrate is formed with the active area and isolation structure extended in a first direction in the semiconductor substrate,
Arranged for interval, the first direction and the second direction are hung down each other in a second direction for the active area and the isolation structure
Directly；
Several storage units are formed on the active area, each storage unit includes the gate tube being connected in series
And storage tube, the adjacent storage unit is in mirror-image arrangement on the same active area, and has public bit line and source
Line, each bit line two sides are formed with the floating gate extended along the second direction, and each source line two sides form one
A selection grid extended along the second direction, being located along the same line on the adjacent active area in this second direction
Selection grid be connected to each other, the floating gate being located along the same line in this second direction on the adjacent active area is each other not
Connection；
It is also formed with barrier layer on the semiconductor substrate, the barrier layer includes that first extended in a second direction is covered
Cover and the second covering part extended in a first direction, first covering part, which covers, is located at same straight line in the second direction
On the floating gate and the adjacent floating gate between the isolation structure, second covering part covers the second party
The isolation structure between the adjacent bit line.
In an embodiment of the invention, it is also formed with the covering semiconductor substrate, institute on the semiconductor substrate
State the interlayer dielectric layer of floating gate and the selection grid.
In an embodiment of the invention, contact hole, the position of the contact hole are formed in the interlayer dielectric layer
It is corresponding with the position of the bit line and the source line.
In an embodiment of the invention, the source line being located along the same line in this second direction passes through respective
The contact hole draw and make to be electrically connected each other, using as public source line.
Otp memory part according to the present invention is changed the figure on barrier layer by optimization domain, makes the barrier layer not only
Cover the isolation structure between floating gate and the adjacent floating gate, also cover between the adjacent bit line it is described every
From structure, namely the barrier layer on the isolation structure between adjacent floating gate is connected, in this way in isolation structure region
Since step has been filled and led up on barrier layer, that is, the difference in height between fleet plough groove isolation structure position and floating gate FG is reduced, so that in layer
Between have the position on barrier layer that would not generate due to step difference after dielectric layer deposition caused by hole, so just will not be adjacent
Bit line contact hole between generate the chain that continuous cavity is formed, draw so as to avoid adjacent bit line contact hole bridge joint interconnection
The problem of playing component failure, improves the yield and reliability of device.
Another aspect of the present invention provides a kind of production method of otp memory part, comprising:
Semiconductor substrate is provided, forms the active area extended in a first direction and isolation junction in the semiconductor substrate
Structure, the active area and the isolation structure arranged for interval in a second direction, the first direction and the second direction are each other
Vertically；
Form several storage units on the active area, each storage unit include the gate tube being connected in series and
Storage tube, the adjacent storage unit is in mirror-image arrangement on the same active area, and has public bit line and source line,
Each bit line two sides are formed with the floating gate extended along the second direction, and each source line two sides form an edge
The selection grid that the second direction extends, the institute being located along the same line in this second direction on the adjacent active area
Selection grid is stated to be connected to each other, the floating gate being located along the same line in this second direction on the adjacent active area that
This is not connected to；
Barrier layer is formed on the semiconductor substrate, and the barrier layer includes the first covering part extended in a second direction
With the second covering part extended in a first direction, first covering part covers to be located along the same line in the second direction
The isolation structure between the floating gate and the adjacent floating gate, second covering part cover the second direction phase
The isolation structure between the adjacent bit line.
In an embodiment of the invention, further includes: formed on the semiconductor substrate cover the semiconductor substrate,
The interlayer dielectric layer of the floating gate and the selection grid.
In an embodiment of the invention, further includes: contact hole, the contact hole are formed in the interlayer dielectric layer
Position it is corresponding with the position of the bit line and the source line.
In an embodiment of the invention, the source line being located along the same line in this second direction passes through respective
The contact hole draw and make to be electrically connected each other, using as public source line.
In an embodiment of the invention, the barrier layer also serves as metal silicide shielding layer, and the production method is also
It include: to form metal silicide on the selection grid, the bit line and the source line using the barrier layer as exposure mask.
The production method of otp memory part according to the present invention changes the figure on barrier layer by optimization domain, makes described
Barrier layer not only covers the isolation structure between floating gate and the adjacent floating gate, also cover the adjacent bit line it
Between the isolation structure, namely the barrier layer on the isolation structure between adjacent floating gate is connected, in this way every
From structural region since step has been filled and led up on barrier layer, that is, reduce the height between fleet plough groove isolation structure position and floating gate FG
Difference, so that hole caused by the position for having barrier layer after interlayer dielectric layer deposition would not be generated due to step difference, in this way
Just the chain that continuous cavity is formed will not be generated, between adjacent bit line contact hole so as to avoid adjacent bit line contact hole
The problem of bridge joint interconnects and causes component failure, improves the yield and reliability of device.
Another aspect of the invention provides a kind of electronic device, including otp memory part as described above and with the OTP
The connected electronic building brick of memory device.
Electronic device according to the present invention, since the otp memory part for being included avoids adjacent bit line contact bridge
The problem of connecing interconnection and causing component failure improves the yield and reliability of device, therefore the electronic device is with similar
Advantage.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows a kind of structural schematic diagram of the storage unit of otp memory part；
Fig. 2A shows a kind of schematic domain of otp memory part；
Fig. 2 B- Fig. 2 D shows otp memory part shown in Fig. 2A along the schematic cross sectional view of X1, X2 and Y-direction；
Fig. 3 shows the schematic domain of otp memory part according to an embodiment of the present invention；
Fig. 4 shows the step flow chart of the production method of otp memory part according to an embodiment of the present invention；
The production method that Fig. 5 A~Fig. 9 A shows otp memory part according to an embodiment of the present invention is successively implemented respectively
The obtained device of step along X1 directional profile schematic diagram；
The production method that Fig. 5 B~Fig. 9 B shows otp memory part according to an embodiment of the present invention is successively implemented respectively
The obtained device of step along X2 directional profile schematic diagram；
The production method that Fig. 5 C~Fig. 9 C shows otp memory part according to an embodiment of the present invention is successively implemented respectively
The obtained device of step along Y-direction diagrammatic cross-section.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
There is the otp memory on barrier layer to be easy to appear because contact hole bridges (bridge) deposited as before, and causes device
The problem of part fails, the reason of this problem occur through analysis has the following:
The first, the deposition on barrier layer is in polysilicon (poly), clearance wall (Spacer) and source and drain S/D on process sequence
It after production, is carried out before interlayer dielectric layer (ILD) and contact hole (CT), manufacturing process is that one layer of resistance is first grown in whole wafer
Then barrier material does not need the barrier material in barrier layer place by lithography and etching removal.To series crystal type OTP
For the storage unit of memory, selection grid SG does not need barrier layer, and floating gate FG is because for storing charge and needing to retain
Barrier layer.
The second, as shown in Figure 2 A, the storage unit of series crystal type otp memory is all that mirror image is placed, bit line BL
Respectively there is a floating gate FG in (being extracted with contact hole CT, the common end as left and right storage unit) left and right, is deposited on floating gate FG
Barrier layer SAB, and the barrier layer being located on same row floating gate FG is in integral arrangement.If the height of the polysilicon of floating gate FG itself
ForThe thickness on barrier layer is alsoPolysilicon adds the overall thickness on barrier layer to beAnd to form contact
The height of the position (BL) of hole CT is 0, when being filled in this way followed by interlayer dielectric layer medium (for example, BPSG and TEOS), figure
Shown in 2B and Fig. 2 C, the medium between floating gate FG may will appear hole 200.Since floating gate FG is each one to arrange around, such as scheme
Shown in 2D, actually (centre) continuous hole 200 can be formed between entire 2 column floating gate FG, contact holes CT etching is waited to complete,
It will occur when filling metal tungsten plug (tungsten is a kind of very strong metal of filling capacity) mutual by tungsten between 2 contact hole CT
Even, it is in contact hole bridge joint (bridge), causes component failure, the form of expression is exactly memory cell data crosstalk up and down.
If interlayer dielectric layer as described above, which fills bad inside, will appear hole, the tungsten filled out after contact hole CT etching will
2 contact holes above and below causing are spread along hole to interconnect due to tungsten, cause component failure.The generation of hole is due to 2
The polysilicon of floating gate along with the overall thickness on the barrier layer above them too it is high cause subsequent interlayer dielectric layer medium (such as
BPSG and TEOS) filling is bad and causes.Current barrier layer is arranged parallel with floating gate FG, if forming hole, hole is edge
2 FG centre up and down formed a string a string of chain 200A (as indicated by the dashed line in fig. 2 and shown in Fig. 2 D).Though in addition,
So in the delivery position of 2 floating gate FG due to not having polysilicon, difference in height is relatively small, and the cavity formed may smaller (example
As at Fig. 2 location of C cavity than at Fig. 2 B location cavity it is small) or hole be possible to discontinuously, but its equally it is right
The yield and reliability of product impact, and cavity will form continuous chain and cause to bridge usually under serious situation.
The present invention is based on above-mentioned analyses to change the figure on barrier layer, floating gate by optimizing the Butut of otp memory part
The barrier layer on the region fleet plough groove isolation structure (STI) between FG is linked up, in this way fleet plough groove isolation structure position due to
Step has been filled and led up on barrier layer, that is, reduces the difference in height between fleet plough groove isolation structure position and floating gate FG, so that being situated between in interlayer
Hole caused by having the position on barrier layer that would not generate due to step difference after electric layer deposition, although in the position on not barrier layer
Setting hole, still there may be but hole will not re-form the chain of line, and the tungsten so as to avoid 2 contact hole CT passes through
Hole interconnection.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
Fig. 3 shows the schematic domain of otp memory part according to an embodiment of the present invention.As shown in figure 3, according to this implementation
Example otp memory part include:
Semiconductor substrate is formed with the active area AA extended in a first direction and isolation junction in the semiconductor substrate
Arranged for interval, the first direction and second direction are hung down each other in a second direction for structure, the active area AA and the isolation structure
Directly.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.In the present embodiment, the constituent material choosing of semiconductor substrate
Use monocrystalline silicon.The isolation structure is, for example, fleet plough groove isolation structure.The first direction is, for example, X-direction (i.e. shown in X1, X2
Direction), the second direction is, for example, Y-direction, active area AA and the isolation structure conduct in second direction arranged for interval, Fig. 3
Signal only shows two active areas.
It is formed with storage unit on the active area AA, the region as shown in dotted line frame in Fig. 3 is a storage unit.
Each storage unit includes the gate tube and storage tube being connected in series, the grid of gate tube alternatively grid SG, storage tube
Grid as floating gate FG, the source electrode of gate tube as source line SL, the drain electrode of storage tube as bit line BL, the drain electrode of gate tube with
The source electrode of storage tube connects.In the present embodiment, the storage unit of otp memory part uses mirror-image arrangement.Specifically, such as Fig. 3
Shown, the adjacent storage unit is in mirror-image arrangement on the same active area AA, and has public bit line BL and source
Line SL, each two sides the bit line BL are formed with the floating gate FG, each source line SL two extended along the second direction
Side forms the selection grid SG extended along the second direction.Such as the active area AA being located above in Fig. 3, two are shown thereon
A storage unit, two storage units share bit line BL formed between, form a floating gate at left and right sides of bit line BL
FG, and two storage units shown in this and the unshowned storage unit in left and right are also in mirror-image arrangement, and are not shown with left and right respectively
A selection SG is formed at left and right sides of storage unit common source line SL out, source line SL.
In the present embodiment, the selection being located along the same line in this second direction on the adjacent active area AA
Grid SG is connected to each other, and the floating gate FG being located along the same line in this second direction on the adjacent active area AA is each other not
Connection.Namely in this embodiment, it is connected to each other positioned at the SG of same row, selection grid has across multiple in a second direction in other words
Source region AA makes the gate tube on the region share a selection grid SG.And floating gate FG is then that each storage unit individually owns, respectively
The floating gate of a storage unit is not connected to each other.
It is easy to cause contact hole bridge joint to lead to asking for component failure as previously mentioned, currently forming the barrier layer on floating gate FG
Topic.In the present embodiment, in order to avoid there is this problem, the figure of barrier layer SAB is optimized.As shown in figure 3, at this
In embodiment, the barrier layer SAB includes that the first covering part extended in a second direction and second extended in a first direction are covered
Cover, first covering part cover the floating gate being located along the same line in the second direction and the adjacent floating gate it
Between the isolation structure, second covering part covers the isolation junction between the adjacent bit line of the second direction
Structure.I.e. in the present embodiment, barrier layer is set as H-shaped structure or trapezium structure (regional area is H-shaped in figure, an entire column
Barrier layer is the trapezium structure of H-shaped composition).By the way that the second covering part is arranged between adjacent bit lines BL, make adjacent floating gate FG it
Between isolation structure on barrier layer connect so that the height (or step) of the isolation structure between adjacent bit lines BL rises
Height so that the region will not re-form hole when subsequent deposition interlayer dielectric layer, thus avoid adjacent bit line contact hole it
Between generate the chain that continuous cavity is formed, and then avoid adjacent bit line contact hole bridge joint interconnection and cause asking for component failure
Topic.
In the present embodiment, which further includes covering the semiconductor substrate, the floating gate FG and the choosing
The interlayer dielectric layer (not shown) of grid SG is selected, and the contact hole CT, the contact hole CT that are formed in the interlayer dielectric layer
Position it is corresponding with the position of the bit line BL and the source line SL.Also, it is located along the same line in this second direction
The source line SL drawn by the respective contact hole and make to be electrically connected each other, using as public source line.I.e.
Source line positioned at same row is electrically connected to each other, as common source line.
According to the otp memory part of the present embodiment, changes the figure on barrier layer by optimization domain, make the barrier layer not
The isolation structure between floating gate and the adjacent floating gate is only covered, is also covered described between the adjacent bit line
Isolation structure, namely the barrier layer on the isolation structure between adjacent floating gate is connected, in this way in isolation structure area
Domain reduces the difference in height between fleet plough groove isolation structure position and floating gate FG since step has been filled and led up on barrier layer, so that
Hole caused by having the position on barrier layer that would not generate due to step difference after interlayer dielectric layer deposition, so just will not be in phase
The chain that continuous cavity is formed is generated between adjacent bit line contact hole, so as to avoid adjacent bit line contact hole bridge joint interconnection
The problem of causing component failure improves the yield and reliability of device.
Embodiment two
Fig. 4 shows the step flow chart of the production method of otp memory part according to an embodiment of the present invention.
As shown in figure 4, the production method that the present embodiment discloses a kind of otp memory part, comprising:
Step 401, semiconductor substrate is provided, formed in the semiconductor substrate the active area that extends in a first direction and
Isolation structure, the active area and the isolation structure arranged for interval in a second direction, the first direction and second direction that
This is vertical；
Step 402, storage unit is formed on the active area, each storage unit includes the gating being connected in series
Pipe and storage tube, the adjacent storage unit is in mirror-image arrangement on the same active area, and with public bit line and
Source line, each bit line two sides are formed with the floating gate extended along the second direction, and each source line two sides are formed
One selection grid extended along the second direction is located at same straight line on the adjacent active area in this second direction
On selection grid be connected to each other, the floating gate being located along the same line in this second direction on the adjacent active area is each other
It is not connected to；
Step 403, barrier layer is formed on the semiconductor substrate, and the barrier layer includes extended in a second direction
One covering part and the second covering part extended in a first direction, first covering part cover in the second direction positioned at same
The isolation structure between floating gate and the adjacent floating gate on straight line, second covering part cover the second party
The isolation structure between the adjacent bit line.
According to the production method of the otp memory part of the present embodiment, changes the figure on barrier layer by optimization domain, make institute
It states barrier layer and not only covers the isolation structure between floating gate and the adjacent floating gate, also cover the adjacent bit line
Between the isolation structure, namely the barrier layer on the isolation structure between adjacent floating gate is connected, exists in this way
Isolation structure region reduces the height between fleet plough groove isolation structure position and floating gate FG since step has been filled and led up on barrier layer
Difference, so that hole caused by the position for having barrier layer after interlayer dielectric layer deposition would not be generated due to step difference, in this way
Just the chain that continuous cavity is formed will not be generated, between adjacent bit line contact hole so as to avoid adjacent bit line contact hole
The problem of bridge joint interconnects and causes component failure, improves the yield and reliability of device.
It is retouched in detail below with reference to production method of Fig. 5 A~Fig. 9 C to otp memory part according to an embodiment of the present invention
It states.
Firstly, providing semiconductor substrate 100 as shown in Fig. 5 A- Fig. 5 C, isolation is formed in the semiconductor substrate 100
Structure 101 and the active area separated by the isolation structure 101, form storage unit on the active area.
Wherein, semiconductor substrate 100 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Isolation structure 101 can be such as selective oxidation silicon or shallow
The isolation structure of trench isolations.Illustratively, in the present embodiment, isolation structure 101 uses fleet plough groove isolation structure (STI).
The shape of active area and isolation structure 101 and arrangement are as shown in figure 3,101 edge of the i.e. described active area and isolation structure
First direction extends, and arranged for interval in a second direction, the first direction and second direction are perpendicular to one another.The first direction
For example, X-direction, the second direction such as Y-direction.
The storage unit includes the gate tube and storage tube being connected in series, gate tube and storage tube include grid and
With the source electrode and drain electrode for being located at grid two sides.The wherein grid of gate tube alternatively grid SG, the grid of storage tube is as floating gate
FG.The manufacturing process of gate tube and storage tube is for example are as follows: firstly, forming grid oxic horizon 102 and more on a semiconductor substrate 100
Then crystal silicon layer 103 is performed etching by exposure mask corresponding with Butut shown in Fig. 3, selection grid SG and floating gate FG is formed, then in institute
Formation clearance wall 104 on the side wall of selection grid SG and floating gate FG is stated, finally carries out ion implanting in selection grid SG and floating gate FG two
Side forms source electrode and drain electrode, and the wherein drain electrode of storage tube is used as bit line, and the source electrode of gate tube is used as source line, the drain electrode of gate tube with
The source electrode connection (namely sharing an endpoint) of storage tube.
In the present embodiment, as shown in figure 3, the storage unit adjacent on the same active area is in mirror-image arrangement,
And there is public bit line and source line, each bit line two sides are formed with the floating gate extended along the second direction,
Each source line two sides form the selection grid extended along the second direction, on the adjacent active area described the
The selection grid being located along the same line on two directions is connected to each other, being located on the adjacent active area in this second direction
Floating gate on same straight line is not connected to each other.
Then, as shown in Fig. 6 A- Fig. 6 C, barrier material layer 105 is formed in the semiconductor substrate 100.
Barrier material layer 105 can be various suitable materials, such as oxide or nitride.Illustratively, in this reality
It applies in example, barrier material layer 105 is oxide, such as silica can be with CVD (chemical vapor deposition), PECVD (etc.
Ion body chemical vapor phase growing) the methods of formed.
Then, as shown in Fig. 7 A- Fig. 7 C, the barrier material layer 105 is performed etching, to form barrier layer 105A.
The forming process of barrier layer 105A are as follows: form patterned photoresist layer on barrier material layer 105 and/or cover firmly
Film layer, the patterned photoresist layer and/or hard mask layer have the image on barrier layer, the figure on the barrier layer such as Fig. 3
It is shown, then using the patterned photoresist layer and/or hard mask layer as exposure mask, pass through suitable dry or wet etch work
Skill, removal do not need to be formed the barrier material layer 105 in the region on barrier layer, retain the barrier material for needing to form barrier region
Layer 105, to form barrier layer 105A shown in Fig. 7 A- Fig. 7 C.
In the present embodiment, barrier layer 105A is as shown in figure 3, include the first covering part for extending in a second direction and along the
The second covering part that one direction extends, first covering part cover the floating gate FG being located along the same line in the second direction
And the isolation structure between the adjacent floating gate FG, second covering part cover the adjacent institute of the second direction
The isolation structure 101 between rheme line BL.
Further, in this embodiment, barrier layer 105A also serves as silicide shielding layer, when formed barrier layer 105A it
Afterwards, metal silicide is formed on the selection grid SG, the bit line and the source line using the barrier layer 105A as exposure mask.
Then, it as shown in Fig. 8 A- Fig. 8 C, is formed in the semiconductor substrate 100 and covers the semiconductor substrate, described
The first interlayer dielectric material layers 106 of the floating gate FG and selection grid SG.
First interlayer dielectric material layers 106 can use various suitable low-K dielectric materials, such as PSG (p-doped silicon glass
Glass), BPSG (boron-phosphorosilicate glass) etc..Illustratively, in the present embodiment, the first interlayer dielectric material layers 106 use BPSG,
With better mobility, better filling can be realized within the cleft.Illustratively, the first interlayer dielectric material layers 106
Forming process include: BPSG material deposition and reflux course, by reflux flow BPSG material again, with realization more
Good filling and flat surface.
Finally, forming the second interlayer dielectric material layers in the first interlayer dielectric material layers 106 as shown in Fig. 9 A- Fig. 9 C
107, and planarization is executed, to form initial interlayer dielectric layer, and contact hole 109 is formed in the initial interlayer dielectric layer.
Second interlayer dielectric material layers 107 can use various suitable dielectric materials, such as oxide.Illustratively,
In the present embodiment, the second interlayer dielectric material layers 107 use TEOS (ethyl orthosilicate) oxide.It can pass through heating
TEOS technique, PECVD TEOS technique or O3- TEOS technique is formed.
After the second interlayer dielectric material layers 107, which deposit, to be completed, then pass through such as CMP (chemically mechanical polishing) or mechanical
The flatening process such as grinding are planarized.Illustratively, in the present embodiment, it is planarized using CMP process.
After completing planarization, then contact hole is formed in the initial interlayer dielectric layer (i.e. ILD0) by etching technics
109, and conductive material, such as tungsten are filled in the contact hole 109 to form plug.The position of contact hole and bit line and
The position of source line is corresponding, and as shown in figure 3, the source line being located along the same line in this second direction passes through respectively
The contact hole draw and make to be electrically connected each other, using as public source line.
Further, as shown in Figure 9 A, during carrying out the second interlayer dielectric material layers 107 deposition, in adjacent floating
It bit line position between grid FG still may be due to filling bad formation since the overall thickness of floating gate FG and barrier layer 105A are larger
Hole 108, but the isolation structure region between adjacent bit lines leads to the region step liter due to the presence of barrier layer 105A
Height not will form hole, so that even if bit line position is due to filling bad formation hole between adjacent floating gate FG
108, but not will form the chain of continuous aperture hole composition between adjacent bit line contact hole, as shown in Figure 9 C, hole is in
Between isolation structure region on interrupt, in this way it is subsequent in the contact hole fill conductive material when, not will lead to bit line contact bridge
(comparison diagram 2D) is met, so as to avoid device problem of implementation, improves the yield and stability of device.
It should be appreciated that being only the hole 108 for being schematically drawn 109 side of contact hole and being likely to form in Fig. 9 C, not
The hole 108 being all likely to form is shown, such as is also likely to be present hole 108 in the other side of two contact holes 109 of Fig. 9 C,
Only it is not shown for brevity.
So far, the processing step that production method according to an embodiment of the present invention is implemented is completed, it is to be understood that this reality
Apply the technique that production flush memory device (not shown) namely this method and flush memory device can be synchronized in a manufacturing method of semiconductor device
Processing procedure is completely compatible, without increasing additional processing step.It is also understood that production method according to an embodiment of the present invention is not only
Including above-mentioned steps, before above-mentioned steps, among or may also include other desired step later, such as form source and drain contact
It the step of hole and gate contact hole and metal layer, is included in the range of this implementation production method.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including otp memory part and stores with the OTP
The connected electronic building brick of device.Wherein, which includes: semiconductor substrate, is formed in the semiconductor substrate
The active area and isolation structure extended in a first direction, the active area and the isolation structure arranged for interval in a second direction,
The first direction and second direction are perpendicular to one another；Storage unit, each storage unit are formed on the active area
Gate tube and storage tube including series connection, the adjacent storage unit is in mirror-image arrangement on the same active area, and
And there is public bit line and source line, each bit line two sides are formed with the floating gate extended along the second direction, often
A source line two sides form the selection grid extended along the second direction, on the adjacent active area described second
The selection grid being located along the same line on direction is connected to each other, and being located on the adjacent active area in this second direction is same
Floating gate on one straight line is not connected to each other；It is also formed with barrier layer on the semiconductor substrate, the barrier layer includes along
The first covering part that two directions extend and the second covering part extended in a first direction, the first covering part covering described second
The isolation structure between floating gate and the adjacent floating gate being located along the same line on direction, second covering part
Cover the isolation structure between the adjacent bit line of the second direction.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In the present embodiment, semiconductor substrate
Constituent material select monocrystalline silicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment, can be tablet computer, laptop, net book, game machine, television set,
Any electronic product such as VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be to appoint
What includes the intermediate products of the semiconductor devices.
Electronic device according to the present invention, since the otp memory part for being included avoids adjacent bit line contact bridge
The problem of connecing interconnection and causing component failure improves the yield and reliability of device, therefore the electronic device is with similar
Advantage.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of otp memory part characterized by comprising
Semiconductor substrate is formed with the active area and isolation structure extended in a first direction in the semiconductor substrate, described
Arranged for interval, the first direction and the second direction are perpendicular to one another in a second direction for active area and the isolation structure；
Several storage units are formed on the active area, each storage unit includes the gate tube being connected in series and deposits
Chu Guan, the adjacent storage unit is in mirror-image arrangement on the same active area, and has public bit line and source line, often
A bit line two sides are formed with the floating gate extended along the second direction, and each source line two sides form one along institute
State the selection grid of second direction extension, the selection being located along the same line in this second direction on the adjacent active area
Grid are connected to each other, and the floating gate being located along the same line in this second direction on the adjacent active area is not connected to each other；
It is also formed with barrier layer on the semiconductor substrate, the barrier layer includes the first covering part extended in a second direction
With the second covering part extended in a first direction, first covering part covers to be located along the same line in the second direction
The isolation structure between the floating gate and the adjacent floating gate, second covering part cover the second direction phase
The isolation structure between the adjacent bit line.
2. otp memory part according to claim 1, which is characterized in that be also formed with cover on the semiconductor substrate
Cover the interlayer dielectric layer of the semiconductor substrate, the floating gate and the selection grid.
3. otp memory part according to claim 2, which is characterized in that be formed with contact in the interlayer dielectric layer
Hole, the position of the contact hole are corresponding with the position of the bit line and the source line.
4. otp memory part according to claim 3, which is characterized in that be located at same straight line in this second direction
On the source line drawn by the respective contact hole and make to be electrically connected each other, using as public source line.
5. a kind of production method of otp memory part characterized by comprising
Semiconductor substrate is provided, forms the active area and isolation structure extended in a first direction, institute in the semiconductor substrate
Active area and the isolation structure arranged for interval in a second direction are stated, the first direction and the second direction are perpendicular to one another；
Several storage units are formed on the active area, each storage unit includes the gate tube being connected in series and storage
It manages, the adjacent storage unit is in mirror-image arrangement on the same active area, and has public bit line and source line, each
The bit line two sides are formed with the floating gate extended along the second direction, and each source line two sides form one along described
The selection grid that second direction extends, the choosing being located along the same line in this second direction on the adjacent active area
It selects grid to be connected to each other, the floating gate being located along the same line in this second direction on the adjacent active area is each other not
Connection；
Barrier layer is formed on the semiconductor substrate, and the barrier layer includes the first covering part extended in a second direction and edge
First direction extend the second covering part, first covering part cover be located along the same line in the second direction it is described
The isolation structure between floating gate and the adjacent floating gate, it is adjacent that second covering part covers the second direction
The isolation structure between the bit line.
6. production method according to claim 5, which is characterized in that further include:
It is formed on the semiconductor substrate and covers the semiconductor substrate, the interlayer dielectric of the floating gate and the selection grid
Layer.
7. production method according to claim 6, which is characterized in that further include:
Contact hole, the position of the position of the contact hole and the bit line and the source line are formed in the interlayer dielectric layer
It is corresponding.
8. production method according to claim 7, which is characterized in that be located along the same line in this second direction
The source line is drawn by the respective contact hole and makes to be electrically connected each other, using as public source line.
9. production method according to claim 5, which is characterized in that the barrier layer also serves as metal silicide masking
Layer, the production method further include:
Metal silicide is formed on the selection grid, the bit line and the source line using the barrier layer as exposure mask.
10. a kind of electronic device, including otp memory part described in any one in claim 1-4 and with the OTP
The connected electronic building brick of memory device.
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