CN110379767A - The method of wafer-level packaging chip through-hole interconnection and the test method of chip - Google Patents
The method of wafer-level packaging chip through-hole interconnection and the test method of chip Download PDFInfo
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- CN110379767A CN110379767A CN201910642140.1A CN201910642140A CN110379767A CN 110379767 A CN110379767 A CN 110379767A CN 201910642140 A CN201910642140 A CN 201910642140A CN 110379767 A CN110379767 A CN 110379767A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
The present invention provides a kind of method of wafer-level packaging chip through-hole interconnection and the test method of chip, the method for the wafer-level packaging chip through-hole interconnection includes: to provide the first chip；It is formed with the passivation layer with the first opening, on first chip to expose the first weld pad on first chip；Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；Device wafers are provided, first chip for foring polymeric layer is bonded in the device wafers；The device wafers and the polymeric layer are etched, to form first through hole, expose first weld pad；Plug is formed in the first through hole to be electrically connected with first weld pad.The method can prevent from generating undercutting (under cut) due to bubble after the etching, avoid conductive material deposition and metal the problem of not connecting, further improve the performance and yield of encapsulation.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of method of wafer-level packaging chip through-hole interconnection
And the test method of chip.
Background technique
System encapsulates (System in Package, abbreviation SiP) for the active component of multiple and different functions and passive
The other elements such as element, MEMS (MEMS), optical element, are combined in a unit, and formation one can provide a variety of
The system or subsystem of function allow heterogeneous IC integrated, are best encapsulation integrated technologies.Compared to system on chip (System
On Chip, abbreviation SoC) encapsulation, SiP integrates relatively easy, the design cycle and appears on the market that the period is shorter, and cost is relatively low, may be implemented
More complicated system.
Compared with traditional SiP, it is on wafer that wafer scale system, which encapsulates (wafer level package, abbreviation WLP),
Encapsulation integration process is completed, there is the area for substantially reducing encapsulating structure, reduce manufacturing cost, optimization electrical property, batch manufacture
Etc. advantages, can significantly reduce the demand of workload and equipment.
In wafer-level packaging processing procedure, when forming electrical connection between wafer, due to that may have bubble in the devices
The problems such as, bubble will affect the effect of plating, to cause electrical connection poor effect, or even forms open circuit, cannot be formed effectively
Electrical connection.
In view of the encapsulation of wafer scale system there are the above problem, how to form effective electrical connection and asked as urgently to be solved
Topic.
Summary of the invention
In view of the significant advantage of wafer scale system encapsulation, how preferably to realize that the encapsulation of wafer scale system is the present invention
Technical problems to be solved.
One aspect of the present invention provides a kind of wafer scale system packaging method, which comprises
First chip is provided, the passivation layer with the first opening is formed on first chip, to expose described the
The first weld pad on one chip；
Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；
Device wafers are provided, first chip for foring polymeric layer is bonded in the device wafers；
The device wafers and the polymeric layer are etched, to form first through hole, expose first weld pad；
Plug is formed in the first through hole to be electrically connected with first weld pad.
Optionally, the polymeric layer includes polyimides, polyparaphenylene's benzo dioxazole.
Optionally, the polymeric layer include can photoetching photosensitive polymers.
Optionally, heated baking is carried out to the polymeric layer, to solidify the polymeric layer.
Optionally, the polymeric layer with a thickness of 5-10 microns.
It optionally, further include the institute in the first opening before the polymeric layer is bonded in the device wafers
It states and makes the second through-hole in polymeric layer, with exposure first weld pad, the second through-hole bore is less than the first through hole
Bore.
Optionally, the first chip of the offer includes:
First wafer is provided, first chip is formed on first wafer.
Optionally, before by first chip and device wafers engagement, the method also includes:
First wafer is cut, will include first core to obtain several crystal grain comprising first chip
The crystal grain of piece is bonded on the first surface of the device wafers.
Optionally, before etching the device wafers, the method also includes:
Injection molded layers are formed on the first surface of the device wafers, to cover first chip and the device wafers
First surface；
And/or the overturning device wafers.
Optionally, the method also includes:
It is brilliant to the device after first chip for foring polymeric layer is bonded in the device wafers
Circle executes reduction process.
Optionally, etching the device wafers includes:
Form mask layer and using the mask layer as exposure mask, device wafers described in dry etching, to form first through hole, dew
First weld pad out.
Optionally, at least one of film and dry film are connected by chip, described the first of polymeric layer will be formd
Chip is bonded in the device wafers.
Optionally, formed after the plug the method also includes:
Redistribution interconnection structure is formed, the plug is electrically connected, wherein the redistribution interconnection structure includes again wiring layer
And pad, alternatively, including pad.
Optionally, seed layer is formed in the first through hole, to cover the surface of the first through hole；
Electroplating technology is executed, to deposit conductive material in the first through hole, to form the plug.
The present invention also provides a kind of test method of chip, the test method includes:
The first wafer is provided, first wafer includes the first chip, is formed on first chip with first
The passivation layer of opening, to expose the first weld pad on first chip；
Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；
The polymeric layer is etched, to form the second opening in the polymeric layer and expose first weldering
Pad；
By first weld pad, functional test is carried out to first chip.
Optionally, the polymeric layer includes polyimides, polyparaphenylene's benzo dioxazole.
Optionally, the polymeric layer be can photoetching photosensitive polymers.
Optionally, heating baking is carried out to the polymeric layer, to solidify the polymeric layer.
Optionally, the polymeric layer with a thickness of 5-10 microns.
The method of wafer-level packaging chip through-hole interconnection of the invention, described first during forming through-hole interconnection
Coated polymer layer and solidify the polymeric layer on chip, to fill first opening, wherein the polymeric layer has
Good mobility, can completely in opening in the filling passivation layer and be avoided that generation bubble, solve and filled
Bubble is led to the problem of in journey, and then prevents from generating undercutting (under cut) due to bubble after the etching, avoids conduction material
The problem of material deposition and metal do not connect, further improves the performance and yield of encapsulation.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the flow chart of the wafer scale system packaging method of a specific embodiment of the invention；
Fig. 2A to Fig. 2 I shows a specific embodiment of the invention and two panels is formed with the wafer of chip vertically heap
Folded direction stacks the diagrammatic cross-section that the method being bonded together successively implements obtained structure；
Fig. 3 A is the structural schematic diagram of the partial structurtes in Fig. 2A in box；
Fig. 3 B is the structural schematic diagram of the partial structurtes in Fig. 2 B in box.
Specific embodiment
In order to thoroughly understand the present invention, detailed step and structure will be proposed in following description, to illustrate the present invention
The technical solution of proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention is also
It can have other embodiments.
In wafer-level packaging processing procedure, film (Die attach film, DAF) can be connected by chip by a core
Piece is aspectant to be attached in another wafer, then passes through through silicon via or other connection types for the metal pad of chip
(chip1) it is connect with the metal pad (chip2) on wafer.In this process, it needs with the mode of dry etching in DAF
Through-hole is done on film.Then PVD and plating are in through-hole, complete metal connection.Because DAF film is attached to chip front side, chip front side
Metal pad pit will cause DAF and the pit of metal pad can not be filled full, post bladdery problem.Bubble can be
Influence etching outline during dry etching, cause undercutting (under cut), PVD deposition not on, and then influence plating
Connection, causes open circuit problem.It in order to solve this problem, can be by improving DAF pad pasting condition, to improve the shape of bubble as far as possible
Condition, but still air bubble problem can be generated by having, and yield is caused to reduce.
In order to solve this problem, the present invention proposes a kind of wafer scale system packaging method, as shown in Figure 1, the method packet
It includes:
Step S1: the first chip is provided；It is formed with the passivation layer with the first opening, on first chip to expose
The first weld pad on first chip；
Step S2: coated polymer layer and solidify the polymeric layer on first chip, to fill described first
Opening；
Step S3: device wafers are provided, first chip for foring polymeric layer is bonded on the device wafers
On；
Step S4: etching the device wafers and the polymeric layer, to form first through hole, exposes first weldering
Pad；
Step S5: plug is formed in the first through hole to be electrically connected with first weld pad.
In the following, being described in detail with reference to Fig. 2A to Fig. 2 I to wafer scale system packaging method of the invention, wherein Tu2AZhi
Fig. 2 I shows the section that wafer scale system packaging method in a specific embodiment of the invention successively implements obtained structure
Schematic diagram.
As an example, the wafer scale system packaging method of the embodiment of the present invention, comprising the following steps:
Firstly, executing step S1, the first chip is provided；The passivation with the first opening is formed on first chip
Layer, to expose the first weld pad 1011 on first chip.
Specifically, in an example of the invention, as shown in Fig. 2A and Fig. 3 A, Fig. 3 A is first chip in Fig. 2A
101 enlarged drawing；First wafer 100 is provided, is formed with the first chip 101 on first wafer 100, on first chip
It is formed with the passivation layer with the first opening, to expose the first weld pad 1011 on first chip.
Optionally, first wafer 100 can be carrying wafer, and the carrying wafer includes semiconductor substrate, is partly led
Body substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP,
InGaAs or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted, or are insulator
Silicon (SSOI) is laminated on upper silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Illustratively, multiple first chips 101 being spaced each other are formed on the carrying wafer.
Illustratively, in embodiments of the present invention involved in chip (such as first chip 101 and subsequent refer to
The second chip) can be any one semiconductor chip, may include memory, logic circuit, power device, bipolar device
The active devices such as part, individual MOS transistor, MEMS (MEMS), are possibly even the phototubes such as light emitting diode
Part may be passive device, such as resistance, capacitor etc..
Wherein, first chip 101 can be arranged on the carrying wafer by adhesive layer 103, namely described
Adhesive layer 103 is provided between first chip 101 and the substrate, first chip 101 is bonded on the carrying wafer.
Or first chip 101 is formed directly on first wafer 100, it is not limited to it is a certain, it is not limited here.
Wherein, it is formed with passivation layer on first chip 101, there is the first opening in the passivation layer, to expose
The first weld pad 1011 on first chip 101, to realize subsequent electric connection.
Optionally, the passivation layer includes the first passivation layer 1012 and the second passivation layer 1013 sequentially formed, such as Fig. 3 A
It is shown.
Wherein, the critical size of 1012 split shed of the first passivation layer is less than 1013 split shed of the second passivation layer
Critical size, and then narrow wide first opening under formation, the shape of first opening are not limited to a certain kind.
Further, first passivation layer 1012 and the second passivation layer 1013 can select identical or different material.Institute
The material for stating the first passivation layer 1012 and the second passivation layer 1013 includes oxide, nitride etc..
In one embodiment of this invention, the first passivation layer 1012 selects SiON, and second passivation layer 1013 selects light
Quick property polymeric material, such as polyimides etc..
Step S2 is executed, coated polymer layer and solidifies the polymeric layer on first chip 101, to fill
State the first opening.
Specifically, as shown in figures 2 b and 3b, Fig. 3 B is the enlarged drawing of dashed region in Fig. 2 B, in first wafer 100
Upper coated polymer layer 102 and curable polymer layer 102, to fill first opening and cover first wafer 100.
Wherein, first opening of the filling of polymeric layer 102, can be filled up completely, can also be partially filled with, be avoided with that can reach
Undercutting is generated when etching to be influenced subject to PVD and subsequent electroplating effect.
It is complete in order to solve the problems, such as to fill when filling the described first opening at present, in an embodiment of the present invention
It selects that mobility is more preferable, the stronger polymeric layer 102 of filling capacity, to be filled up completely first opening, and then avoids filling out
Bubble is generated during filling and avoids generating gap between the polymeric layer 102 and first opening contours, such as Fig. 3 B
It is shown, the effect for influencing subsequent deposition and plating is avoided, solves the problems, such as to generate bubble in filling process, and then prevent from losing
Undercutting (under cut) is generated due to bubble after quarter, avoids conductive material deposition and metal the problem of not connecting, into
One step improves the performance and yield of encapsulation.
In an example of the invention, the polymeric layer 102 include can photoetching photosensitive polymers.In another implementation
In, the polymeric layer 102 includes polyimides, polyparaphenylene's benzo dioxazole etc., and cited material all has good
Mobility, but it is not limited to above-mentioned example.As long as the photosensitive polymers layer 102 has preferable mobility and stronger
Filling capacity can be applied to the application, it is not limited to it is a certain.
In an example of the invention, the polymeric layer is formed on first chip 101 by the method for spin coating
102, wherein the concrete technology of spin coating is referred to conventional technique, and details are not described herein.
Optionally, the polymeric layer 102 is not only filled up completely first opening and also covers 100 shape of the first wafer
At the surface for having the first chip 101, height is greater than the height on 100 surface of the first wafer.For example, showing of the invention one
Example in, the polymeric layer 102 with a thickness of 5 microns -10 microns.
Optionally, the polyimide material has preferable mobility and filling capacity, and hardness is smaller, therefore in order to
It is formed on adhesive layer 103, needs to solidify the polymeric layer 102, to improve the hard of the polymeric layer 102
Degree.
In this embodiment, the polymeric layer 102 is solidified by the method that heating bakes, so that it is formed and improves hard
Degree.Such as in one example, to the polymeric layer 102 150 DEG C -250 DEG C or so at a temperature of heat about 0.5-3 hours
Time so that the polymeric layer 102 solidifies, hardness becomes larger.
After forming the polymeric layer 102, further includes: production second is logical in the polymeric layer 102 of the first opening
Hole 10, with exposure first weld pad 1011.
Specifically, the second through-hole 10 is made in the polymeric layer 102 of the first opening, with exposure first weld pad
1011, as shown in Figure 2 C, the second through-hole bore is less than the first through hole bore that plug is used to form in subsequent step.
Wherein, the polymeric layer 102 has photosensitive property, therefore conventional photolithography method can be selected to the polymerization
Nitride layer 102 carries out photoetching.It selects photolithography method to keep entire technique simpler, reduces cost.
Step S3 is executed, device wafers are provided, first chip 101 for foring polymeric layer 102 is bonded on institute
It states in device wafers.
Specifically, as shown in Figure 2 D, adhesive layer 103 is formed, on first wafer 100 to cover the polymeric layer
102。
Specifically, adhesive layer 103 is formed on first wafer 100, to cover first chip 101 and as envelope
Fill layer.
Wherein, the adhesive layer 103 is formed on the polymeric layer 102, and the adhesive layer 103 is used for described first
Wafer 100 and the device wafers of subsequent offer are bonded together, and are formed and first chip 101 in the adhesive layer
The plug of interconnection.
In addition, the adhesive layer 103 can also play fixed function to the first chip 101, and be capable of providing physics and
Electic protection prevents external interference.
Optionally, the adhesive layer 103 can be organic film, and organic film may include various organic films, such as
Chip connects film (die attach film, DAF), dry film (dry film) etc., and the thickness of adhesive layer is set as needed,
And the number of plies of adhesive layer 103 is also not necessarily limited to one layer, and can be two or more layers.
Polymeric layer 102 is being carried out to form the adhesive layer 103 on the polymeric layer 102 again after photoetching,
When forming the adhesive layer 103, the adhesive layer 103 is simultaneously not filled with second through-hole, is only covered in the polymeric layer 102
Surface.
On first wafer 100 formed adhesive layer 103 before further include first weld pad executed to exposing
1011 the step of being detected, re-formed adhesive layer 103 after first weld pad 1011 detection passes through.
Fig. 2 E is please referred to, first wafer 100 is cut, to obtain several crystal grain comprising first chip 101.
In the present embodiment, after forming adhesive layer, first wafer 100 is cut, as shown in Figure 2 E, the will be integrated in
Multiple chip separations on one wafer 100 are unit 110 independent, for example, each unit 110 include at least one the
One chip 101, the unit 110 form the system or subsystem that can provide multiple functions, which depends on practical integrated
Chip function.
Then as shown in Figure 2 F, device wafers 200 are provided, first chip 101 for foring polymeric layer 102 is connect
It closes in the device wafers 200.
Specifically, the crystal grain comprising first chip 101 is bonded on the first surface of the device wafers 200.
In the present embodiment, the second chip 201, second core are formed on the first surface of the device wafers 200
The second weld pad is formed on piece 201；First chip 101 is bonded in the device wafers 200 through the adhesive layer 103
The side of second chip 201.
In the present embodiment, multiple second cores being spaced each other are provided within the first surface of the device wafers 200
Piece 201.
Device wafers 200 are to complete element manufacturing, are formed with the device wafers 200 of multiple second chips 201.The device is brilliant
Circle 200 can be made of production of integrated circuits technology according to corresponding layout-design, such as be led on a semiconductor wafer
Cross the interconnection layer that the work such as deposition, etching form the device of NMOS and/or PMOS etc. and dielectric layer and metal layer are constituted
With the structures such as pad being located on interconnection layer, to make the second chip 201 being arranged in array in semiconductor crystal wafer.
Specifically, device wafers 200 include semiconductor substrate, and semiconductor substrate can be in the following material being previously mentioned
At least one: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compounds are partly led
Body further includes the multilayered structure etc. that these semiconductors are constituted, or for silicon is laminated on silicon-on-insulator (SOI), insulator
(SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on insulator
(GeOI) etc..
Wherein, second chip 201 is embedded in the front of the device wafers 200.
It is noted that the second chip 201 can also be the multiple and different knots being formed within 200 front of device wafers
The chip of structure, the different chip of function.
Illustratively, both the first chip 101 and the second chip 201 are also possible to the identical chip of structure and function.
Then the crystal grain comprising first chip 101 is bonded in the device wafers 200 through the adhesive layer 103
It is formed on the first surface of second chip 201.
Wherein, the relative position of the second chip 201 and the first chip 101 can carry out reasonable according to type of device and size
Setting, for example, first chip 101 and 201 top and the bottom of the second chip can be made to be overlapped, alternatively, described second
The region except first chip 101 is arranged in chip 201, so that second chip 201 and the first chip 101 are completely wrong
It opens, in order to the execution of subsequent plug process.
After by the first surface of the grain bonding to the device wafers 200, the method is also further wrapped
It includes: overturning the device wafers 200, so that the second surface of the device wafers 200 is upward, and to device wafers 200
Second surface, such as the back side carry out reduction process, as shown in Figure 2 G, so that the thickness of the device wafers 200 after being thinned reaches mesh
Scale value.
It is noted that in the present invention, the thickness of the wafer after being thinned, can also for example between 10 μm to 100 μm
To adjust accordingly to the thickness, be not specifically limited herein according to the difference of technology node.
In one example, the step of carrying out reduction process to the back side of device wafers 200 includes: with first wafer
100 be support substrate, directly carries out reduction process or being additionally provided support substrate (not shown), in one example, can be with
The first wafer 100 and device wafers 200 are engaged first, after carrying out the engagement step, to 200 back side of device wafers
Reduction process is carried out, so that the thickness of the device wafers 200 after being thinned reaches target value.
After by the first surface of the grain bonding to the device wafers 200, further includes: brilliant in the device
Injection molded layers 202 are formed on the first surface of circle 200, to cover the first table of first chip 101 and the device wafers 200
Face further fixes the first chip 101, protect the first chip 101 not contaminated etc., and can be supported for follow-up process.
Wherein, the relative position of the second chip 201 and the first chip 101 can carry out reasonable according to type of device and size
Setting, for example, first chip 101 and 201 top and the bottom of the second chip can be made to be overlapped, alternatively, described second
The region except first chip 101 is arranged in chip 201, so that second chip 201 and the first chip 101 are completely wrong
It opens, in order to the execution of subsequent plug process.
After by the first table of the grain bonding to the device wafers 200, the method be may further comprise:
Injection molded layers 202 are formed on the first surface of the device wafers 200, it is brilliant to cover first chip 101 and the device
The first surface of circle 200.The first chip 101 is further fixed, the first chip 101 of protection does not receive pollution etc., and can be subsequent
Processing procedure supports.
It is noted that in the present invention, the thickness of the device wafers 200 after being thinned for example 10 μm to 100 μm it
Between, the thickness can also be adjusted accordingly, be not specifically limited herein according to the difference of technology node.
In one example, the step of carrying out reduction process to the back side of device wafers 200 includes: with first wafer
100 be support substrate, directly carries out reduction process or being additionally provided support substrate (not shown), in one example, can be with
The first wafer 100 and device wafers 200 are engaged first, after carrying out the engagement step, formed before plug, to device
200 back side of part wafer carries out reduction process, so that the thickness of the device wafers 200 after being thinned reaches target value.
It executes step S4 and etches the device wafers 200 and the polymeric layer 102 as illustrated in figure 2h, to form first
Through-hole exposes first weld pad 1011.
Specifically, in an example of the invention, mask layer is formed and using the mask layer as exposure mask, described in dry etching
The second surface of device wafers 200, the polymeric layer 102 expose first weld pad 1011 to form first through hole 20,
The second surface of device wafers 200 described in dry etching simultaneously, to form third through-hole 30, to expose second weld pad.
Wherein, the first through hole be set to the top of second through-hole and the first through hole bore be greater than it is described
Second through-hole bore, so that the profile of second through-hole is completely covered in the profile of first through hole.
In this step, since the polymeric layer 102 is filled up completely first opening, in the dry etching
In not will form undercut phenomenon, will form the excellent first through hole of profile and third through-hole, to solve current electrical connection
Performance is bad, or even the case where opening.
Step S5 is executed, as shown in figure 2i, forms plug in the first through hole with electric with first weld pad 1011
Connection.
Specifically, in an example of the invention, in the first through hole and the third through-hole formed simultaneously with institute
State the plug 203 that the first weld pad 1011 and second weld pad are electrically connected.
Specifically, conductive material is filled in the first through hole and the third through-hole, to form the first plug and the
Two plugs, respectively with second in the weld pad and the device wafers 200 on the first chip 101 in first wafer 100
Weld pad electrical connection on chip 201.
Specifically, in one example, as shown in figure 2i, filled in the first through hole and the third through-hole conductive
Material is to form spaced multiple plugs.
Wherein, one end of the plug is electrically connected the first weld pad 1011, and the other end is electrically connected the second weld pad.Certainly, described
Plug is also used to be electrically connected in subsequent step with other devices.
Related plug can be metal plug or through silicon via (TSV), metal plug in an embodiment of the present invention
Material can include but is not limited at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al metal, and silicon is logical
The material in hole may include the polysilicon adulterated or undoped polysilicon etc..
The step of forming the plug include:
Seed layer is formed in the first through hole, to cover the surface of the first through hole；
Electroplating technology is executed, to deposit conductive material in the first through hole, to form the plug.
Specifically, the seed layer of deposited metal copper in through-holes first in this step, the deposition method of the seed layer
Chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or atomic layer deposition (ALD) method etc. can be selected.Implement one
In example, pass through the seed layer of physical vapour deposition (PVD) (PVD) method deposited metal copper.
Then it selects the method for Cu electroplating (ECP) to form the metallic copper, optionally, can also be used in plating
Additive, the additive are flat dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
Optionally, the step of can also further including annealing after forming the metallic copper and being formed, annealing can be 80
It is carried out 2-4 hours at DEG C -160 DEG C, to promote copper to recrystallize, long big crystal grain reduces resistance and improves stability.
The electroplating technology may preferably fill through-hole, further avoid generating bubble in through-holes.
Optionally, after forming the first through hole and the third through-hole, the method also includes forming dielectric layer
The step of, wherein the dielectric layer covers the back side of the device wafers 200.In another embodiment, the dielectric layer portions
The first through hole and third through-hole (in being not shown in the figure for the present embodiment) are filled in ground, such as in the first through hole and third
The dielectric layer is formed on the side wall of through-hole and bottom.First through hole is filled at conductive material (such as metal material or polysilicon)
Before third through-hole, the method also includes removing the dielectric layer of the first through hole and third through-hole bottom, simultaneously
Retain the dielectric layer on the side wall of first through hole and third through-hole, for being isolated with the device wafers 200.
Since first through hole bottom can continuously cover first through hole side wall and bottom without undercutting, seed layer or dielectric layer, keep away
Exempted from seed layer or the problem of dielectric layer deposition is discontinuous and metal does not connect, further improve encapsulation performance and
Yield.
Then, step S6 is executed, redistribution interconnection structure is formed, is electrically connected the plug.
Illustratively, redistribution interconnection structure is formed on the surface that the device wafers 200 are formed with the plug.
Being routed interconnection structure material again can include but is not limited in Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al
At least one metal.The redistribution interconnection structure may include again wiring layer and pad, alternatively, including pad.
In an example of the invention, the redistribution interconnection structure includes pad and is used to be isolated around the pad
The passivation layer of the pad.Optionally, the height of the passivation layer is higher than the height of the pad.
Any suitable method can be used and form the redistribution interconnection structure, for example, forming metal material layer to cover
The second surface of lid device wafers 200, wherein physical gas-phase deposite method (PVD), chemical vapor deposition method can be used
(CVD), it sputters, electrolysis is electroplated, electrodeless plating technique or other suitable metal deposition process form the metal material
Layer, then the part metal material layer is removed by the method for etching, to form spaced multiple redistribution interconnection structures.
So far, the introduction for completing the committed step of the method engaged to two wafers of the invention, for complete
After the completion of the step of method is also possible that other, such as encapsulation, cutting technique can also be carried out to wafer along Cutting Road, it will
The multiple chip separations being integrated on wafer are unit independent, such as each unit includes at least one first chip
101 form the system or subsystem that can provide multiple functions at least one second chip, the unit, which depends on
The actually function of integrated chip.
The method of wafer-level packaging chip through-hole interconnection of the invention, described first during forming through-hole interconnection
Coated polymer layer 102 and solidify the polymeric layer 102 on chip 101, to fill first opening, wherein described poly-
Closing nitride layer 102 has good mobility, can completely in opening in the filling passivation layer and be avoided that generation bubble,
It solves the problems, such as to generate bubble in filling process, and then prevents from generating undercutting (under cut) due to bubble after the etching,
Conductive material deposition and metal the problem of not connecting are avoided, the performance and yield of encapsulation are further improved.
The embodiment of the invention also provides a kind of test method of chip, the test method includes:
First chip is provided, the passivation layer with the first opening is formed on first chip, to expose described the
The first weld pad on one chip；
Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；
The polymeric layer is etched, to form the second opening in the polymeric layer and expose first weldering
Pad；
By first weld pad, functional test is carried out to first chip.
In the following, being described in detail with reference to test method of the Fig. 2A to Fig. 2 C to chip of the invention, wherein Fig. 2A to Fig. 2 C
The test method for showing chip in a specific embodiment of the invention successively implements the diagrammatic cross-section of obtained structure.
As an example, the test method of the chip of the embodiment of the present invention, comprising the following steps:
Firstly, executing step 1, the first chip 101 is provided；It is formed on first chip 101 with the first opening
Passivation layer, to expose the first weld pad 1011 on first chip 101.
Specifically, in an example of the invention, as shown in Fig. 2A and Fig. 3 A, the first wafer 100 is provided, described first
It is formed with the first chip 101 on wafer 100, is formed with the passivation layer with the first opening, on first chip 101 with dew
The first weld pad 1011 on first chip 101 out.
First wafer 100, the first chip 101 material, structure and position as described in earlier figures 2A, do not do herein superfluous
It states.Illustratively, multiple first chips 101 being spaced each other are formed on the carrying wafer.
Wherein, first chip 101 can be arranged on the carrying wafer by adhesive layer 103, namely described
Adhesive layer 103 is provided between first chip 101 and the substrate, first chip 101 is bonded on the carrying wafer.
Or first chip 101 is formed directly on first wafer, it is not limited to it is a certain, it is not limited here.
Wherein, it is formed with passivation layer on first chip 101, there is the first opening in the passivation layer, to expose
The first weld pad 1011 on first chip 101, to realize subsequent electric connection.
Optionally, the passivation layer includes the first passivation layer 1012 and the second passivation layer 1013 sequentially formed, such as Fig. 3 A
It is shown.
Wherein, the critical size of 1012 split shed of the first passivation layer is less than 1013 split shed of the second passivation layer
Critical size, and then narrow wide first opening under formation, the shape of first opening are not limited to a certain kind.
Further, first passivation layer 1012 and the second passivation layer 1013 can select identical or different material,
In one embodiment of the invention, the first passivation layer 1012 selects SiON, and second passivation layer 1013 selects light sensitivity to polymerize material
Material, such as polyimides etc..
Step 2 is executed, coated polymer layer 102 and solidifies the polymeric layer 102 on first chip 101, with
Fill first opening.
Specifically, as shown in Figure 2 B, coated polymer layer 102 and curable polymer layer on first wafer 100
102, to fill first opening and cover first wafer.
Wherein, first opening of the filling of polymeric layer 102, can be filled up completely, can also be partially filled with, be avoided with that can reach
Undercutting is generated when etching to be influenced subject to PVD and subsequent electroplating effect.
It is complete in order to solve the problems, such as to fill when filling the described first opening at present, in an embodiment of the present invention
It selects that mobility is more preferable, the stronger polymeric layer 102 of filling capacity, to be filled up completely first opening, and then avoids filling out
Bubble is generated during filling and avoids generating gap between the polymeric layer 102 and first opening contours, such as Fig. 3 B
It is shown, the effect for influencing subsequent deposition and plating is avoided, solves the problems, such as to generate bubble in filling process, and then prevent from losing
Undercutting (under cut) is generated due to bubble after quarter, avoids conductive material deposition and metal the problem of not connecting, into
One step improves the performance and yield of encapsulation.
In an example of the invention, the polymeric layer 102 include can photoetching photosensitive polymers.In another implementation
In, the polymeric layer 102 includes polyimides, polyparaphenylene's benzo dioxazole etc., and cited material all has good
Mobility, but it is not limited to above-mentioned example.As long as the photosensitive polymers layer 102 has preferable mobility and stronger
Filling capacity can be applied to the application, it is not limited to it is a certain.
In an example of the invention, the polymeric layer is formed on first chip 101 by the method for spin coating
102, wherein the concrete technology of spin coating is referred to conventional technique, and details are not described herein.
Optionally, the polymeric layer 102 is not only filled up completely first opening and also covers 100 shape of the first wafer
At the surface for having the first chip 101, height is greater than the height on 100 surface of the first wafer.For example, showing of the invention one
Example in, the polymeric layer 102 with a thickness of 5-10 microns.
Optionally, the polyimide material has preferable mobility and filling capacity, and hardness is smaller, therefore in order to
It is formed on adhesive layer 103, needs to solidify the polymeric layer 102, to improve the hard of the polymeric layer 102
Degree.
In this embodiment, the polymeric layer 102 is solidified by the method that heating bakes, so that it is formed and improves hard
Degree.Such as in one example, to the polymeric layer 102 150 DEG C -250 DEG C or so at a temperature of heat about 0.5-3 hours
Time so that the polymeric layer 102 solidifies, hardness becomes larger.
Step 3 is executed, the polymeric layer 102 is etched, is opened with forming second in the polymeric layer 102
Mouth simultaneously exposes first weld pad 1011, to carry out weld pad test.
Specifically, the second opening of production in the polymeric layer 102 of the first opening, with exposure first weld pad
1011, as shown in Figure 2 C, the second opening bore is less than the first through hole bore that plug is used to form in subsequent step.
Wherein, the polymeric layer 102 has photosensitive property, therefore conventional photolithography method can be selected to the polymerization
Nitride layer 102 carries out photoetching.It selects photolithography method to keep entire technique simpler, reduces cost.
After exposing first weld pad, weld pad test is carried out to first weld pad, weld pad test is to send out in time
A kind of test mode of existing problem, and the more defective products of prevention generate a kind of necessary means for reducing loss.In the weld pad
The test signal that tooling can be will test in test is connect by test point with tested wiring board, and detection needs the signal verified,
It is middle to need the signal verified that be selected or be designed according to actual needs, it is not limited to a certain.
The test method of chip of the invention coats polymerization during forming through-hole interconnection on first chip
Nitride layer simultaneously solidifies the polymeric layer, to fill first opening, wherein and the polymeric layer has good mobility,
Can completely in opening in the filling passivation layer and be avoided that generation bubble, after to polymeric layer patterning
Expose first weld pad and weld pad test is carried out to first weld pad, by the first weld pad, judges the first wafer electricity
Property, function etc. it is whether good, measurement can be impacted to avoid bubble is generated, the accuracy of chip testing can be improved, with
Further increase the performance and yield of encapsulation.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (19)
1. a kind of method of wafer-level packaging chip through-hole interconnection, which is characterized in that the described method includes:
First chip is provided；It is formed with the passivation layer with the first opening, on first chip to expose first core
First weld pad of on piece；
Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；
Device wafers are provided, first chip for foring polymeric layer is bonded in the device wafers；
The device wafers and the polymeric layer are etched, to form first through hole, expose first weld pad；
Plug is formed in the first through hole to be electrically connected with first weld pad.
2. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that the polymeric layer
Including polyimides, polyparaphenylene's benzo dioxazole.
3. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that the polymeric layer
Including can photoetching photosensitive polymers.
4. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that the polymer
Layer carries out heated baking, to solidify the polymeric layer.
5. the method according to claim 1, wherein the polymeric layer with a thickness of 5-10 microns.
6. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that by the polymerization
It further include making the second through-hole in the polymeric layer of the first opening before nitride layer is bonded in the device wafers, with
Exposure first weld pad, the second through-hole bore are less than the first through hole bore.
7. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that described to provide first
Chip includes:
First wafer is provided, first chip is formed on first wafer.
8. the method for wafer-level packaging chip through-hole interconnection according to claim 7, which is characterized in that by described first
Before chip and device wafers engagement, the method also includes:
First wafer is cut, to obtain several crystal grain comprising first chip, first chip will be included
Crystal grain is bonded on the first surface of the device wafers.
9. the method for wafer-level packaging chip through-hole interconnection according to claim 8, which is characterized in that etch the device
Before wafer, the method also includes:
Injection molded layers are formed on the first surface of the device wafers, to cover the of first chip and the device wafers
One surface；
And/or the overturning device wafers.
10. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that the method is also
Include:
After first chip for foring polymeric layer is bonded in the device wafers, the device wafers are held
Row reduction process.
11. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that etch the device
Part wafer includes:
Mask layer and using the mask layer as exposure mask is formed, device wafers described in dry etching expose institute to form first through hole
State the first weld pad.
12. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that connected by chip
At least one of film and dry film are connect, first chip for foring polymeric layer is bonded in the device wafers.
13. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that form described insert
After plug the method also includes:
Redistribution interconnection structure is formed, the plug is electrically connected, wherein the redistribution interconnection structure includes wiring layer and weldering again
Disk, alternatively, including pad.
14. the method for wafer-level packaging chip through-hole interconnection according to claim 1, which is characterized in that described first
Seed layer is formed in through-hole, to cover the surface of the first through hole；
Electroplating technology is executed, to deposit conductive material in the first through hole, to form the plug.
15. a kind of test method of chip, which is characterized in that the test method includes:
The first wafer is provided, first wafer includes the first chip, is formed on first chip with the first opening
Passivation layer, to expose the first weld pad on first chip；
Coated polymer layer and solidify the polymeric layer on first chip, to fill first opening；
The polymeric layer is etched, to form the second opening in the polymeric layer and expose first weld pad；
By first weld pad, functional test is carried out to first chip.
16. the test method of chip according to claim 15, which is characterized in that the polymeric layer includes polyamides Asia
Amine, polyparaphenylene's benzo dioxazole.
17. the test method of chip according to claim 15, which is characterized in that the polymeric layer be can photoetching light
Sensitive polymer.
18. the test method of chip according to claim 15, which is characterized in that carry out heating baking to the polymeric layer
Roasting, to solidify the polymeric layer.
19. the test method of chip according to claim 15, which is characterized in that the polymeric layer with a thickness of 5-10
Micron.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114758962A (en) * | 2022-04-06 | 2022-07-15 | 北京燕东微电子科技有限公司 | Method for manufacturing chip |
| CN116705625A (en) * | 2023-08-02 | 2023-09-05 | 北京大学 | Wafer packaging method, structure and device based on DAF film |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856279A (en) * | 2011-06-28 | 2013-01-02 | 台湾积体电路制造股份有限公司 | Interconnect structure for wafer level package |
| CN105244341A (en) * | 2015-09-01 | 2016-01-13 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device FOWLP packaging structure and manufacturing method thereof |
| CN107406590A (en) * | 2015-01-27 | 2017-11-28 | 东丽株式会社 | Resin, photosensitive polymer combination and their electronic unit, display device are used |
| CN108470722A (en) * | 2018-04-17 | 2018-08-31 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and forming method thereof |
| CN207909859U (en) * | 2017-12-01 | 2018-09-25 | 华进半导体封装先导技术研发中心有限公司 | A kind of high-density package structure |
| CN108666264A (en) * | 2017-09-30 | 2018-10-16 | 中芯集成电路（宁波）有限公司 | Wafer scale system encapsulating method and structure |
| CN109860064A (en) * | 2018-12-21 | 2019-06-07 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
-
2019
- 2019-07-16 CN CN201910642140.1A patent/CN110379767B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856279A (en) * | 2011-06-28 | 2013-01-02 | 台湾积体电路制造股份有限公司 | Interconnect structure for wafer level package |
| CN107406590A (en) * | 2015-01-27 | 2017-11-28 | 东丽株式会社 | Resin, photosensitive polymer combination and their electronic unit, display device are used |
| CN105244341A (en) * | 2015-09-01 | 2016-01-13 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor device FOWLP packaging structure and manufacturing method thereof |
| CN108666264A (en) * | 2017-09-30 | 2018-10-16 | 中芯集成电路（宁波）有限公司 | Wafer scale system encapsulating method and structure |
| CN207909859U (en) * | 2017-12-01 | 2018-09-25 | 华进半导体封装先导技术研发中心有限公司 | A kind of high-density package structure |
| CN108470722A (en) * | 2018-04-17 | 2018-08-31 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and forming method thereof |
| CN109860064A (en) * | 2018-12-21 | 2019-06-07 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114758962A (en) * | 2022-04-06 | 2022-07-15 | 北京燕东微电子科技有限公司 | Method for manufacturing chip |
| CN116705625A (en) * | 2023-08-02 | 2023-09-05 | 北京大学 | Wafer packaging method, structure and device based on DAF film |
| CN116705625B (en) * | 2023-08-02 | 2023-10-20 | 北京大学 | Wafer packaging method, structure and device based on DAF film |
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