CN110379452B - Anti-fuse cell circuit and integrated chip - Google Patents
Anti-fuse cell circuit and integrated chip Download PDFInfo
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- CN110379452B CN110379452B CN201910668960.8A CN201910668960A CN110379452B CN 110379452 B CN110379452 B CN 110379452B CN 201910668960 A CN201910668960 A CN 201910668960A CN 110379452 B CN110379452 B CN 110379452B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
Abstract
The invention discloses an anti-fuse cell circuit and an integrated chip, wherein the anti-fuse cell circuit comprises a programming unit and a detection unit, wherein the programming unit is used for programming an anti-fuse cell according to programming voltage and enabling voltage; the detection unit is used for detecting the working current of the anti-fuse cell and generating working voltage according to the working current; generating a feedback voltage when the working voltage is greater than a preset voltage threshold; the programming unit is also used for finishing programming when receiving the feedback voltage. The programming time of the anti-fuse cells in the technical scheme of the invention is variable and is determined according to the time required by programming of each anti-fuse cell, compared with the traditional fixed programming period, the programming period of the anti-fuse cells in the technical scheme of the invention is greatly shortened, and meanwhile, the circuit loss in the programming process is reduced due to the shortened period.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to an antifuse cell circuit and an integrated chip.
Background
An antifuse (Anti-fuse) is a one-time programmable nonvolatile integrated chip (OTP Memory) widely used in various IC chips, such as sensor ICs, display driver ICs, power management ICs, radio frequency identification chip Sets (RFIDs), etc., to improve yield, ensure high performance of the chip, and provide design flexibility. The general unprogrammed antifuse has a very high impedance (greater than 1G ohm) characteristic, and the impedance thereof is greatly reduced to a range of 10K Ω after a breakdown phenomenon occurs by programming a high voltage VPP >6.6V, so that a digital signal storing a logic 0 or a logic 1 can be designed by utilizing the characteristic that the impedance is greatly changed before and after programming. It follows that programming is the most important step in the anti-fuse circuit to collapse. The design of the antifuse cell circuit directly affects the success or failure and performance of the antifuse cell circuit.
Referring to fig. 1, a conventional program Cell, an "anti-fuse Cell (Cell), is a 3T architecture (a three-dimensional (3T) architecture). The architecture consists of three MOS transistors, MP1 serving as an antifuse, typically a P-type MOS transistor, having its drain and source connected to a programming voltage VPP, and its gate connected to node a. MN1 is an N-type MOS transistor with high voltage isolation function, its drain is connected to node A, its source is connected to node B, and its gate is connected to VDDB (3.3V). MN2 is an N-type MOS transistor functioning as a programming switch, having its drain connected to node B, its source connected to ground, and its gate connected to a programming signal PG. When PG is high, MN2 switch is turned on, and point A is pulled down to control, so that anti-fuse MP1 bears 6.6V voltage to generate breakdown. MN2 is turned off when PG is low and is not programmed. The program signal PG is usually a single pulse signal with a constant time interval T being high, during which the programming is performed.
Referring to fig. 2 and 3, because the current carrying capability of the circuit is limited, the anti-fuse cells in all the arrays cannot be programmed at one time, and thus the circuit is burned out due to excessive current. Normally, one antifuse cell is programmed at a time, and antifuse cell 0, antifuse cell 1, antifuse cell 2 …, and antifuse cell n are programmed sequentially in a sequential programming manner. The PG0 PGn signals are generated by an external processor. First, the pulse of PG0 is generated first, and the anti-fuse cell 0 is programmed in the time interval T, and after the pulse of PG0 is finished, the pulse of PG1 is generated next, and the anti-fuse cell 1 is programmed in the time interval T. After PG1 pulse ends, PG2 pulse is then generated to program antifuse cell 2 in time interval T. And programming the anti-fuse cells in the array one by one according to the principle until the last anti-fuse cell n is programmed to finish the programming procedure of the whole array.
The above conventional method has the following disadvantages: the duration T of PG being high is the programming time, which is usually set to the "longest" time under the worst case conditions for antifuse breakdown to ensure successful programming of each antifuse cell. However, in an antifuse array, if each antifuse cell is programmed with the "longest" time, it will waste much time. Therefore, the traditional programming circuit has the problem of long programming time.
Disclosure of Invention
The present invention provides an anti-fuse cell circuit, which is aimed at increasing the programming speed of anti-fuse.
In order to achieve the above object, the anti-fuse cell circuit of the present invention includes a programming unit and a detecting unit; wherein
The programming unit is used for programming the anti-fuse cell according to a programming voltage and an enabling voltage;
the detection unit is used for detecting the working current of the anti-fuse cell and generating working voltage according to the working current; generating a feedback voltage when the working voltage is greater than a preset voltage threshold;
the programming unit is also used for finishing programming when receiving the feedback voltage.
Preferably, the detection unit comprises a sampling circuit, a switch circuit, a voltage division circuit and a logic circuit; wherein
The sampling circuit is used for detecting the working current of the anti-fuse cell and generating working voltage according to the working current;
the switching circuit is used for being started when the working voltage is greater than a preset voltage threshold;
the voltage division circuit is used for receiving the programming voltage input by the programming unit when the switch circuit is started, and dividing the programming voltage to obtain a sampling voltage;
and the logic circuit is used for generating feedback voltage after performing logic operation on the sampling voltage and the enabling voltage.
Preferably, the programming circuit comprises a first PMOS transistor, a first NMOS transistor and a second NMOS transistor; wherein
The drain electrode and the source electrode of the first PMOS tube are connected, the drain electrode and the source electrode also receive programming voltage, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with a power supply, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the detection unit, and the source electrode of the second NMOS tube is grounded.
Preferably, the sampling circuit includes a current detection resistor, a first end of the current detection resistor is connected to the gate of the first PMOS transistor, and a second end of the current detection resistor is connected to the drain of the first NMOS transistor.
Preferably, the switch circuit includes a second PMOS transistor, a gate of the second PMOS transistor is connected to the second end of the current detection resistor, a source of the second PMOS transistor is connected to the gate of the first PMOS transistor, and a drain of the second PMOS transistor is connected to the voltage divider circuit.
Preferably, the voltage division circuit comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; wherein
The grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube is grounded.
Preferably, the logic circuit comprises an exclusive or gate, a first input terminal of the exclusive or gate receives the enable voltage, a second input terminal of the exclusive or gate receives the sampling voltage, and an output terminal of the exclusive or gate is connected with the programming unit.
Preferably, the detection unit further includes a latch output circuit; and the latch output circuit is used for amplifying and latching the sampling voltage and outputting the amplified and latched sampling voltage to an external processor.
Preferably, the latch output circuit comprises a first not gate, a second not gate and a latch; the input end of the first NOT gate is connected with the voltage division circuit, the output end of the first NOT gate is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with the input end of the latch, and the output end of the latch is connected with an external processor.
In order to achieve the above object, the present invention further provides an integrated chip including the antifuse cell circuit as described above.
According to the technical scheme, the programming unit and the detection unit are arranged, so that the anti-fuse cell circuit is formed. The programming unit programs the anti-fuse cell according to the programming voltage and the enabling voltage, the detection unit detects the working current of the anti-fuse cell and generates the working voltage according to the working current; and generating a feedback voltage when the working voltage is greater than a preset voltage threshold, and finishing programming when the programming unit receives the feedback voltage. The programming time of the anti-fuse cells in the technical scheme of the invention is variable and is determined according to the time required by programming of each anti-fuse cell, compared with the traditional fixed programming period, the programming period of the anti-fuse cells in the technical scheme of the invention is greatly shortened, and meanwhile, the circuit loss in the programming process is reduced due to the shortened period.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional 3T antifuse cell structure;
FIG. 2 is a schematic diagram of a conventional antifuse array;
FIG. 3 is a timing diagram illustrating a conventional anti-fuse array programming;
FIG. 4 is a functional block diagram of an anti-fuse cell circuit according to an embodiment of the present invention;
FIG. 5 is a functional block diagram of an anti-fuse cell circuit according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of an anti-fuse cell circuit according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of an antifuse array according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating programming of an antifuse array according to an embodiment of the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
The invention provides an anti-fuse cell circuit.
Referring to fig. 4, in the embodiment of the invention, the anti-fuse cell circuit includes a programming unit 100 and a sensing unit 200.
The programming unit 100 is configured to program the antifuse cell according to a programming voltage and an enable voltage. The programming voltage and the enable voltage are preset. In one embodiment, the programming voltage is 6.6V, which is valid when the enable voltage is high. In the initial state, the enable voltage is low.
The detection unit 200 is configured to detect a working current of the antifuse cell, and generate a working voltage according to the working current; and generating a feedback voltage when the working voltage is greater than a preset voltage threshold. The programming unit 100 is further configured to end programming when receiving the feedback voltage.
In this embodiment, the detecting unit 200 can monitor the state of the antifuse in real time, detect the antifuse cell in the antifuse array immediately when the antifuse cell is broken during programming, and close the programming switch immediately to end programming
The technical scheme provided by the invention solves the problem that each anti-fuse cell cannot be programmed efficiently in the traditional method. The technology can shorten the programming time of each anti-fuse cell and achieve the purpose of high-speed programming.
According to the technical scheme of the invention, the programming unit 100 and the detection unit 200 are arranged to form the anti-fuse cell circuit. The programming unit 100 programs the antifuse cell according to a programming voltage and an enabling voltage, and the detecting unit 200 detects a working current of the antifuse cell and generates a working voltage according to the working current; when the operating voltage is greater than the preset voltage threshold, a feedback voltage is generated, and the programming unit 100 ends programming when receiving the feedback voltage. The programming time of the anti-fuse cells in the technical scheme of the invention is variable and is determined according to the time required by programming of each anti-fuse cell, compared with the traditional fixed programming period, the programming period of the anti-fuse cells in the technical scheme of the invention is greatly shortened, and meanwhile, the circuit loss in the programming process is reduced due to the shortened period.
Referring to fig. 5, in an embodiment, the detecting unit 200 includes a sampling circuit 210, a switching circuit 220, a voltage dividing circuit 230, and a logic circuit 240; wherein
The sampling circuit 210 is configured to detect a working current of the antifuse cell, and generate a working voltage according to the working current. In this embodiment, the sampling circuit 210 samples the current through the current detection resistor, and the current detection resistor is connected in series in the loop of the current to be detected, so that the voltage drop across the current detection resistor can be obtained through the pre-calculation design because the resistance of the current detection resistor is known.
The switch circuit 220 is configured to turn on when the operating voltage is greater than a preset voltage threshold. When the antifuse is broken down, the resistance thereof is greatly reduced, a large current flows through the current detection resistor, the voltage drop across the current detection resistor is larger than the preset voltage threshold of the switch circuit 220, and the switch circuit 220 is turned on. The switching circuit 220 shunts the large current flowing into the current detection resistor.
The voltage dividing circuit 230 is configured to receive a programming voltage input by the programming unit 100 when the switch circuit 220 is turned on, and divide the programming voltage to obtain a sampling voltage. The voltage divider 230 divides the programming voltage inputted from the switch circuit 220 according to the principle of resistance voltage division.
The logic circuit 240 is configured to perform a logic operation on the sampling voltage and the enable voltage PGEN to generate a feedback voltage. In this embodiment, the logic circuit 240 includes an exclusive or gate XOR, a first input terminal of the exclusive or gate XOR receives the enable voltage PGEN, a second input terminal of the exclusive or gate XOR receives the sampling voltage, and an output terminal of the exclusive or gate XOR is connected to the programming unit 100. Therefore, when one of the sampling voltage and the enable voltage PGEN is at a high level, a high level signal is output.
Referring to fig. 6, the programming circuit includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN 2.
The drain and the source of the first PMOS transistor MP1 are connected, the drain and the source also receive a programming voltage, and the gate of the first PMOS transistor MP1 is connected with the drain of the first NMOS transistor MN 1; the gate of the first NMOS transistor MN1 is connected to a power supply VDDB, the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 is connected to the detection unit 200, and the source of the second NMOS transistor MN2 is grounded.
In this embodiment, "anti-fuse Cell (Cell)" is a 3T architecture (thread transistor structure). The structure is composed of three MOS transistors, the first PMOS transistor MP1 is used as an antifuse and is a P-type MOS transistor, although an N-type MOS transistor can also be used. The drain and source of the first PMOS transistor MP1 are connected to the programming voltage VPP (6.6V), and the gate is connected to N2. The first NMOS transistor MN1 is an N-type MOS transistor with high voltage isolation function, its drain is connected to node N2, its source is connected to node N3, and its gate is connected to power supply VDDB, which is 3.3V in this embodiment. The second NMOS transistor MN2 is an N-type MOS transistor and functions as a programming switch, with the drain connected to node N3, the source connected to ground, and the gate connected to node N4. When the node N4 is turned on, the second NMOS transistor MN2 starts programming, and the node N2 is pulled low, the antifuse first PMOS transistor MP1 is subjected to a 6.6V voltage step, resulting in a breakdown. When the node N4 is low, the second NMOS transistor MN2 is turned off and is not programmed.
Specifically, the sampling circuit 210 includes a current detection resistor Rsense, a first end of the current detection resistor Rsense is connected to the gate of the first PMOS transistor MP1, and a second end of the current detection resistor Rsense is connected to the drain of the first NMOS transistor MN 1.
The switch circuit 220 includes a second PMOS transistor MP2, a gate of the second PMOS transistor MP2 is connected to the second end of the current detection resistor Rsense, a source of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, and a drain of the second PMOS transistor MP2 is connected to the voltage divider circuit 230.
It should be noted that, when the second NMOS transistor MN2 is turned on for programming, the resistance thereof is greatly reduced after the antifuse is broken down, so that a large current I1 flows through the first PMOS transistor MP1, the current detection resistor Rsense, the first NMOS transistor MN1, the second NMOS transistor MN2 to ground. When a large current I1 flows through the current sensing resistor Rsense, a voltage drop is generated, such that the voltage of N1 is greater than the voltage of N2, and the value of the current sensing resistor Rsense is specially designed, such that the voltage difference between the two nodes N1 and N2 is greater than Vth (threshold voltage) of the PMOS transistor, and at this time, the second PMOS transistor MP2 is turned on.
Specifically, the voltage divider circuit 230 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM 6. The gate of the third NMOS transistor NM3 is connected to the drain of the third NMOS transistor NM3, the drain of the third NMOS transistor NM3 is connected to the drain of the second PMOS transistor MP2, and the source of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM 4; a gate of the fourth NMOS transistor NM4 is connected to a drain of the fourth NMOS transistor NM4, and a source of the fourth NMOS transistor NM4 is connected to a drain of the fifth NMOS transistor NM 5; a gate of the fifth NMOS transistor NM5 is connected to a drain of the fifth NMOS transistor NM5, and a source of the fifth NMOS transistor NM5 is connected to a drain of the sixth NMOS transistor NM 6; the gate of the sixth NMOS transistor NM6 is connected to the drain of the sixth NMOS transistor NM6, and the source of the sixth NMOS transistor NM6 is grounded.
When the second PMOS transistor MP2 is turned on, the voltage at the node N5 rises to around 6.6V, and turns on four Diode-connected (Diode-connected) NMOS transistors, including the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6, and a small current I2 flows through the NMOS transistors. In this embodiment, the four NMOS transistors of the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all the same, so that they have the same equivalent impedance, and according to the law of resistance voltage division, the voltage at the node N7 is increased from the low level 0 to about 3.3V, which is one-half of the voltage at the node N5. When the node N7 goes high to 3.3V, the two-terminal input of the XOR goes low at the output node N4 because it is high at the same time, and the second NMOS transistor MN2 is turned off immediately to finish the programming.
Further, the detection unit 200 further includes a latch output circuit 250; the latch output circuit 250 is configured to amplify and latch the sampling voltage and output the amplified and latched sampling voltage to an external processor. In this embodiment, the latch output circuit 250 includes a first not gate INV1, a second not gate INV2, and a latch L1; an input end of the first not gate INV1 is connected to the voltage divider circuit 230, an output end of the first not gate INV1 is connected to an input end of the second not gate INV2, an output end of the second not gate INV2 is connected to an input end of the latch L1, and an output end of the latch L1 is connected to an external processor. The same time that the node N7 rises to 3.3V will also cause the node FIN to go from low to high, which will be immediately latched (Latch) and transmitted to the external processor to inform the external processor that the anti-fuse cell has been programmed.
It is worth noting that a plurality of anti-fuse cells are typically present in a chip. When a plurality of antifuse cells are present, an antifuse array is formed.
Referring to fig. 7 and 8, when PGEN0 goes from low to high, the antifuse cell 0 starts programming, the antifuse in the antifuse cell 0 collapses after a time interval T0, and then programming ends and FIN0 goes high, informing the external processor to start programming the antifuse cell 1; at this time, PGEN1 is raised from low to high, after a time interval of T1, the antifuse in the antifuse cell 1 is broken, and at this time, the programming is finished and FIN1 is pulled to high, informing the external processor to start programming the antifuse cell 2; at this time, PGEN2 goes high from low, and after a time interval T2, the antifuse in the antifuse cell 2 collapses, and the programming is finished and FIN2 goes high, informing the external processor to start programming the next antifuse cell, and so on, and the programming of the whole antifuse array is completed. The programming time of the present technique is found to be significantly shorter than that of the conventional method by T0, T1, and T2 in the timing diagram.
The ultra-fast programming circuit technology of the anti-fuse cell provided by the technical scheme of the invention successfully solves the problem that each anti-fuse cell cannot be programmed efficiently in the traditional method. The technical scheme of the invention can shorten the programming time of each anti-fuse cell and achieve the aim of high-speed programming. Another feature of the present invention is that power consumption during programming is greatly reduced, thereby saving power.
The present invention further provides an integrated chip, which includes an antifuse cell circuit, and the specific structure of the antifuse cell circuit refers to the above embodiments, and since the integrated chip employs all the technical solutions of all the above embodiments, the integrated chip at least has all the beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein.
The integrated chip may be a radio frequency identification chip.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. An anti-fuse cell circuit, comprising a programming unit and a detecting unit; wherein
The programming unit is used for programming the anti-fuse cell according to a programming voltage and an enabling voltage;
the detection unit is used for detecting the working current of the anti-fuse cell and generating working voltage according to the working current; generating a feedback voltage when the working voltage is greater than a preset voltage threshold;
the programming unit is also used for finishing programming when receiving the feedback voltage;
the detection unit comprises a sampling circuit, a switching circuit, a voltage division circuit and a logic circuit;
the sampling circuit is used for detecting the working current of the anti-fuse cell and generating working voltage according to the working current;
the switching circuit is used for being started when the working voltage is greater than a preset voltage threshold;
the voltage division circuit is used for receiving the programming voltage input by the programming unit when the switch circuit is started, and dividing the programming voltage to obtain a sampling voltage;
and the logic circuit is used for generating feedback voltage after performing logic operation on the sampling voltage and the enabling voltage.
2. The antifuse cell circuit of claim 1, wherein the programming unit comprises a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; wherein
The drain electrode and the source electrode of the first PMOS tube are connected, the drain electrode and the source electrode also receive programming voltage, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with a power supply, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the detection unit, and the source electrode of the second NMOS tube is grounded.
3. The antifuse cell circuit of claim 2, wherein the sampling circuit comprises a current detection resistor, a first end of the current detection resistor is connected to the gate of the first PMOS transistor, and a second end of the current detection resistor is connected to the drain of the first NMOS transistor.
4. The antifuse cell circuit of claim 2, wherein the switch circuit comprises a second PMOS transistor, a gate of the second PMOS transistor is connected to the second terminal of the current detection resistor, a source of the second PMOS transistor is connected to the gate of the first PMOS transistor, and a drain of the second PMOS transistor is connected to the voltage divider circuit.
5. The antifuse cell circuit of claim 4, wherein the voltage divider circuit comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; wherein
The grid electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube is grounded.
6. The antifuse cell circuit of claim 5, wherein the logic circuit comprises an exclusive-or gate, a first input of the exclusive-or gate receiving the enable voltage, a second input of the exclusive-or gate receiving the sampling voltage, an output of the exclusive-or gate connected to the programming unit.
7. The antifuse cell circuit of any one of claims 1 to 6, wherein the detection unit further comprises a latch output circuit; and the latch output circuit is used for amplifying and latching the sampling voltage and outputting the amplified and latched sampling voltage to an external processor.
8. The antifuse cell circuit of claim 7, wherein the latch output circuit comprises a first not gate, a second not gate, and a latch; the input end of the first NOT gate is connected with the voltage division circuit, the output end of the first NOT gate is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with the input end of the latch, and the output end of the latch is connected with an external processor.
9. An integrated chip comprising the antifuse cell circuit of any one of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910668960.8A CN110379452B (en) | 2019-07-22 | 2019-07-22 | Anti-fuse cell circuit and integrated chip |
| PCT/CN2019/130111 WO2021012620A1 (en) | 2019-07-22 | 2019-12-30 | Anti-fuse cell circuit and integrated chip |
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| CN201910668960.8A CN110379452B (en) | 2019-07-22 | 2019-07-22 | Anti-fuse cell circuit and integrated chip |
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| CN110379452A CN110379452A (en) | 2019-10-25 |
| CN110379452B true CN110379452B (en) | 2021-04-16 |
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| CN110379452B (en) * | 2019-07-22 | 2021-04-16 | 潍坊歌尔微电子有限公司 | Anti-fuse cell circuit and integrated chip |
| CN112600553A (en) * | 2020-12-18 | 2021-04-02 | 中国电子科技集团公司第四十七研究所 | Programming voltage monitoring circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1289445A (en) * | 1998-09-24 | 2001-03-28 | 爱特梅尔股份有限公司 | Fuse circuit having zero power draw for partially blown condition |
| CN105448332A (en) * | 2014-09-16 | 2016-03-30 | 复旦大学 | Resistive type random access memory and write operation method thereof |
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| US8964444B2 (en) * | 2012-04-25 | 2015-02-24 | Semiconductor Components Industries, Llc | One-time programmable memory, integrated circuit including same, and method therefor |
| CN103066995A (en) * | 2012-12-18 | 2013-04-24 | 南京邮电大学 | High integration density programmable frequency divider unit circuit |
| CN105301483B (en) * | 2014-07-23 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | Detection circuit and method for integrated circuit |
| FR3025927B1 (en) * | 2014-09-12 | 2018-01-12 | St Microelectronics Sa | PROGRAMMING ANTI-FUSIBLE CELLS |
| KR102247562B1 (en) * | 2014-12-15 | 2021-05-03 | 삼성전자 주식회사 | Otp memory capable of performing multi-programing, and semiconductor memory device including the same |
| CN106325900A (en) * | 2015-06-24 | 2017-01-11 | 赵智达 | Design of burner for anti-fuse FPGA (Field Programmable Gate Array) |
| CN107464585B (en) * | 2016-06-06 | 2020-02-28 | 华邦电子股份有限公司 | Electronic fuse device and electronic fuse array |
| CN110379452B (en) * | 2019-07-22 | 2021-04-16 | 潍坊歌尔微电子有限公司 | Anti-fuse cell circuit and integrated chip |
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- 2019-07-22 CN CN201910668960.8A patent/CN110379452B/en active Active
- 2019-12-30 WO PCT/CN2019/130111 patent/WO2021012620A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1289445A (en) * | 1998-09-24 | 2001-03-28 | 爱特梅尔股份有限公司 | Fuse circuit having zero power draw for partially blown condition |
| CN105448332A (en) * | 2014-09-16 | 2016-03-30 | 复旦大学 | Resistive type random access memory and write operation method thereof |
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| WO2021012620A1 (en) | 2021-01-28 |
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