CN110365449B

CN110365449B - Cyclic redundancy check acceleration method and device and access network equipment

Info

Publication number: CN110365449B
Application number: CN201910689549.9A
Authority: CN
Inventors: 翟雄飞; 黄锦华; 李俊; 汪富; 严仲佳; 杨波
Original assignee: Comba Network Systems Co Ltd
Current assignee: Guangzhou Jingxin Communication Technology Co ltd
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2022-05-06
Anticipated expiration: 2039-07-29
Also published as: CN110365449A

Abstract

The application relates to a cyclic redundancy check acceleration method, a cyclic redundancy check acceleration device and access network equipment; the cyclic redundancy check acceleration method implemented from the perspective of a physical layer comprises the following steps: the physical layer sending end analyzes the MAC layer data packet from the media access control layer to obtain first analysis information; completing CRC calculation of the MAC layer data packet based on the first analysis information, attaching a first cyclic redundancy check bit obtained through the CRC calculation to the MAC layer data packet, and sending the MAC layer data packet attached with the first cyclic redundancy check bit to a physical layer receiving end; and the physical layer receiving end compares the first cyclic redundancy check bit with the second cyclic redundancy check bit and completes data reporting according to the comparison result. The method and the device reduce the calculation complexity of the MAC layer and can realize the real-time calculation of the cyclic redundancy check bits of the data.

Description

Cyclic redundancy check acceleration method and device and access network equipment

Technical Field

The present application relates to the field of wireless communications technologies, and in particular, to a method and an apparatus for accelerating cyclic redundancy check, and an access network device.

Background

In modern digital communication systems, errors inevitably occur in data transmission between layers and between devices. To detect this error without spreading it out in the network, 3GPP (3rd Generation Partnership Project) specifies a corresponding cyclic redundancy check for each stage of transmission in a digital communication system.

In the traditional cyclic redundancy check technology, software is generally used for implementing cyclic redundancy check; in the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the system has high real-time requirement on a large data volume, but the traditional method needs to occupy larger operation resources and memory resources of a Central Processing Unit (CPU), which easily causes high CPU logic Processing load, low efficiency and long time.

Disclosure of Invention

In view of the foregoing, it is necessary to provide a cyclic redundancy check acceleration method, apparatus and access network device.

In order to achieve the above object, in one aspect, an embodiment of the present invention provides a cyclic redundancy check acceleration method implemented from a physical layer perspective, including:

the physical layer sending end analyzes the MAC layer data packet from the media access control layer to obtain first analysis information; the MAC layer data packet is a data packet which is constructed by a media access control layer and conforms to an MAC frame structure;

the physical layer sending end completes CRC calculation of the MAC layer data packet based on the first analysis information, attaches a first cyclic redundancy check bit obtained through the CRC calculation to the MAC layer data packet, and sends the MAC layer data packet attached with the first cyclic redundancy check bit to the physical layer receiving end;

the physical layer receiving end analyzes the MAC layer data packet added with the first cyclic redundancy check bit to obtain second analysis information; and based on the second analysis information, completing CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit to obtain a second cyclic redundancy check bit;

and the physical layer receiving end compares the first cyclic redundancy check bit with the second cyclic redundancy check bit and completes data reporting according to the comparison result.

In one embodiment, the first parsing information includes a frame header and a frame body length;

the physical layer sending end analyzes the MAC layer data packet from the media access control layer to obtain first analysis information, and the step of obtaining the first analysis information comprises the following steps:

the physical layer sending end caches the MAC layer data packet, and detects the MAC layer data packet in the cache according to a communication protocol to obtain a frame header;

and the physical layer sending end reads the MAC layer data packet in the cache according to the communication protocol and the frame head to obtain the frame body length.

In one embodiment, the MAC layer data packet comprises a cyclic redundancy check parameter selected by the media access control layer according to a communication protocol; the cyclic redundancy check parameters comprise polynomial length and parallelism;

the physical layer sending end completes the CRC calculation of the MAC layer data packet based on the first analysis information and comprises the following steps:

the physical layer sending end takes out the MAC layer data packet in the cache based on the transmission rate according to the cyclic redundancy check parameter and the first-in first-out rule, calculates the first cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache;

the method comprises the following steps of taking out the MAC layer data packet in the buffer by taking the transmission rate as a reference, and calculating a first cyclic redundancy check bit:

the physical layer sending end confirms whether CRC calculation processing of the MAC layer data packet is finished or not according to the data packet length; the data packet length is obtained according to the overhead of the MAC layer data packet and the frame body length; the MAC layer packet overhead is determined based on the communication protocol.

In one embodiment, the second parsing information includes a frame header and a frame body length;

the physical layer receiving end analyzes the MAC layer data packet with the first cyclic redundancy check bit to obtain second analysis information, and the step of obtaining the second analysis information comprises the following steps:

the physical layer receiving end caches the MAC layer data packet added with the first cyclic redundancy check bit, and detects the MAC layer data packet added with the first cyclic redundancy check bit in the cache according to a communication protocol to obtain a frame header;

and the physical layer receiving end reads the MAC layer data packet with the first cyclic redundancy check bit in the cache according to the communication protocol and the frame head to obtain the frame body length.

the physical layer receiving end completes CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit based on the second analysis information, and the step of obtaining the second cyclic redundancy check bit comprises the following steps:

the physical layer receiving end takes out the MAC layer data packet which is added with the first cyclic redundancy check bit in the cache by taking the transmission rate as a reference according to the cyclic redundancy check parameters and a first-in first-out rule, calculates the second cyclic redundancy check bit and fills the MAC layer data packet to be issued after calculation into the cache;

the method comprises the following steps of taking out the MAC layer data packet with the first cyclic redundancy check bit in the buffer by taking the transmission rate as a reference, and calculating the second cyclic redundancy check bit:

the physical layer receiving end confirms whether CRC calculation processing of the MAC layer data packet added with the first cyclic redundancy check bit is finished or not according to the length of the data packet; the data packet length is obtained according to the overhead of the MAC layer data packet, the length of the first cyclic redundancy check bit and the frame body length; the MAC layer packet overhead is determined based on the communication protocol.

On the other hand, an embodiment of the present invention further provides a cyclic redundancy check acceleration method implemented from the perspective of a media access control layer, including the steps of:

the media access control layer constructs an MAC layer data packet which accords with an MAC frame structure;

the media access control layer sends the MAC layer data packet to the physical layer sending end;

the MAC layer data packet is used for indicating the physical layer sending end to send the MAC layer data packet added with the first cyclic redundancy check bit to the physical layer receiving end; the MAC layer data packet added with the first cyclic redundancy check bit is obtained by adding the first cyclic redundancy check bit to the MAC layer data packet through a physical layer sending end; the first cyclic redundancy check bit is obtained by completing CRC calculation on the basis of first analysis information by an MAC layer data packet through a physical layer sending end; the first analysis information is obtained by analyzing an MAC layer data packet through a physical layer sending end;

the MAC layer data packet added with the first cyclic redundancy check bit is used for indicating a physical layer receiving end to compare the second cyclic redundancy check bit with the first cyclic redundancy check bit and finishing data reporting according to a comparison result; the second cyclic redundancy check bit is obtained by completing CRC calculation on the basis of second analysis information through a physical layer receiving end by an MAC layer data packet added with the first cyclic redundancy check bit; the second analysis information is obtained by analyzing the MAC layer data packet added with the first cyclic redundancy check bit through a physical layer receiving end.

In one embodiment, the media access control layer is implemented based on an ARM architecture; the media access control layer sends the MAC layer data packet to the physical layer sending end through PCIe or parallel interface.

In one embodiment, the MAC layer, constructing the MAC layer packet conforming to the MAC frame structure, includes:

the media access control layer selects a cyclic redundancy check parameter according to a communication protocol, and constructs an MAC layer data packet which accords with an MAC frame structure and vacates a corresponding cyclic redundancy check bit position according to the cyclic redundancy check parameter;

the cyclic redundancy check parameters include polynomial length and parallelism.

A cyclic redundancy check acceleration apparatus implemented from a physical layer perspective, comprising:

the system comprises a sending end cyclic redundancy check module, a receiving end cyclic redundancy check module and a transmitting end cyclic redundancy check module, wherein the sending end cyclic redundancy check module is used for analyzing an MAC layer data packet from a media access control layer to obtain first analysis information; the MAC layer data packet is a data packet which is constructed by a media access control layer and conforms to an MAC frame structure; and completing CRC calculation of the MAC layer data packet based on the first analysis information, attaching a first cyclic redundancy check bit obtained through the CRC calculation to the MAC layer data packet, and sending the MAC layer data packet attached with the first cyclic redundancy check bit to a physical layer receiving end;

the receiving end cyclic redundancy check module is used for analyzing the MAC layer data packet which is received by the physical layer receiving end and is added with the first cyclic redundancy check bit to obtain second analysis information; and based on the second analysis information, completing CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit to obtain a second cyclic redundancy check bit; and comparing the first cyclic redundancy check bit with the second cyclic redundancy check bit, and finishing data reporting according to the comparison result.

A cyclic redundancy check acceleration apparatus implemented from a media access control layer perspective, comprising:

the MAC layer construction data packet module is used for constructing an MAC layer data packet which accords with an MAC frame structure;

the MAC layer data sending module is used for sending the MAC layer data packet to the physical layer sending end;

An access network device comprises a CPU and a Field-Programmable Gate Array (FPGA) connected with the CPU;

the CPU is used for executing the steps of any cyclic redundancy check acceleration method implemented from the perspective of a media access control layer;

the FPGA is used for executing the steps of any cyclic redundancy check acceleration method implemented from the perspective of a physical layer.

In one embodiment, the access network device is a base station; the base stations comprise macro base stations, micro base stations, pico base stations and pico base stations.

In one embodiment, the CPU is connected to the FPGA through PCIe or parallel port.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any of the above.

One of the above technical solutions has the following advantages and beneficial effects:

the Media Access Control (MAC) layer constructs a data packet conforming to an MAC frame structure according to a communication protocol and issues the data packet to a physical layer; then, the physical layer analyzes the content of the MAC layer data packet and calculates the cyclic redundancy check bit of the data in real time; enabling the physical layer to cooperate with the MAC, and enabling the physical layer to understand the communication protocol of the MAC; the method and the device sink the function of calculating the cyclic redundancy check of the MAC layer to the physical layer for calculation, reduce the calculation burden of the MAC by utilizing the abundant logical resources of the physical layer, reduce the calculation complexity of the MAC layer and realize the real-time calculation of the cyclic redundancy check bit of the data; according to the method and the device, the cyclic redundancy check parameters are reasonably selected, and the real-time performance and effectiveness of the calculation of the cyclic redundancy check bits in the data are improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic flow chart diagram of a cyclic redundancy check acceleration method implemented from a physical layer perspective in one embodiment;

FIG. 2 is a schematic flow chart diagram of a cyclic redundancy check acceleration method implemented from the perspective of a MAC layer in one embodiment;

FIG. 3 is a schematic flow chart diagram of a cyclic redundancy check acceleration method implemented from the perspective of a base station in one embodiment;

FIG. 4 is a block diagram of a CRC accelerator implemented from a physical layer perspective in one embodiment;

FIG. 5 is a block diagram of a CRC accelerator implemented from the perspective of the MAC layer in one embodiment;

FIG. 6 is a block diagram of a CRC accelerator implemented from the perspective of a base station in one embodiment;

fig. 7 is a schematic diagram of an accelerated crc procedure applied to an access network device in an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The conventional cyclic redundancy check technology mainly comprises two key technical points: 1. selecting cyclic redundancy check parameters; 2. the cyclic redundancy check is implemented. Aiming at the key technical point 1: the number of the cyclic redundancy check parameters to be selected is two, namely the cyclic redundancy check digit sum generating polynomial. The former basically determines the performance and implementation complexity of the cyclic redundancy check as a whole, and generally, the longer the number of cyclic redundancy check bits is, the better the performance is and the greater the implementation complexity is. The latter ensures the randomness of the cyclic redundancy check and also ensures the performance of the cyclic redundancy check to a certain extent. Aiming at the key technical point 2: in the conventional method, software is used for implementing cyclic redundancy check, a large lookup table needs to be maintained, so that a large operation resource and a large memory resource for a CPU need to be occupied, and meanwhile, the time delay is large, which is easy to become a bottleneck of system performance, and the system performance is reduced.

The method and the device have the advantages that the cyclic redundancy check function is put down to the physical layer, so that the calculation burden of the MAC layer is reduced, and the calculation performance of the MAC layer is improved; according to the method and the device, the cyclic redundancy check is implemented by using the physical layer based on the FPGA chip, so that the time delay of calculating the cyclic redundancy check bit can be effectively reduced, and the overall time delay performance of the system is improved.

The cyclic redundancy check acceleration method provided by the application can be applied to a wireless communication system, and is particularly suitable for cyclic redundancy check in a microwave communication system. In particular, the method can be suitable for 5G (5th generation mobile networks) millimeter wave systems, and has a wide application prospect.

In one embodiment, as shown in fig. 1, a cyclic redundancy check acceleration method is provided, which is described by taking the method as an example of being applied to a physical layer, and includes the following steps:

step S102, a physical layer sending end analyzes an MAC layer data packet from a media access control layer to obtain first analysis information;

the MAC layer data packet is a data packet which is constructed by a media access control layer and conforms to an MAC frame structure.

Specifically, after receiving an MAC layer packet transmitted by a media access control layer, a physical layer transmitting end needs to perform parsing, for example, parse a packet sent by an MAC layer according to a communication protocol; in a specific example, the variables that need to be resolved (i.e., the first resolution information) may include: the frame head of the MAC layer data packet and the frame body length of the MAC layer data packet. It should be noted that the communication protocol in the present application is related to the communication system of a specific application. The method can be realized by combining with a specific communication system protocol, and two specialties of an MAC layer and a physical layer are required to be matched with each other.

The frame header of each MAC data packet represents the initial position of each MAC layer data packet and is also a separation point of each MAC layer data packet; the frame body length of the MAC layer packet indicates a data length of each MAC layer packet except for overhead.

For example: the header of the MAC layer packet may be represented by 16 special bits, and if hexadecimal numbers are used to represent the header, 0x4859 may be used to represent the header; and the frame body length of the MAC layer packet can be expressed by 12 bits, so the frame body length is 8192 bytes at most.

Further, in a specific embodiment, the step of the physical layer sending end analyzing the MAC layer packet from the media access control layer to obtain the first analysis information may include:

Specifically, a physical layer sending end caches a data packet sent by an MAC layer, and detects a frame header and a corresponding frame length of the MAC layer data packet; in a specific example, the physical layer sending end first identifies a delimiter (i.e., a frame header) in the MAC layer packet, and then analyzes the frame body length of the MAC layer packet according to the structure of the MAC layer packet.

It should be noted that, in practical applications, data is sent little by little, and the header of the data packet has a certain length. For example, when data is transmitted, 1bit is transmitted each time, and the frame header has 10 bits; for this application, the data packet sent by the MAC layer is buffered, for example, 10-bit data must be buffered, and then it is determined whether the 10bit is the frame header, instead of determining whether 1bit is received, so as to improve the parsing efficiency.

The frame header of the MAC layer data packet and the information position indicating the length of the frame body can be determined according to the communication protocol. For example: the header of the frame is defined as 0x4859 in the communication protocol, and when the physical layer detects that a certain 16 consecutive bits are equal to 0x4859, it is considered as the start position of a MAC layer packet. Meanwhile, according to the specification of the communication protocol, the 5th and 6 th bytes from the frame header indicate the length of the frame body, so that the physical layer can read the frame body length of the current MAC layer packet at the corresponding position.

Step S104, the physical layer sending end completes CRC calculation of the MAC layer data packet based on the first analysis information, attaches a first cyclic redundancy check bit obtained through CRC calculation to the MAC layer data packet, and sends the MAC layer data packet attached with the first cyclic redundancy check bit to the physical layer receiving end.

Specifically, the physical layer transmitting end obtains the length of the MAC packet and performs a corresponding CRC operation on the MAC packet. After detecting the frame header of the MAC layer data packet and obtaining the data packet length, the physical layer sending end realizes the gradual calculation of the cyclic redundancy check bit while sending the MAC layer data packet according to the cyclic redundancy check parameter (the parameter is obtained by the media access control layer, namely the MAC layer according to the selection of the communication protocol) contained in the MAC layer data packet; according to the method and the device, the cyclic redundancy check parameters are reasonably selected, and the real-time performance and effectiveness of the calculation of the cyclic redundancy check bits in the data are improved.

In a specific embodiment, the MAC layer packet includes a cyclic redundancy check parameter selected by the MAC layer according to the communication protocol; the cyclic redundancy check parameters comprise polynomial length and parallelism;

Specifically, after detecting the frame header of the MAC layer packet and obtaining the packet length, the physical layer sending end may take out the data in the buffer memory based on the transmission rate according to the cyclic redundancy check parameters obtained before and according to the first-in first-out principle, and perform the calculation of the cyclic redundancy check bits, and at the same time, fill the issued data into the buffer memory, so as to keep the balance of the data in and out of the buffer memory, and perform the gradual calculation of the cyclic redundancy check bits while the MAC layer packet is issued. Where parallelism refers to the length of data processed in a single clock cycle.

Further, the physical layer sending end can judge whether the current MAC layer packet is processed according to the packet length of the MAC layer packet, if so, attach a first Cyclic Redundancy Check bit calculated by CRC (Cyclic Redundancy Check) to the MAC layer packet, otherwise, execute the step-by-step calculation of the Cyclic Redundancy Check bit. The length of the data packet can be determined according to the frame body length and the overhead of the MAC layer data packet, and the latter can be determined according to the communication protocol of the system.

For example: the length of the data packet indicating frame body is 4000 bytes, according to the communication protocol, the overhead of the MAC layer data packet is fixed to 11 bytes, and then the physical layer sending end can determine that the length of the data packet is 4011 byte, so as to judge whether the current MAC layer data packet is processed completely. And if the processing is judged to be finished, attaching the cyclic redundancy check bit to the back of the data of the MAC layer data packet for sending.

Step S106, the physical layer receiving end analyzes the MAC layer data packet added with the first cyclic redundancy check bit to obtain second analysis information; and based on the second analysis information, CRC calculation of the MAC layer data packet added with the first cyclic redundancy check bit is completed, and a second cyclic redundancy check bit is obtained.

Specifically, the physical layer receiving end can calculate the cyclic redundancy check bits of the data packet according to the communication protocol. Further, after obtaining the length of the MAC layer packet appended with the first CRC, the physical layer receiving end performs a corresponding CRC operation on the MAC layer packet.

Specifically, the physical layer receiving end caches the data packet received from the physical layer sending end, and detects the frame header of the MAC layer data packet and the corresponding data packet length;

the frame header of the MAC layer data packet and the information position indicating the length of the data packet are determined according to the communication protocol. For example: the header of the frame is defined as 0x4859 in the communication protocol, and the physical layer considers that the starting position of a MAC layer packet is here when detecting that certain 16 consecutive bits are equal to 0x 4859. The simultaneous communication protocol provides that the 5th and 6 th bytes from the frame header indicate the frame body length, so that the physical layer can read the frame body length of the current MAC layer packet at the corresponding position.

On the other hand, in a specific embodiment, the MAC layer packet contains a cyclic redundancy check parameter selected by the media access control layer according to the communication protocol; the cyclic redundancy check parameters comprise polynomial length and parallelism;

the physical layer receiving end confirms whether CRC calculation processing of the MAC layer data packet added with the first cyclic redundancy check bit is finished or not according to the length of the data packet; the data packet length is obtained according to the overhead of the MAC layer data packet, the length of the first cyclic redundancy check bit and the length of the frame body; the MAC layer packet overhead is determined based on the communication protocol.

Specifically, after detecting the frame header of the MAC layer packet and obtaining the packet length, the physical layer receiving end takes out the data in the buffer memory based on the transmission rate according to the cyclic redundancy check parameters obtained before and according to the first-in first-out principle, calculates the cyclic redundancy check bits, and fills the issued data into the buffer memory to keep the balance of the data in and out of the buffer memory, thereby realizing the gradual calculation of the cyclic redundancy check bits while issuing the MAC layer packet. According to the method and the device, the cyclic redundancy check parameters are reasonably selected, and the real-time performance and effectiveness of the calculation of the cyclic redundancy check bits in the data are improved.

The physical layer receiving end can judge whether the current MAC layer data packet is processed or not according to the length of the MAC layer data packet, if so, the step S108 is executed, otherwise, the step-by-step calculation of the second cyclic redundancy check bit is executed;

the data packet length of the MAC layer packet to which the first cyclic redundancy check bit is added may be determined according to the first cyclic redundancy check bit, the frame body length and the overhead of the MAC layer packet, which is determined according to the system communication protocol. For example: the length of the data packet indication frame body is 4000 bytes, and according to the communication protocol, the overhead of the MAC layer data packet is fixed to be 11 bytes, so that the physical layer can determine that the length of the data packet is 4011 byte. Assuming that the length of the added cyclic redundancy check bit is 4 bytes, the length of the data packet to be processed should be 4007 bytes, so as to determine whether the current MAC layer data packet is processed completely.

And step S108, the physical layer receiving end compares the first cyclic redundancy check bit with the second cyclic redundancy check bit and completes data reporting according to the comparison result.

Specifically, the physical layer receiving end compares whether the calculated cyclic redundancy check bit is consistent with the received cyclic redundancy check bit, and the comparison result and the data are reported.

It should be noted that the main idea of the cyclic redundancy check is to determine the success probability of the required cyclic redundancy check, and then determine the number of cyclic redundancy check bits to be added and the corresponding generator polynomial. The sending end calculates the cyclic redundancy check bit with fixed length according to the generator polynomial and the input data, and attaches the cyclic redundancy check bit to the back of the data for transmission. After receiving the data, the receiving end performs the same calculation according to the generator polynomial and the received data, if the calculated cyclic redundancy check bit is consistent with the received cyclic redundancy check bit, the transmitted data is considered to have no error under the previously determined probability, and the data can be further processed; otherwise, the data transmission is considered to be in error and needs to be discarded.

The cyclic redundancy check originally implemented at the MAC layer is sunk to the physical layer for implementation, so that the logical circuit resources of the physical layer are fully utilized, the calculation complexity of the MAC layer is reduced, and the real-time calculation of the cyclic redundancy check bits of the data can be realized. Furthermore, the cyclic redundancy check parameters are reasonably selected, and the real-time performance and effectiveness of the calculation of the cyclic redundancy check bits in the data are improved.

In addition, different from the traditional technology, the method is focused on describing how to flexibly realize the calculation of the cyclic redundancy check bits with different bit widths in the FPGA or what calculation architecture is adopted in the cyclic redundancy check calculation to accelerate; the present application is directed to how to enable a physical layer (e.g., FPGA) to cooperate with a MAC, so that the physical layer understands a communication protocol of the MAC, and thereby, a cyclic redundancy check function of the MAC layer (i.e., a media access control layer) is put into the physical layer to speed up the cyclic redundancy check of the MAC layer. Regarding a specific application scenario, the communication protocol mentioned in the present application may refer to a millimeter wave communication protocol of 5G.

In one embodiment, as shown in fig. 2, a cyclic redundancy check acceleration method is provided, which is described by taking the method as an example applied to a MAC layer (i.e., a medium access control layer), and includes the following steps:

step S202, the media access control layer constructs a MAC layer data packet which accords with the MAC frame structure;

specifically, the MAC layer may construct a packet that conforms to the frame structure of the MAC layer according to the communication protocol.

Further, in a specific embodiment, the step of constructing the MAC layer packet conforming to the MAC frame structure at the MAC control layer may include:

the media access control layer selects a cyclic redundancy check parameter according to a communication protocol, and constructs an MAC layer data packet which accords with an MAC frame structure and vacates a corresponding cyclic redundancy check bit position according to the cyclic redundancy check parameter; the cyclic redundancy check parameters include polynomial length and parallelism.

Specifically, the MAC layer constructs a data packet conforming to the MAC frame structure according to the communication protocol, and simultaneously vacates the position of the corresponding cyclic redundancy check bit.

Further, the MAC layer selects parameters of cyclic redundancy check, such as the length of a polynomial and the calculated parallelism (data length processed in a single clock cycle), according to requirements of a transmission protocol communication protocol, such as time delay, transmission rate, and bit error rate, and constructs a data packet conforming to the MAC frame structure, and simultaneously vacates the position of a corresponding cyclic redundancy check bit.

It should be noted that, the higher the time delay requirement of the communication protocol in the present application is, the higher the transmission rate requirement is, the higher the calculation speed requirement of the cyclic redundancy check is; the stricter the requirement of the bit error rate is, the longer the requirement of the length of the cyclic redundancy check polynomial is.

Step S204, the media access control layer sends the MAC layer data packet to the physical layer sending end; the MAC layer data packet is used for indicating the physical layer sending end to send the MAC layer data packet added with the first cyclic redundancy check bit to the physical layer receiving end; the MAC layer data packet added with the first cyclic redundancy check bit is obtained by adding the first cyclic redundancy check bit to the MAC layer data packet through a physical layer sending end; the first cyclic redundancy check bit is obtained by completing CRC calculation on the basis of first analysis information by an MAC layer data packet through a physical layer sending end; the first analysis information is obtained by analyzing an MAC layer data packet through a physical layer sending end;

Specifically, the MAC layer constructs a data packet conforming to the MAC frame structure according to the communication protocol, and simultaneously vacates the position of a corresponding cyclic redundancy check bit, and issues the data packet to the physical layer through a PCI Express (peripheral component interconnect Express) or parallel interface or other devices; further, the physical layer executes a corresponding cyclic redundancy check process, wherein the specific process of the physical layer executing the CRC calculation may refer to the aforementioned cyclic redundancy check acceleration method executed by the physical layer, and is not described herein again.

In a specific embodiment, the media access control layer is implemented based on an ARM architecture; the media access control layer sends the MAC layer data packet to the physical layer sending end through PCIe or parallel interface.

In the above, most of the MAC layers in the communication system are implemented based on the CPU of the ARM architecture, and the calculation of the cyclic redundancy check bits has a large burden on the MAC layers, which affects the system performance. The method and the device have the advantages that the cyclic redundancy check function is put down to the physical layer, so that the calculation burden of the MAC layer is reduced, and the calculation performance of the MAC layer is improved; meanwhile, the cyclic redundancy check is implemented by using the physical layer, so that the time delay of calculating the cyclic redundancy check bit can be effectively reduced, and the overall time delay performance of the system is improved.

The method mainly aims to solve the problem of how to enable a physical layer (such as an FPGA) to be cooperated with an MAC (media access control), so that the physical layer can understand the communication protocol of the MAC, the cyclic redundancy check function of the MAC layer is transferred to the physical layer, the cyclic redundancy check bits of the data are calculated in real time by utilizing abundant circuit logic resources in the physical layer, and the calculation of the cyclic redundancy check bits in the data is accelerated.

The following describes the present application in detail with reference to a specific example, and as shown in fig. 3, a cyclic redundancy check acceleration method is provided, which is described by taking as an example that the method is applied to a base station, and is specifically applied to a MAC layer (i.e., a MAC layer) and a physical layer in the base station, and includes the following steps:

step 301, the MAC layer in the base station constructs a data packet conforming to the frame structure of the MAC layer according to the communication protocol, and simultaneously vacates the position of the corresponding crc bit, and issues the crc bit to the physical layer through PCIE or parallel interface devices.

Specifically, in order to cooperate with an FPGA (physical layer) and a MAC, the MAC layer selects parameters of cyclic redundancy check, such as the length of a polynomial and the calculated parallelism (data length processed in a single clock cycle), according to requirements of a communication protocol, such as time delay, transmission rate, and bit error rate, and constructs a data packet conforming to the MAC frame structure, and simultaneously vacates the position of a corresponding cyclic redundancy check bit.

Step 302, a physical layer sending end in the base station analyzes a data packet sent by an MAC layer according to a communication protocol.

The variables to be analyzed in step 302 respectively include: the frame head of the MAC layer data packet and the frame body length of the MAC layer data packet;

wherein, the frame header of each MAC layer data packet represents the starting position of each MAC layer data packet and is also the separation point of each MAC layer data packet; the frame body length of the MAC layer data packet represents the data length of each MAC layer data packet except the overhead;

for example: the header of the MAC layer packet may be represented by 16 special bits, and if hexadecimal numbers are used to represent the header, 0x4859 may be used to represent the header;

the frame length of the MAC layer packet can be expressed by 12 bits, so the frame length is 8192 bytes at most, and if the overhead of the MAC layer packet is fixed to 11 bytes (including the frame header and other overhead), the maximum length of the whole MAC layer packet is 8203 bytes;

the method for the physical layer sending end to calculate the cyclic redundancy check bits of the data packet according to the communication protocol in step 302 may be:

1) caching a data packet issued by an MAC layer, and detecting a frame header of the MAC layer data packet and the corresponding data packet length;

in step 1), the frame header of the MAC layer packet and the information position indicating the packet length are both determined according to the communication protocol.

For example: the header of the frame is defined as 0x4859 in the communication protocol, and the physical layer considers that the starting position of a MAC layer packet is here when detecting that certain 16 consecutive bits are equal to 0x 4859. The simultaneous communication protocol provides that the 5th and 6 th bytes from the frame header indicate the frame body length, so that the physical layer can read the frame body length of the current MAC layer packet at the corresponding position.

2) After detecting the frame header of the MAC layer data packet and obtaining the length of the data packet, according to the previously obtained cyclic redundancy check parameters and according to the first-in first-out principle, taking out the data in the cache by taking the transmission rate as the reference, calculating the cyclic redundancy check bits, filling the issued data into the cache, keeping the balance of the data in and out of the cache, and realizing the gradual calculation of the cyclic redundancy check bits while issuing the MAC layer data packet;

3) judging whether the current MAC layer data packet is processed or not according to the length of the MAC layer data packet, if so, executing the step 4), otherwise, executing the step 2);

in step 3), the length of the data packet is determined according to the frame body length and the overhead of the MAC layer data packet, and the latter is determined according to the system communication protocol.

For example: the length of the indicated frame body of the data packet is 4000 bytes, and according to the communication protocol, the overhead of the MAC layer data packet is fixed to be 11 bytes, so that the physical layer can determine that the length of the data packet is 4011 byte, and whether the current MAC layer data packet is processed is judged.

4) And (5) attaching the cyclic redundancy check bit to the data for transmission, and executing the step 5).

And 303, the physical layer receiving end calculates the cyclic redundancy check bits of the data packet according to the communication protocol and compares the cyclic redundancy check bits.

Specifically, the process of calculating and comparing the cyclic redundancy check bits of the data packet according to the communication protocol by the physical layer receiving end may include:

5) caching a data packet received from a physical layer sending end, and detecting a frame header of an MAC layer data packet and the length of the corresponding data packet;

in step 5), the frame header of the MAC layer packet and the information position indicating the packet length are determined according to the communication protocol.

6) After detecting the frame header of the MAC layer data packet and obtaining the length of the data packet, according to the previously obtained cyclic redundancy check parameters and according to the first-in first-out principle, taking out the data in the cache by taking the transmission rate as the reference, calculating the cyclic redundancy check bits, filling the issued data into the cache, keeping the balance of the data in and out of the cache, and realizing the gradual calculation of the cyclic redundancy check bits while issuing the MAC layer data packet;

7) judging whether the current MAC layer data packet is processed or not according to the length of the MAC layer data packet, if so, executing a step 8), otherwise, executing a step 6);

in step 7), the length of the data packet may be determined according to the length of the added cyclic redundancy check bit, the length of the frame body, and the overhead of the MAC layer data packet, and the latter is determined according to the system communication protocol. For example: the length of the data packet indication frame body is 4000 bytes, and according to the communication protocol, the overhead of the MAC layer data packet is fixed to be 11 bytes, so that the physical layer can determine that the length of the data packet is 4011 byte. Assuming that the length of the added cyclic redundancy check bit is 4 bytes, the length of the data packet to be processed should be 4007 bytes, so as to determine whether the current MAC layer data packet is processed completely.

8) And comparing whether the calculated cyclic redundancy check bit is consistent with the received cyclic redundancy check bit or not, and finishing the report of the comparison result and the data.

The MAC layer constructs a data packet which accords with an MAC frame structure according to a communication protocol and issues the data packet to a physical layer; then, the physical layer analyzes the content of the MAC layer data packet and calculates the cyclic redundancy check bits of the data in real time. The method and the device sink the function of calculating the cyclic redundancy check of the MAC layer to the physical layer for calculation, reduce the calculation burden of the MAC by utilizing the abundant logical resources of the physical layer, reduce the calculation complexity of the MAC layer and realize the real-time calculation of the cyclic redundancy check bit of the data; according to the method and the device, the cyclic redundancy check parameters are reasonably selected, and the real-time performance and effectiveness of the calculation of the cyclic redundancy check bits in the data are improved.

It should be understood that although the various steps in the flow charts of fig. 1-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-3 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

In one embodiment, as shown in fig. 4, there is provided a cyclic redundancy check acceleration apparatus implemented from a physical layer perspective, including:

a sending end cyclic redundancy check module 410, configured to analyze an MAC layer packet from a media access control layer to obtain first analysis information; the MAC layer data packet is a data packet which is constructed by a media access control layer and conforms to an MAC frame structure; and completing CRC calculation of the MAC layer data packet based on the first analysis information, attaching a first cyclic redundancy check bit obtained through the CRC calculation to the MAC layer data packet, and sending the MAC layer data packet attached with the first cyclic redundancy check bit to a physical layer receiving end;

the receiving end cyclic redundancy check module 420 is configured to analyze the MAC layer packet with the first cyclic redundancy check bit received by the physical layer receiving end to obtain second analysis information; and based on the second analysis information, completing CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit to obtain a second cyclic redundancy check bit; and comparing the first cyclic redundancy check bit with the second cyclic redundancy check bit, and finishing data reporting according to the comparison result.

For specific definition of the crc accelerated device from the perspective of the physical layer, reference may be made to the above definition of the crc accelerated method from the perspective of the physical layer, and details are not repeated here. The various modules in the above described cyclic redundancy check acceleration apparatus implemented from the physical layer perspective may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, as shown in fig. 5, there is provided a cyclic redundancy check acceleration apparatus implemented from a media access control layer perspective, including:

a MAC layer construction packet module 510 configured to construct a MAC layer packet that conforms to a MAC frame structure;

the MAC layer data transmitting module 520 is configured to transmit the MAC layer data packet to the physical layer transmitting end;

For specific limitations of the crc accelerated device from the perspective of the MAC layer, reference may be made to the above limitations of the crc accelerated method from the perspective of the MAC layer, and details are not repeated here. The various modules in the above described cyclic redundancy check acceleration apparatus implemented from the perspective of the MAC layer may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In an embodiment, as shown in fig. 6, a cyclic redundancy check acceleration apparatus implemented from the perspective of a base station is provided, which includes an MAC layer construction packet module 601, a transmitting side cyclic redundancy check module 602, and a receiving side cyclic redundancy check module 603;

the MAC layer construction data packet module 601 is configured to construct, by the MAC layer according to a communication protocol, a data packet that conforms to a frame structure of the MAC layer and send the data packet to the physical layer;

a sending end cyclic redundancy check module 602, configured to calculate and add a cyclic redundancy check bit of an MAC layer packet at a physical layer sending end, and send the cyclic redundancy check bit;

and the receiving end cyclic redundancy check module 603 is configured to calculate and compare cyclic redundancy check bits of the MAC layer data packet by the receiving end of the physical layer, and complete reporting of the comparison result and the data.

For specific limitations of the crc accelerated device from the perspective of the base station, reference may be made to the above limitations of the crc accelerated method from the perspective of the base station, and details are not repeated here. The various modules in the above described cyclic redundancy check acceleration apparatus implemented from the base station perspective may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, an access network device is provided, the access network device comprising a CPU and an FPGA connected to the CPU;

In a specific embodiment, the access network device is a base station; the base stations comprise macro base stations, micro base stations, pico base stations and pico base stations.

In a specific embodiment, the CPU is connected to the FPGA through PCIe or parallel port.

Specifically, as shown in fig. 7, the MAC layer packet processing can be accelerated, the traditional system has high real-time requirement on a large data volume, the CPU logic processing load is high, the efficiency is low, and the time is long; the application proposes to sink part of the functions; specifically, the MAC layer issues the MAC packet to the FPGA chip, and the FPGA chip first identifies the delimiter in the MAC packet and then analyzes the length of the MAC packet according to the structure of the MAC packet. After the length of the MAC packet is obtained, corresponding CRC operation is carried out on the MAC packet.

It should be noted that the MAC layer is located in the upper layer CPU, and the FPGA belongs to the lower layer service of the CPU; the method and the device have the advantages that the MAC layer is put into the FPGA under the operation, the cooperation of the FPGA and the MAC layer is realized, and the cyclic redundancy check of the MAC layer is accelerated on the basis that the FPGA understands the communication protocol of the MAC layer. The calculation pressure of the MAC layer can be obviously reduced, and the real-time calculation capability of the cyclic redundancy check bit is obviously improved.

Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, realizes the steps of the method of any of the above.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A cyclic redundancy check acceleration method, comprising the steps of:

the physical layer sending end analyzes the MAC layer data packet from the media access control layer to obtain first analysis information; the MAC layer data packet comprises a cyclic redundancy check parameter selected by the media access control layer according to a communication protocol; the MAC layer data packet is a data packet which is constructed by the media access control layer according to the cyclic redundancy check parameter and accords with an MAC frame structure;

the physical layer sending end completes CRC calculation of the MAC layer data packet based on the first analysis information and the cyclic redundancy check parameters, attaches a first cyclic redundancy check bit obtained through CRC calculation to the MAC layer data packet, and sends the MAC layer data packet with the first cyclic redundancy check bit attached to the MAC layer data packet to a physical layer receiving end; wherein, the step of attaching the first cyclic redundancy check bit obtained by CRC calculation to the MAC layer data packet comprises: attaching the first cyclic redundancy check bit to the rear of the MAC layer packet in the case of confirming that the MAC layer packet is processed by CRC calculation; wherein the step of the physical layer transmitting end completing the CRC calculation of the MAC layer packet based on the first parsing information and the cyclic redundancy check parameter includes: the physical layer sending end takes out the MAC layer data packet in the cache based on the transmission rate according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the first cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache;

the physical layer receiving end analyzes the MAC layer data packet added with the first cyclic redundancy check bit to obtain second analysis information; completing CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit on the basis of the second analysis information and the cyclic redundancy check parameter to obtain a second cyclic redundancy check bit; wherein, the physical layer receiving end completes the CRC calculation of the MAC layer packet to which the first cyclic redundancy check bit is added based on the second parsing information and the cyclic redundancy check parameter, and the step of obtaining the second cyclic redundancy check bit includes: the physical layer receiving end takes out the MAC layer data packet which is added with the first cyclic redundancy check bit in the cache by taking the transmission rate as the reference according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the second cyclic redundancy check bit and fills the MAC layer data packet to be issued after calculation into the cache;

and the physical layer receiving end compares the first cyclic redundancy check bit with the second cyclic redundancy check bit and finishes data reporting according to the comparison result.

2. The crc accelerated method of claim 1, wherein the first parsing information comprises a frame header and a frame body length;

the physical layer sending end caches the MAC layer data packet, and detects the MAC layer data packet in the cache according to the communication protocol to obtain the frame header;

and the physical layer sending end reads the MAC layer data packet in the cache according to the communication protocol and the frame header to obtain the frame body length.

3. The cyclic redundancy check acceleration method of claim 2, wherein the cyclic redundancy check parameters include a polynomial length and a degree of parallelism;

wherein, the step of taking out the MAC layer packet in the buffer based on the transmission rate and calculating the first cyclic redundancy check bit comprises:

the physical layer sending end confirms whether CRC calculation processing of the MAC layer data packet is finished or not according to the length of the data packet; the data packet length is obtained according to the overhead of the MAC layer data packet and the frame body length; the MAC layer packet overhead is determined based on the communication protocol.

4. The crc accelerated method of claim 1, wherein the second parsing information comprises a frame header and a frame body length;

the physical layer receiving end analyzes the MAC layer packet to which the first crc bit is added, and obtains second analysis information, including:

the physical layer receiving end caches the MAC layer data packet with the first cyclic redundancy check bit, and detects the MAC layer data packet with the first cyclic redundancy check bit in the cache according to the communication protocol to obtain the frame header;

and the physical layer receiving end reads the MAC layer data packet with the attached first cyclic redundancy check bit in the cache according to the communication protocol and the frame header to obtain the length of the frame body.

5. The CRC acceleration method of claim 4, wherein the CRC parameters include a polynomial length and a degree of parallelism;

wherein, the step of taking out the MAC layer packet with the first cyclic redundancy check bit in the buffer based on the transmission rate and calculating the second cyclic redundancy check bit comprises:

6. A cyclic redundancy check acceleration method, comprising the steps of:

the media access control layer selects a cyclic redundancy check parameter according to a communication protocol and constructs an MAC layer data packet which accords with an MAC frame structure according to the cyclic redundancy check parameter;

the media access control layer transmits the MAC layer data packet containing the cyclic redundancy check parameter to a physical layer transmitting end;

the MAC layer data packet is used for indicating the physical layer sending end to send the MAC layer data packet with the first cyclic redundancy check bit to the physical layer receiving end; the MAC layer data packet added with the first cyclic redundancy check bit is obtained by adding the first cyclic redundancy check bit to the MAC layer data packet through the physical layer sending end, wherein the physical layer sending end attaches the first cyclic redundancy check bit to the back of the MAC layer data packet under the condition that the MAC layer data packet is confirmed to be processed through CRC calculation; the first cyclic redundancy check bit is obtained by completing CRC calculation of the MAC layer data packet through the physical layer sending end based on first analysis information and the cyclic redundancy check parameter; the first analysis information is obtained by analyzing the MAC layer data packet through the physical layer sending end; wherein the step of completing the CRC calculation for the MAC layer packet based on the first parsing information and the cyclic redundancy check parameter comprises: the physical layer sending end takes out the MAC layer data packet in the cache based on the transmission rate according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the first cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache;

the MAC layer data packet with the first cyclic redundancy check bit is used for indicating the physical layer receiving end to compare a second cyclic redundancy check bit with the first cyclic redundancy check bit and completing data reporting according to the comparison result; the second cyclic redundancy check bit is obtained by completing CRC calculation of the MAC layer data packet added with the first cyclic redundancy check bit through the physical layer receiving end based on second analysis information and the cyclic redundancy check parameter; the second analysis information is obtained by analyzing the MAC layer data packet added with the first cyclic redundancy check bit through the physical layer receiving end; wherein, the step of completing the CRC calculation of the MAC layer packet to which the first cyclic redundancy check bit is added based on the second parsing information and the cyclic redundancy check parameter to obtain a second cyclic redundancy check bit includes: and the physical layer receiving end takes out the MAC layer data packet which is added with the first cyclic redundancy check bit in the cache by taking the transmission rate as the reference according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the second cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache.

7. The CRC acceleration method according to claim 6, wherein the MAC layer is implemented based on ARM architecture;

and the media access control layer issues the MAC layer data packet to the physical layer sending end through PCIe or parallel interface.

8. The cyclic redundancy check acceleration method according to claim 6 or 7, wherein the step of the media access control layer selecting a cyclic redundancy check parameter according to a communication protocol and constructing a MAC layer packet conforming to the MAC frame structure according to the cyclic redundancy check parameter comprises:

the media access control layer constructs the MAC layer data packet which accords with the MAC frame structure and vacates the corresponding cyclic redundancy check bit position according to the cyclic redundancy check parameters;

wherein the cyclic redundancy check parameters include a polynomial length and a parallelism.

9. A cyclic redundancy check acceleration apparatus, the apparatus comprising:

the system comprises a sending end cyclic redundancy check module, a receiving end cyclic redundancy check module and a transmitting end cyclic redundancy check module, wherein the sending end cyclic redundancy check module is used for analyzing an MAC layer data packet from a media access control layer to obtain first analysis information; the MAC layer data packet comprises a cyclic redundancy check parameter selected by the media access control layer according to a communication protocol, and the MAC layer data packet is a data packet which is constructed by the media access control layer according to the cyclic redundancy check parameter and accords with an MAC frame structure; and completing CRC calculation of the MAC layer data packet based on the first analysis information and the cyclic redundancy check parameters, attaching a first cyclic redundancy check bit obtained through the CRC calculation to the MAC layer data packet, and sending the MAC layer data packet attached with the first cyclic redundancy check bit to a physical layer receiving end; wherein the first cyclic redundancy check bit is attached to the rear of the MAC layer packet in case of confirming that the MAC layer packet is processed by CRC calculation; the sending end cyclic redundancy check module is used for taking out the MAC layer data packet in the cache based on the transmission rate according to the cyclic redundancy check parameter and a first-in first-out rule, calculating the first cyclic redundancy check bit and filling the MAC layer data packet to be sent after calculation into the cache;

the receiving end cyclic redundancy check module is used for analyzing the MAC layer data packet which is received by the physical layer receiving end and is added with the first cyclic redundancy check bit to obtain second analysis information; and based on the second analytic information and the cyclic redundancy check parameter, completing CRC calculation of the MAC layer data packet attached with the first cyclic redundancy check bit to obtain a second cyclic redundancy check bit; comparing the first cyclic redundancy check bit with the second cyclic redundancy check bit, and finishing data reporting according to the comparison result; the receiving end cyclic redundancy check module is configured to take out the MAC layer packet with the first cyclic redundancy check bit appended thereto in the cache based on the transmission rate according to the cyclic redundancy check parameter and a first-in first-out rule, perform calculation of the second cyclic redundancy check bit, and fill the MAC layer packet to be delivered after calculation into the cache.

10. A cyclic redundancy check acceleration apparatus, the apparatus comprising:

the MAC layer construction data packet module is used for selecting a cyclic redundancy check parameter according to a communication protocol and constructing an MAC layer data packet which accords with an MAC frame structure according to the cyclic redundancy check parameter;

the MAC layer data sending module is used for sending the MAC layer data packet containing the cyclic redundancy check parameter to a physical layer sending end;

the MAC layer data packet is used for indicating the physical layer sending end to send the MAC layer data packet with the first cyclic redundancy check bit to the physical layer receiving end; the MAC layer data packet added with the first cyclic redundancy check bit is obtained by adding the first cyclic redundancy check bit to the MAC layer data packet through the physical layer sending end, wherein the physical layer sending end attaches the first cyclic redundancy check bit to the back of the MAC layer data packet under the condition that the MAC layer data packet is confirmed to be processed through CRC calculation; the first cyclic redundancy check bit is obtained by completing CRC calculation on the basis of first analysis information and the cyclic redundancy check parameter by the MAC layer data packet through the physical layer sending end; the first analysis information is obtained by analyzing the MAC layer data packet through the physical layer sending end; wherein the step of completing the CRC calculation for the MAC layer packet based on the first parsing information and the cyclic redundancy check parameter comprises: the physical layer sending end takes out the MAC layer data packet in the cache based on the transmission rate according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the first cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache;

the MAC layer data packet with the first cyclic redundancy check bit is used for indicating the physical layer receiving end to compare a second cyclic redundancy check bit with the first cyclic redundancy check bit and finishing data reporting according to the comparison result; the second cyclic redundancy check bit is obtained by completing CRC calculation of the MAC layer data packet added with the first cyclic redundancy check bit through the physical layer receiving end based on second analysis information and the cyclic redundancy check parameter; the second analysis information is obtained by analyzing the MAC layer data packet added with the first cyclic redundancy check bit through the physical layer receiving end; wherein, the step of completing the CRC calculation of the MAC layer packet to which the first cyclic redundancy check bit is added based on the second parsing information and the cyclic redundancy check parameter to obtain a second cyclic redundancy check bit includes: and the physical layer receiving end takes out the MAC layer data packet which is added with the first cyclic redundancy check bit in the cache by taking the transmission rate as the reference according to the cyclic redundancy check parameter and a first-in first-out rule, calculates the second cyclic redundancy check bit, and fills the MAC layer data packet to be issued after calculation into the cache.

11. The access network equipment is characterized by comprising a CPU and an FPGA connected with the CPU;

the CPU is configured to perform the steps of the method of any one of claims 6 to 8;

the FPGA is configured to perform the steps of the method of any one of claims 1 to 5.

12. The access network device of claim 11, wherein the access network device is a base station; the base stations comprise macro base stations, micro base stations, pico base stations and pico base stations.

13. The access network device of claim 11, wherein the CPU connects to the FPGA through PCIe or parallel.

14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 8.