CN110362530B

CN110362530B - Data chain blind signal processing method based on parallel pipeline architecture

Info

Publication number: CN110362530B
Application number: CN201910646037.4A
Authority: CN
Inventors: 范曦丹; 张花国; 薛文丽; 高岚
Original assignee: University of Electronic Science and Technology of China
Current assignee: NORTH AUTOMATIC CONTROL TECHNOLOGY INSTITUTE
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2023-02-03
Anticipated expiration: 2039-07-17
Also published as: CN110362530A

Abstract

The invention belongs to the technical field of blind signal processing, and relates to a data chain blind signal processing method based on a parallel pipeline architecture. The invention mainly utilizes a DSP C6678 chip to complete the parallel processing of data chain pulse signals. Through the processing operation of the pipeline, the parallel processing calculation of three cores is realized, and the processing capacity of data chain signals is improved. Through actual debugging, each core in the chip can ensure that blind processing of the data link signal is completed within 50 microseconds to obtain a parameter estimation result, so that the integrity and the real-time performance of continuous data link pulse signal processing are ensured.

Description

Data chain blind signal processing method based on parallel pipeline architecture

Technical Field

The invention belongs to the technical field of blind signal processing, and relates to a data chain blind signal processing method based on a parallel pipeline architecture.

Background

In many practical signal processing situations, the various information required for signal processing is not fully known, and in this case, the signal processing is called blind signal processing, and the original signal is estimated on the premise that the signal cannot utilize a reference signal or a theoretical model. "blind" means that the channel information of the original signal and the transmission signal is not known in advance to the receiving side, and the information of the input signal is estimated by performing a blind processing technique on the mixed signal received by a receiver or the like. In the field of non-cooperative signal processing, after receiving an unknown frequency hopping signal sent by a sender through a receiving device, blind detection needs to be performed on the frequency hopping signal mixed in noise, parameter estimation needs to be performed on the detected unknown signal, a modulation mode of the signal is identified, and important parameter information such as baud rate of data needs to be identified, so that interception of the sender signal is achieved.

Disclosure of Invention

The invention mainly provides a parallel framework for realizing high-speed signal blind processing through hardware, which divides each data link signal to be processed into a plurality of subtasks and distributes the subtasks to a plurality of kernels by utilizing a DSP digital signal processing chip and adopting a multi-core development design; the method has the advantages that each subtask is executed in a parallel and cooperative mode through a plurality of kernels, the processing capacity of the tasks is improved, the pulse period of a data link signal to be processed is microsecond order when the signal to be processed is a high-speed frequency hopping jump data link signal, and the characteristic of frequency agility among pulses is required

The invention is used for realizing blind processing of high-speed data chain signals, the data chain signals adopt a GMSK modulation mode, a DSP adopts a C6678 chip, the design of a parallel computing structure is realized by using three cores, the computing mode adopts a pipeline mode for processing, namely, each core only completes part of processing on currently received pulse data, the currently received pulse data is processed by the next core continuously after the processing is completed, and the current core starts to process the next pulse data. The whole calculation process mainly comprises the following steps: the method comprises the steps of direction finding by adopting a Music algorithm, self-adaptive beam forming, bandwidth rough estimation, fine estimation of pulse starting time and pulse ending time, identification of a signal modulation mode and parameter estimation. The parameter estimation comprises estimation of the frequency, bandwidth, baud rate, power of the signal. The task between cores is divided into: the core0 completes the direction finding and self-adaptive beam forming part of a Music algorithm, the core1 completes the bandwidth rough estimation and the fine estimation part of the pulse starting time and the pulse ending time, and the core2 completes the identification of a signal modulation mode and the parameter estimation part.

The method comprises the following specific steps:

s1, using Core0 as a main Core to complete system initialization, distributing a shared stack for sending messages, wherein the messages comprise necessary MessageQ Header, using Core0 to complete a Music algorithm and an adaptive beam forming algorithm of Data1 Data, storing the formed pulse signals in a multi-Core shared memory, storing the Data in a Ping array, inquiring whether Flag bit Flag0 in the Core1 is 1, if so, the Core1 is in a cycle waiting state, if so, sending messages to inform Core1 to complete subsequent calculation, using Core0 to wait for receiving and processing next batch of Data2 Data, and storing the processed results in a Pong array;

and S2, the Core1 serves as a slave Core, receives the message sent by the Core0, starts the subsequent calculation of the Data1 Data, and reads the Data required by the calculation from the Ping array. The Core1 mainly completes the rough estimation of bandwidth and the fine estimation of pulse starting time and pulse ending time of the formed Data and the interception of pulse signals, a Flag0 is set to be 0 before processing, the processed Data is stored in a Ping array, whether the Flag1 in the Core2 Core is 1 or not is inquired at the moment, if the value is 0, the device is in a circulation waiting state, if the value is 1, a message is sent to inform the Core2 to finish the subsequent calculation, and a Flag0 is set to be 1, at the moment, the Core1 starts to wait for receiving the message sent by the Core0 and starts to process the next batch of Data2 Data, and the processed result is stored in a Pong array;

and S3, the Core2 serves as a slave Core, receives the message sent by the Core1, starts the subsequent calculation of the Data1, and reads the Data required by the calculation from the Ping array. The Core2 mainly completes the identification of the modulation mode of the intercepted Data and a parameter estimation part, the parameter estimation comprises the estimation of the frequency, the bandwidth, the baud rate and the power of signals, a Flag1 is set to be 0 before the processing, the final result after the processing is completed is stored in a Ping array, the Flag1 is set to be 1, and the Ping array comprises all parameter measurement of the Data1 Data. After the Data1 is processed, the Data2 Data sent by the Core1 can be processed, the result is stored in the Pong array, and the like is carried out on the following Data processing method, so that the parallel processing structure of the Data pipeline is realized.

By adopting the structure of multi-core pipeline parallel processing calculation, as shown in table 1, the processing time of each core is within 50 microseconds, and the processing time distribution among the cores is uniform, so that one core is not in a long-time waiting state. Where the Count value represents the number of pulses processed. Therefore, the pipeline processing structure of the invention is suitable for processing high-speed data chain signals.

Drawings

FIG. 1 is a flow chart of the blind processing of data chain signals in the present invention;

FIG. 2 is a flow chart of the present invention for pipelining data link signals;

FIG. 3 is a timing diagram of the DSP core processing of the present invention;

FIG. 4 is a diagram of the DSP inter-core processing architecture of the present invention;

Detailed Description

The invention is described in detail below with reference to the figures and examples

The data chain signal is modulated by GMSK, the pulse period is 50 microseconds, and the calculation of parameter estimation is required to be guaranteed to be completed for each pulse. The DSP adopts a C6678 chip to complete hardware realization. The overall flow chart of the data blind processing adopts a mode of fig. 1, and a pipeline parallel mode is adopted for processing on the DSP hardware realization, as shown in fig. 2. And the distribution adopts Ping, pong and Ball arrays to store the current data, the result after the processing of each core is finished is stored in the corresponding array, and the flow is continued to the next core.

The whole timing diagram adopts the mode of fig. 3, namely after the current core process is finished, the current core needs to wait for the next core process to be finished before data transmission is carried out, otherwise, the current core needs to be in a waiting state.

The structure diagram of the invention adopts the mode of FIG. 4 to ensure that the resources among the cores are not preempted and the deadlock phenomenon. When the processing of each core is completed, the corresponding zone bit needs to be inquired, and whether the next core is in an idle state or not is judged through the zone bit. If the current core is in the idle state, the next core can be informed to process the current data by sending a message, and if the current core is in the busy state, the current core needs to perform loop waiting. Each core processes the pulse signal for a time (in microseconds) as shown in table 1:

TABLE 1

Claims

1. A data link blind signal processing method based on a parallel pipeline architecture is characterized in that based on a DSP C6678 multi-core chip, a GMSK modulation mode is adopted for a data link pulse signal, and the pulse period is 50 microseconds; the DSP C6678 chip dominant frequency is set to be 1.25GHz, and three cores of Core0, core1 and Core2 are adopted to complete parallel calculation; the processing method is characterized by comprising the following steps:

s1, using Core0 as a main Core, completing system initialization, distributing a shared stack for sending messages, wherein the messages comprise necessary MessageQ Header, using Core0 to complete a Music algorithm and an adaptive beam forming algorithm of a first batch of input Data1 Data, storing the formed pulse signals in a multi-Core shared memory, storing the Data in a Ping array, inquiring whether Flag bit Flag0 in the Core1 is 1 or not, if the Flag bit Flag0 is 0, then the Core1 is in a cycle waiting state, if the Flag bit Flag is 1, sending messages to inform the Core1 to complete subsequent calculation, using Core0 to wait for receiving and processing the next batch of input Data2 Data, and storing the processed results in the Pong array;

s2, the Core1 serves as a slave Core, receives a message sent by the Core0, starts the subsequent calculation of the Data1 Data, and reads the Data required by the calculation from the Ping array; the Core1 mainly completes the rough estimation of bandwidth and the fine estimation of pulse starting time and pulse ending time of the formed Data and the interception of pulse signals, a Flag0 is set to be 0 before processing, the processed Data is stored in a Ping array, whether the Flag1 in the Core2 Core is 1 or not is inquired at the moment, if the value is 0, the device is in a circulation waiting state, if the value is 1, a message is sent to inform the Core2 to finish the subsequent calculation, and a Flag0 is set to be 1, at the moment, the Core1 starts to wait for receiving the message sent by the Core0 and starts to process the next batch of Data2 Data, and the processed result is stored in a Pong array;

s3, the Core2 serves as a slave Core, receives the message sent by the Core1, starts the subsequent calculation of the Data1 Data, and reads the Data required by the calculation from the Ping array; the Core2 mainly completes the identification of the modulation mode of the intercepted Data and a parameter estimation part, the parameter estimation comprises the estimation of the frequency, the bandwidth, the baud rate and the power of a signal, a Flag1 is set to be 0 before the processing, the final result after the processing is finished is stored in a Ping array, the Flag1 is set to be 1, and the Ping array comprises all parameter measurement of the Data1 Data; after Data1 Data is processed, data2 Data sent by Core1 can be processed, the result is stored in the Pong array, and the like for the following Data processing method, so that the parallel processing of the Data pipelines is realized.