CN110346992A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN110346992A CN110346992A CN201910509298.1A CN201910509298A CN110346992A CN 110346992 A CN110346992 A CN 110346992A CN 201910509298 A CN201910509298 A CN 201910509298A CN 110346992 A CN110346992 A CN 110346992A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
This application provides a kind of array substrate and display panel, array substrate includes pixel cell, and pixel cell includes multiple picture element subelements；Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, and thin film transistor (TFT) group includes first film transistor, the second thin film transistor (TFT) and the third thin film transistor (TFT) connecting with the second thin film transistor (TFT)；Multiple data lines and multi-strip scanning line；Wherein, each thin film transistor (TFT) in thin film transistor (TFT) group all has channel, the width value in channel is W, length value L, connect the picture element subelement of same data line, according to the sequence at the driving end for being gradually distance from data line, the ratio of the width value W and length value L of first film transistor and the second thin film transistor (TFT) are gradually increased.The application improves display effect by adjusting the channel sized of the thin film transistor (TFT) group of different location in array substrate to realize the homogeneity of the color of different location in the case of big visual angle.
Description
Technical field
This application involves field of display technology, in particular to a kind of array substrate and display panel.
Background technique
Here statement only provides background information related with the application, without inevitably constituting example technique.
Liquid crystal display is mainly by membrane array substrate, color membrane array substrate and the liquid crystal structure between two substrates
At.Currently in order to improving the big viewing angle problem of liquid crystal display, picture element can use the design of 8 farmland 3T transistors (8domain).
The pixel design of 8Domain, each of which pixel electrode can be divided into main picture element region and sub-picture element area.Due to main picture element region and sub-picture element
The characteristic that different brightness can be generated under the area ratio difference in area and identical charging voltage, can achieve and mitigate big visual angle color
Inclined problem.
In large size panel, since data line can be long, load weight on signal wire leads to grid signal and data
Signal can postpone, and the big view effect of different location can be inconsistent, this is allowed at big visual angle, panel difference position
The difference that can generate color is set, display effect is influenced.
Summary of the invention
The main purpose of the application is to provide a kind of array substrate and display panel, it is intended to solve large size panel difference
The technical issues of big visual angle display effect of position is inconsistent, causes different location to generate color difference, influences display effect.
To achieve the goals above, the application provides a kind of array substrate, and the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture
Plain area and the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the film crystal
Pipe group include the first film transistor of driving first picture element region switch, driving the second picture element region switch it is second thin
Film transistor and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions
Domain, each picture element region are provided with the picture element subelement, and every data line connects same row picture element subelement, and every is swept
Line connection is retouched with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, long
Angle value is L, connects the picture element subelement of same data line, and according to the sequence at the driving end for being gradually distance from data line, first is thin
The ratio of the width value W and length value L of film transistor and the second thin film transistor (TFT) are gradually increased or the width of third thin film transistor (TFT)
Angle value W and the ratio of length value L are gradually reduced.
In one embodiment, the width value W and length value L of the corresponding first film transistor of the same picture element subelement
Ratio it is identical as the ratio of the width value W of the second thin film transistor (TFT) and length value L.
In one embodiment, the width value W and length value L of the first film transistor and second thin film transistor (TFT)
Ratio linearly increase.
In one embodiment, the first film transistor and second in each picture element subelement of same data line is connected
Thin film transistor (TFT) is gradually increased according to the sequence for driving end for being gradually distance from data line, width value W, and length value L remains unchanged.
In one embodiment, the first film transistor and second in each picture element subelement of same data line is connected
Thin film transistor (TFT) is gradually reduced according to the sequence for driving end for being gradually distance from data line, length value L, and width value W is remained unchanged.
In one embodiment, the ratio of the width value W and length value L of the first film transistor and the second thin film transistor (TFT)
Value is greater than the width value W of the third thin film transistor (TFT) and the ratio of length value L.
In one embodiment, the width value W of the third thin film transistor (TFT) and the ratio of length value L linearly reduce.
In one embodiment, in the picture element subelement for connecting same data line, the area of each first picture element region
Unanimously, the area of each second picture element region is also consistent.
To achieve the goals above, the application also provides a kind of array substrate, and the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture
Plain area and the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the film crystal
Pipe group include the first film transistor of driving first picture element region switch, driving the second picture element region switch it is second thin
Film transistor and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions
Domain, each picture element region are provided with the picture element subelement, and every data line connects same row picture element subelement, and every is swept
Line connection is retouched with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, long
Angle value is L, connects the picture element subelement of same data line, and according to the sequence at the driving end for being gradually distance from data line, first is thin
The ratio of the width value W and length value L of film transistor and the second thin film transistor (TFT) are gradually increased, the width of third thin film transistor (TFT)
Value W and the ratio of length value L are gradually reduced, the width value W and length of the first film transistor and the second thin film transistor (TFT)
The ratio of value L is greater than the width value W of the third thin film transistor (TFT) and the ratio of length value L.
In addition, the application also provides a kind of display panel, the display panel includes:
Array substrate；
Color membrane substrates, the array substrate are oppositely arranged with the color membrane substrates；
Liquid crystal layer, the liquid crystal layer is between the array substrate and the color membrane substrates；
Wherein, the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture
Plain area and the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the film crystal
Pipe group include the first film transistor of driving first picture element region switch, driving the second picture element region switch it is second thin
Film transistor and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions
Domain, each picture element region are provided with the picture element subelement, and every data line connects same row picture element subelement, and every is swept
Line connection is retouched with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, long
Angle value is L, connects the picture element subelement of same data line, and according to the sequence at the driving end for being gradually distance from data line, first is thin
The ratio of the width value W and length value L of film transistor and the second thin film transistor (TFT) are gradually increased or the width of third thin film transistor (TFT)
Angle value W and the ratio of length value L are gradually reduced.
The application applies in large size panel, by adjusting the thin film transistor (TFT) of picture element subelement each in array substrate
The channel sized of group such as connects the picture of same data line to realize the homogeneity of the color of different location in the case of big visual angle
Sub-prime unit adjusts first film transistor and the second thin film transistor (TFT) according to the sequence at the driving end for being gradually distance from data line
Width value and the ratio of length value be gradually increased, or adjustment third thin film transistor (TFT) width value and length value ratio by
Decrescence small, in this way, the charge rate of the thin film transistor (TFT) far from driving end is higher under the identical charging time, brighter display is solved
Data-signal postpones in large size panel the problem of transmission, so that the Color uniformity of panel different location, improves display
Effect.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
The acquisition others attached drawing shown according to these attached drawings.
Fig. 1 is the structural schematic diagram of pixel cell in the application array substrate；
Fig. 2 is the embodiment enlarged structure schematic diagram in Fig. 1 at A；
Fig. 3 is another embodiment enlarged structure schematic diagram in Fig. 1 at A；
Fig. 4 is the enlarged structure schematic diagram of another embodiment at A in Fig. 1；
Fig. 5 is the enlarged structure schematic diagram of still another embodiment at A in Fig. 1；
Fig. 6 is the schematic diagram of internal structure of thin film transistor (TFT) group in the application array substrate.
Drawing reference numeral explanation:
The embodiments will be further described with reference to the accompanying drawings for realization, functional characteristics and the advantage of the application purpose.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiment of the application, instead of all the embodiments.Base
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall in the protection scope of this application.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used in the embodiment of the present application
In explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if should
When particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being related to " first ", " second " etc. in this application is used for description purposes only, and should not be understood as referring to
Show or imply its relative importance or implicitly indicates the quantity of indicated technical characteristic." first ", " are defined as a result,
Two " feature can explicitly or implicitly include at least one of the features.In addition, the technical solution between each embodiment can
It to be combined with each other, but must be based on can be realized by those of ordinary skill in the art, when the combination of technical solution occurs
Conflicting or cannot achieve when, will be understood that the combination of this technical solution is not present, also not this application claims protection model
Within enclosing.
The application provides a kind of array substrate, is applied on large scale display panel, especially applies and adopt in array substrate
On display panel with 8 farmland 3T transistor controls pixel electrodes switch.
Referring to figs. 1 to Fig. 6, the application provides a kind of array substrate, and the array substrate includes:
Pixel cell 10, the pixel cell 10 include multiple picture element subelements 11, and multiple picture element subelements 11 have
Sequence arrangement, to form rows and columns picture element subelement 11；Each picture element subelement 11 includes the first picture element region 111 and the
Two picture element regions 112, wherein the area of first picture element region 111 and the second picture element region 112 is according to different model or different requirements
Certain proportion, such as area of the area of the first picture element region 111 less than the second picture element region 112 are set.
The array substrate further includes thin film transistor (TFT) group 40, wherein the thin film transistor (TFT) group 40 is 8 farmland 3T crystal
Pipe, including three transistors, specially first film transistor 41, the second thin film transistor (TFT) 42 and third thin film transistor (TFT) 43.
Each picture element subelement 11 be correspondingly connected with one group described in thin film transistor (TFT) group 40, the specific thin film transistor (TFT) group 40 connects
Between the first picture element region 111 and the second picture element region 112 of the picture element subelement 11, the first film transistor 41 and institute
State the connection of the first picture element region 111, for driving first picture element region 111 to switch, second thin film transistor (TFT) 42 with it is described
The connection of second picture element region 112, for driving second picture element region 112 to switch, the third thin film transistor (TFT) 43 and described the
Two thin film transistor (TFT)s 42 connection, for unloading the part electricity of second film crystal, to reduce second film crystal
The charge rate of pipe 42.For large scale display panel, the problem of mitigating big visual angle colour cast.
The array substrate further includes multiple data lines 20 and multi-strip scanning line 30, the data line 20 and scan line 30
It is arranged in a crossed manner to be partitioned into multiple picture element regions, each picture element region is provided with the picture element subelement 11, every data
Line 20 connects same row picture element subelement 11, and every connection of scan line 30 is the same as a line picture element subelement 11.The data line 20
Driving end is connected with data driver, and the driving end of the scan line 30 is connected with scanner driver, the thin film transistor (TFT) group
When the 40 opening picture element subelement 11, the data driver passes through the data line 20 to each picture element subelement 11
Charging.
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group 40 all has channel 401, the width in channel 401
Value is W, length value L, the picture element subelement 11 of same data line 20 is connected, according to the driving end for being gradually distance from data line 20
Sequence, the ratio of the width value W and length value L of first film transistor 41 and the second thin film transistor (TFT) 42 is gradually increased, or
The width value W of third thin film transistor (TFT) 43 and the ratio of length value L are gradually reduced.Namely first in each picture element subelement 11
Thin film transistor (TFT) 41 and the second thin film transistor (TFT) 42, according to the sequence at the driving end for being gradually distance from data line 20, width value W and length
The ratio of angle value L is gradually increased, so that first film transistor 41 and the second film in the picture element subelement 11 of last line
The width value W of transistor 42 and the ratio of length value L are maximum.Due to remoter first thin in the driving end apart from the data line 20
The ratio of the width value W and length value L of film transistor 41 and the second thin film transistor (TFT) 42 are bigger, in identical charging voltage and charging
Under time, charge rate is higher, brighter display, and each position color difference caused by postponing based on data-signal is avoided to ask
Topic, it is ensured that the homogeneity of color.
Referring in particular to Fig. 3, in one embodiment, so that the first film transistor 41 in each picture element subelement 11 and
Two thin film transistor (TFT)s 42, according to the sequence at the driving end for being gradually distance from data line 20, the ratio of width value W and length value L is gradually
The mode of increase includes: the first film transistor 41 and second in each picture element subelement 11 for connect same data line 20
Thin film transistor (TFT) 42 is gradually increased according to the sequence for driving end for being gradually distance from data line 20, width value W, and length value L is kept not
Become, to realize that the ratio of the width value W and the length value L are gradually increased.In the present embodiment, third thin film transistor (TFT) 43
Width value W and length value L it is constant.When the width value W of first film transistor 41 and the second thin film transistor (TFT) 42 is gradually increased,
The charge rate of the picture element subelement 11 can be improved, improve brightness.
Wherein, during first film transistor 41 and the second thin film transistor (TFT) 42 are gradually increased, the same picture element
The width of the width value W of the corresponding first film transistor 41 of subelement 11 and the ratio of length value L and the second thin film transistor (TFT) 42
Angle value W is identical with the ratio of length value L.
Referring in particular to Fig. 4, in another embodiment, so that the first film transistor 41 in each picture element subelement 11
With the second thin film transistor (TFT) 42, according to be gradually distance from data line 20 driving end sequence, the ratio of width value W and length value L
The mode being gradually increased further include: the first film transistor 41 in each picture element subelement 11 of connection same data line 20
With the second thin film transistor (TFT) 42 according to the sequence at the driving end for being gradually distance from data line 20, length value L is gradually reduced, width value W
It remains unchanged, to realize that the ratio of the width value W and the length value L are gradually increased.In the present embodiment, third film is brilliant
The width value W and length value L of body pipe 43 are constant.First film transistor 41 and the length value L of the second thin film transistor (TFT) 42 are gradually
When reduction, the ratio of width value and length value increases, and the charge rate of the picture element subelement 11 can be improved, and improves brightness.
Wherein, during first film transistor 41 and the second thin film transistor (TFT) 42 are gradually increased, the same picture element
The width of the width value W of the corresponding first film transistor 41 of subelement 11 and the ratio of length value L and the second thin film transistor (TFT) 42
Angle value W and the ratio of length value L also keep identical.
Referring in particular to Fig. 5, in another embodiment, so that 41 He of first film transistor in each picture element subelement 11
Second thin film transistor (TFT) 42, according to the sequence at the driving end for being gradually distance from data line 20, the ratio of width value W and length value L by
Cumulative big mode further include: in each picture element subelement 11 of connection same data line 20, previous picture element subelement 11
First film transistor 41 and the second thin film transistor (TFT) 42 width value W it is more brilliant than the first film of the latter picture element subelement 11
The width value W of body pipe 41 is small, and the length value L of the first film transistor 41 of the latter picture element subelement 11 is drawn than the latter again
The length value L of the first film transistor 41 of sub-prime unit 11 is big, and the ratio of previous width value W and length value L, after being less than
The ratio of one width value W and length value L, and the ratio of the latter width value W and length value L are less than the latter width value W again
With the ratio of length value L.
Namely each picture element subelement 11 can be randomly selected by increasing width value W mode and increase width value W and length
The ratio of angle value L also can choose by way of reducing length value L and change the ratio of width value W and length value L, as long as
Guarantee the width value W and length value L of the first film transistor 41 and the second thin film transistor (TFT) 42 in each picture element subelement 11
Ratio be gradually increased.
It is to be appreciated that the width value W of first film transistor 41 and the ratio of length value L and the second thin film transistor (TFT) 42
Width value W and the ratio of length value L can also be different, such as the width value W of first film transistor 41 and the ratio of length value L
For a, and the width value W of the second thin film transistor (TFT) 42 and the ratio of length value L are k*a, wherein k is constant, with line number by
Cumulative to add, the ratio of the width value W and length value L of first film transistor 41 and the second thin film transistor (TFT) 42 are gradually increased, but K
It is worth constant；When last line, the ratio of the width value W of first film transistor 41 and length value L to maximum value b, the second film
The width value W of transistor 42 and the ratio of length value L also reach maximum value K*b.Wherein b is greater than a.
Alternatively, referring in particular to Fig. 6 in still another embodiment, the transmission of data line 20 can be solved in the following ways and prolonged
When the problem of: third thin film transistor (TFT) 43 in each picture element subelement 11, according to the driving end for being gradually distance from data line 20
Sequentially, width value W and the ratio of length value L are gradually reduced, and the width of first film transistor 41 and the second thin film transistor (TFT) 42
Angle value W and the ratio of length value L remain unchanged.Since third thin film transistor (TFT) 43 is for unloading the second thin film transistor (TFT) 42
Voltage, the width value of the third thin film transistor (TFT) 43 at the driving end far from data line 20 and the ratio of length value are smaller,
The efficiency for unloading voltage is lower, so that the charge efficiency of the picture element subelement 11 at the driving end far from data line 20 is more highlighted
Degree is brighter, avoids the problem that based on each position color difference caused by data-signal delay, it is ensured that the homogeneity of color.
Wherein, the ratio of the width value W and length value L of the first film transistor 41 and the second thin film transistor (TFT) 42 are big
In the width value W of the third thin film transistor (TFT) 43 and the ratio of length value L, to prevent the electricity filled to the second thin film transistor (TFT) 42
All unloaded by the third thin film transistor (TFT) 43.Optionally, the width value W and length value L of the third thin film transistor (TFT) 43
Ratio linearly reduce.
The application applies in large size panel, by adjusting the film crystal of picture element subelement 11 each in array substrate
401 size of channel of pipe group 40 such as connects same data to realize the homogeneity of the color of different location in the case of big visual angle
The picture element subelement 11 of line 20 adjusts 41 He of first film transistor according to the sequence at the driving end for being gradually distance from data line 20
The width value of second thin film transistor (TFT) 42 and the ratio of length value are gradually increased, or the width of adjustment third thin film transistor (TFT) 43
The ratio of value and length value is gradually reduced, in this way, under the identical charging time, the charge rate of the thin film transistor (TFT) far from driving end
Higher, brighter display solves the problems, such as that data-signal postpones transmission in large size panel, so that the face of panel different location
Color homogeneity improves display effect.
It is understood that the width value W and length of first film transistor 41 described above and the second thin film transistor (TFT) 42
In the scheme that the ratio of angle value L is gradually increased, specific increase is according to the load of the processing procedure, data line 20 of the array substrate
Size, material and line width etc. are different and different.It determines especially by simulative debugging, is such as adjusted line by line using multiple increases
Examination selects the optimal increase of display effect to increase the width of each first film transistor 41 and the second thin film transistor (TFT) 12
The ratio of W and length L.Also because of the influence of the factors such as load, line width of data line 20, the first film transistor 41 and the
Non-linear increase can be set in the width value W of two thin film transistor (TFT)s 42 and the ratio of length value L, and specific increase can be according to phase
Depending on difference between adjacent two picture element subelements 11.And preferably, the first film transistor 41 and second film
The width value W of transistor 42 and the ratio of length value L linearly increase, and are easier to realize, and be easily manipulated.
Likewise, subtracting in the scheme that the width value W of third thin film transistor (TFT) 43 and the ratio of length value L are gradually reduced
In a small amount can be linear, it can also be nonlinear.
Optionally, in the picture element subelement 11 for connecting same data line 20, the area of each first picture element region 111
Unanimously, the area of each second picture element region 112 is also consistent.The application is mainly the channel for passing through and changing in thin film transistor (TFT) group 40
401 sizes are protected to increase the charge rate of picture element subelement 11 at the driving end far from data line 20 in order to ensure regulating effect
The area for demonstrate,proving each first picture element region 111 is also consistent, and the area of each second picture element region 112 is also consistent.
To achieve the goals above, the application also provides a kind of array substrate, referring in particular to Fig. 1 to Fig. 6, the array base
Plate includes:
Pixel cell 10, the pixel cell 10 include multiple picture element subelements 11, and each picture element subelement 11 wraps
Include the first picture element region 111 and the second picture element region 112；
Thin film transistor (TFT) group 40, each picture element subelement 11 is correspondingly connected with a cluster film transistor group 40, described thin
Film transistor group 40 includes the first film transistor 41 for driving first picture element region 111 to switch, driving second picture element
The second thin film transistor (TFT) 42 that area 112 switchs and the third thin film transistor (TFT) 43 being connect with second thin film transistor (TFT) 42；
Multiple data lines 20 and multi-strip scanning line 30, the data line 20 and scan line 30 are arranged in a crossed manner more to be partitioned into
A picture element region, each picture element region are provided with the picture element subelement 11, and every data line 20 connects same row picture element
Subelement 11, every connection of scan line 30 is the same as a line picture element subelement 11；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group 40 all has channel 401, the width in channel 401
Value is W, length value L, the picture element subelement 11 of same data line 20 is connected, according to the driving end for being gradually distance from data line 20
Sequence, the ratio of the width value W and length value L of first film transistor 41 and the second thin film transistor (TFT) 42 is gradually increased,
The width value W of three thin film transistor (TFT)s 43 and the ratio of length value L are gradually reduced, the first film transistor 41 and the second film
The width value W of transistor 42 and the ratio of length value L are greater than the width value W and length value L of the third thin film transistor (TFT) 43
Ratio.
Array substrate described in the present embodiment and the array substrate difference of above-described embodiment are, adjust simultaneously in the present embodiment
Save the width of three thin film transistor (TFT)s namely first film transistor 41 and the second thin film transistor (TFT) 42 in picture element subelement 11
While value W and the ratio of length value L are gradually increased, the width value W of third thin film transistor (TFT) 43 and the ratio of length value L are also adjusted
Value is gradually reduced.The ratio of the width value W and length value L of the first film transistor 41 and the second thin film transistor (TFT) 42 are gradually
Increase, can also be gradually increased the charge rate of each picture element subelement 11, and the width value W and length of third thin film transistor (TFT) 43
The ratio of value L is gradually reduced, and be can reduce the voltage discharging quantity of the second thin film transistor (TFT) 42, is further increased the second film crystal
The charge rate of pipe 42, it is seen then that each to adjust by the width value W of three thin film transistor (TFT)s of adjustment simultaneously and the ratio of length value L
The mode of the charge rate of a picture element subelement 11, can reduce the increase of the ratio of width value W and length value L, for larger
For size display screen, the first film transistor 41 of last line and the width of the second thin film transistor (TFT) 42 can be effectively prevented
Value W and the ratio of length value L are excessive.
The array substrate of the present embodiment and above-described embodiment beneficial effect having the same, i.e., under the identical charging time,
The charge rate of thin film transistor (TFT) far from driving end is higher, and brighter display solves data-signal and postpones in large size panel
The problem of transmission, so that the Color uniformity of panel different location, improves display effect, while being also possible that the first film is brilliant
The increase of the ratio of the width value W and length value L of body pipe 41 and the second thin film transistor (TFT) 42 is smaller.
In addition, the application also provides a kind of display panel, the display panel includes:
Array substrate；
Color membrane substrates, the array substrate are oppositely arranged with the color membrane substrates；
Liquid crystal layer, the liquid crystal layer is between the array substrate and the color membrane substrates；
Wherein, the array substrate includes:
Pixel cell 10, the pixel cell 10 include multiple picture element subelements 11, and each picture element subelement 11 wraps
Include the first picture element region 111 and the second picture element region 112；
Thin film transistor (TFT) group 40, each picture element subelement 11 is correspondingly connected with a cluster film transistor group 40, described thin
Film transistor group 40 includes the first film transistor 41 for driving first picture element region 111 to switch, driving second picture element
The second thin film transistor (TFT) 42 that area 112 switchs and the third thin film transistor (TFT) 43 being connect with second thin film transistor (TFT) 42；
Multiple data lines 20 and multi-strip scanning line 30, the data line 20 and scan line 30 are arranged in a crossed manner more to be partitioned into
A picture element region, each picture element region are provided with the picture element subelement 11, and every data line 20 connects same row picture element
Subelement 11, every connection of scan line 30 is the same as a line picture element subelement 11；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group 40 all has channel 401, the width in channel 401
Value is W, length value L, the picture element subelement 11 of same data line 20 is connected, according to the driving end for being gradually distance from data line 20
Sequence, the ratio of the width value W and length value L of first film transistor 41 and the second thin film transistor (TFT) 42 is gradually increased, or
The width value W of third thin film transistor (TFT) 43 and the ratio of length value L are gradually reduced.
The application discloses display panel using the array substrate of above-described embodiment, and therefore, the array substrate has
Effective effect, the application display panel also has the same effect, therefore the display panel of the application is realized in the big view of large scale
Under the display at angle, guarantees the homogeneity of the color of display panel different location, improve the display effect of the display panel.
The foregoing is merely the alternative embodiments of the application, are not intended to limit the scope of the patents of the application, all at this
Under the design of application, using equivalent transformation made by present specification and accompanying drawing content, or directly/it is used in other phases indirectly
The technical field of pass is included in the scope of patent protection of the application.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture element region
With the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the thin film transistor (TFT) group
Including driving first film transistor, the second film of driving the second picture element region switch of the first picture element region switch brilliant
Body pipe and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions,
Each picture element region is provided with the picture element subelement, and every data line connects same row picture element subelement, every scanning
Line is connected with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, length value
For L, the picture element subelement of same data line is connected, according to the sequence at the driving end for being gradually distance from data line, the first film is brilliant
The ratio of the width value W and length value L of body pipe and the second thin film transistor (TFT) are gradually increased or the width value of third thin film transistor (TFT)
W and the ratio of length value L are gradually reduced.
2. array substrate as described in claim 1, which is characterized in that the corresponding the first film of the same picture element subelement is brilliant
The width value W of body pipe and the ratio of length value L are identical as the ratio of the width value W of the second thin film transistor (TFT) and length value L.
3. array substrate as described in claim 1, which is characterized in that the first film transistor and second film are brilliant
The width value W of body pipe and the ratio of length value L linearly increase.
4. array substrate according to claim 1 to 3, which is characterized in that each picture element of connection same data line
The sequence of first film transistor and the second thin film transistor (TFT) according to the driving end for being gradually distance from data line in subelement, width
Value W is gradually increased, and length value L remains unchanged.
5. array substrate a method according to any one of claims 1-3, which is characterized in that each picture element of connection same data line
The sequence of first film transistor and the second thin film transistor (TFT) according to the driving end for being gradually distance from data line in unit, length value
L is gradually reduced, and width value W is remained unchanged.
6. array substrate as described in claim 1, which is characterized in that the first film transistor and the second thin film transistor (TFT)
Width value W and length value L ratio be greater than the third thin film transistor (TFT) width value W and length value L ratio.
7. array substrate as described in claim 1, which is characterized in that the width value W and length of the third thin film transistor (TFT)
The ratio of value L linearly reduces.
8. array substrate as described in claim 1, which is characterized in that in the picture element subelement of connection same data line, respectively
The area of a first picture element region is consistent, and the area of each second picture element region is also consistent.
9. a kind of array substrate, which is characterized in that the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture element region
With the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the thin film transistor (TFT) group
Including driving first film transistor, the second film of driving the second picture element region switch of the first picture element region switch brilliant
Body pipe and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions,
Each picture element region is provided with the picture element subelement, and every data line connects same row picture element subelement, every scanning
Line is connected with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, length value
For L, the picture element subelement of same data line is connected, according to the sequence at the driving end for being gradually distance from data line, the first film is brilliant
The ratio of the width value W and length value L of body pipe and the second thin film transistor (TFT) are gradually increased, the width value W of third thin film transistor (TFT)
It is gradually reduced with the ratio of length value L, the width value W and length value L of the first film transistor and the second thin film transistor (TFT)
Ratio be greater than the third thin film transistor (TFT) width value W and length value L ratio.
10. a kind of display panel, which is characterized in that the display panel includes:
Array substrate；
Color membrane substrates, the array substrate are oppositely arranged with the color membrane substrates；
Liquid crystal layer, the liquid crystal layer is between the array substrate and the color membrane substrates；
Wherein, the array substrate includes:
Pixel cell, the pixel cell include multiple picture element subelements, and each picture element subelement includes the first picture element region
With the second picture element region；
Thin film transistor (TFT) group, each picture element subelement are correspondingly connected with a cluster film transistor group, the thin film transistor (TFT) group
Including driving first film transistor, the second film of driving the second picture element region switch of the first picture element region switch brilliant
Body pipe and the third thin film transistor (TFT) being connect with second thin film transistor (TFT)；
Multiple data lines and multi-strip scanning line, the data line and scan line are arranged in a crossed manner to be partitioned into multiple picture element regions,
Each picture element region is provided with the picture element subelement, and every data line connects same row picture element subelement, every scanning
Line is connected with a line picture element subelement；
Wherein, each thin film transistor (TFT) in the thin film transistor (TFT) group all has channel, and the width value in channel is W, length value
For L, the picture element subelement of same data line is connected, according to the sequence at the driving end for being gradually distance from data line, the first film is brilliant
The ratio of the width value W and length value L of body pipe and the second thin film transistor (TFT) are gradually increased or the width value of third thin film transistor (TFT)
W and the ratio of length value L are gradually reduced.
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| CN201910509298.1A CN110346992A (en) | 2019-06-11 | 2019-06-11 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910509298.1A CN110346992A (en) | 2019-06-11 | 2019-06-11 | Array substrate and display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951174A (en) * | 2021-03-30 | 2021-06-11 | 长沙惠科光电有限公司 | Pixel driving circuit, display device and driving method of pixel driving circuit |
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Application publication date: 20191018 |