CN110337643A - Chip, processor, computer system and movable equipment - Google Patents
Chip, processor, computer system and movable equipment Download PDFInfo
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- CN110337643A CN110337643A CN201880012524.9A CN201880012524A CN110337643A CN 110337643 A CN110337643 A CN 110337643A CN 201880012524 A CN201880012524 A CN 201880012524A CN 110337643 A CN110337643 A CN 110337643A
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 34
- 238000010586 diagram Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 9
- 230000015654 memory Effects 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005183 dynamical system Methods 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- RZVHIXYEVGDQDX-UHFFFAOYSA-N 9,10-anthraquinone Chemical compound C1=CC=C2C(=O)C3=CC=CC=C3C(=O)C2=C1 RZVHIXYEVGDQDX-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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- 239000000463 material Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
Disclose a kind of chip, processor, computer system and movable equipment.The chip includes multiple subsystems；The first interface of the first system bus and peripheral bus is provided in the first subsystem in the multiple subsystem, the first interface is connect with the first system bus；The second interface of second system bus and the peripheral bus is provided in the second subsystem in the multiple subsystem, the second interface is connect with the second system bus.The technical solution of the embodiment of the present invention is able to ascend the performance of chip.
Description
Copyright notice
This patent document disclosure includes material protected by copyright.The copyright is all for copyright holder.Copyright holder does not oppose that the patent document or the patent in the presence of anyone replicates the proce's-verbal of Patent&Trademark Office and archives disclose.
The present invention relates to information technology fields, and more particularly, to a kind of chip, processor, computer system and movable equipment.
In existing chip design, interconnecting for multiple subsystems can be related to by having.It might have multiple subsystems in one chips, for example, application processor (Application Processor, AP) subsystem, media subsystem, communication subsystem, winged control subsystem etc., need corresponding access passage between subsystems.
Current chip design is using Advanced High-Performance Bus (Advanced High Performance Bus, AHB) or the bus of level expansion interface (Advanced eXtensible Interface, AXI) bus etc completes exchanging visit function.Such as: if AP subsystem, which will access, flies control subsystem, then master (master) interface is reserved in the ahb bus of AP subsystem, one is reserved from (slave) interface in the ahb bus for flying control subsystem, the two interfaces are connected when integrated, to guarantee the presence of access passage.However, the on-chip bus structure due to AHB and AXI has stringent timing requirements, once the signal during bus transfer has exception, it is easy to and cause winged control subsystem to hang dead or even whole chips and hang extremely, influences the performance of chip.
Summary of the invention
The embodiment of the invention provides a kind of chip, processor, computer system and movable equipments, are able to ascend the performance of chip.
In a first aspect, providing a kind of chip, the chip includes multiple subsystems；The first interface of the first system bus and peripheral bus is provided in the first subsystem in the multiple subsystem, the first interface is connect with the first system bus；The second interface of second system bus and the peripheral bus is provided in the second subsystem in the multiple subsystem, the second interface is connect with the second system bus.
Second aspect provides a kind of processor, the chip including above-mentioned first aspect.
The third aspect provides a kind of computer system, the processor of chip or second aspect including above-mentioned first aspect.
Fourth aspect provides a kind of movable equipment, comprising: the chip of above-mentioned first aspect；Alternatively, the processor of above-mentioned second aspect；Alternatively, the computer system of the above-mentioned third aspect.
The technical solution of the embodiment of the present invention, by peripheral bus realize chip interior subsystem connection, can prevent system bus is hung as caused by timing requirements extremely and subsystem extension it is dead, so as to promote the performance of chip.
Fig. 1 is the schematic diagram using the multiple subsystem chip of the technical solution of the embodiment of the present invention.
Fig. 2 is the schematic diagram of the movable equipment of one embodiment of the invention.
Fig. 3 is the schematic diagram of the chip of one embodiment of the invention.
Fig. 4 is the schematic diagram of the chip of another embodiment of the present invention.
Fig. 5 is the schematic diagram of the computer system of the embodiment of the present invention.
Fig. 6 is the schematic diagram of the movable equipment of another embodiment of the present invention.
Below in conjunction with attached drawing, technical solution in the embodiment of the present invention is described.
It should be understood that specific example herein is intended merely to that those skilled in the art is helped to more fully understand the embodiment of the present invention, the range for the embodiment that is not intended to limit the present invention.
It should also be understood that various embodiments described in this specification, both can individually implement, implementation can also be combined, the embodiment of the present invention does not limit this.
The technical solution of the embodiment of the present invention can be applied to multiple subsystem chip, and multiple subsystems may include AP subsystem, media subsystem, communication subsystem, fly to control subsystem etc., but the embodiment of the present invention does not limit this.
Fig. 1 shows the schematic diagram of the multiple subsystem chip using the technical solution of the embodiment of the present invention.
As shown in Figure 1, chip 100 includes AP subsystem 110 and flies to control subsystem 120.It should be understood that chip 100 can also include other unshowned subsystems in Fig. 1, only it is illustrated by AP subsystem 110 and for flying control subsystem 120 in Fig. 1, repeats no more below.AP subsystem 110 and winged control subsystem 120 are set in a chips.Interconnecting and can be realized by system bus between AP subsystem 110 and winged control subsystem 120, such as ahb bus (shown in Fig. 1) or AXI bus.Here the quantity of ahb bus with no restrictions, can be one, connect bus and system by ahb bus；Can also have a plurality of, multiple bus be connected by ahb bus interface, embodiment do not define this.
AHB and AXI bus has stringent timing requirements, that is, after the operation in a upper period is completed, can just continue the operation in next period.By taking Fig. 1 as an example, after AP subsystem 110 sends read operation instruction to winged control subsystem 120, next corresponding data will be transmitted to AP subsystem 110 by flying control subsystem 120, and after data transmission success, subsequent operation can just be continued by flying control subsystem 120.After if AP subsystem 110 sends read operation instruction to winged control subsystem 120, AP subsystem 110, which goes wrong, to be needed to be reset, in this case, flying control subsystem 120 cannot be successfully received to the data that AP subsystem 110 transmits, and may result in winged control subsystem 120 in this way can not continue subsequent operation and hang dead.
In view of the above problems, the embodiment of the invention provides a kind of improved technical solutions, and portion passes through peripheral bus, such as Serial Peripheral Interface (SPI) (Serial Peripheral Interface in the chip, SPI) bus connects subsystem, so that subsystem be avoided to hang dead situation.
The technical solution of the embodiment of the present invention can be applied in various movable equipments.The movable equipment can be unmanned plane, unmanned ship, automatic driving vehicle or robot etc., but the embodiment of the present invention does not limit this.
Fig. 2 is the schematic architectural diagram of the movable equipment 200 of the embodiment of the present invention.
As shown in Fig. 2, movable equipment 200 may include dynamical system 210, control system 220, sensor-based system 230 and processing system 240.
Dynamical system 210 is used to provide power for the movable equipment 200.
By taking unmanned plane as an example, the dynamical system of unmanned plane may include electron speed regulator (referred to as electricity is adjusted), propeller and motor corresponding with propeller.Motor is connected between electron speed regulator and propeller, and motor and propeller are arranged on corresponding horn；Electron speed regulator is used to receive the driving signal of control system generation, and provides driving current to motor, to control the revolving speed of motor according to driving signal.Motor is for driving propeller to rotate, so that the flight for unmanned plane provides power.
Sensor-based system 230 can be used for measuring the posture information of movable equipment 200, i.e., movable equipment 200 space location information and status information, for example, three-dimensional position, three-dimensional perspective, three-dimensional velocity, three-dimensional acceleration and three-dimensional angular velocity etc..Sensor-based system 230 for example may include gyroscope, electronic compass, Inertial Measurement Unit (Inertial Measurement Unit, IMU), at least one of sensors such as visual sensor, global positioning system (Global Positioning System, GPS), barometer, pitot meter.
In embodiments of the present invention, sensor-based system 230 can also be used to acquire image, i.e. sensor-based system 230 includes the sensor for acquiring image, such as camera etc..
Control system 220 is used to control the movement of movable equipment 200.Control system 220 can control movable equipment 200 according to pre-set program instruction.For example, control system 220 can be according to the movement of the posture information control movable equipment 200 for the movable equipment 200 that sensor-based system 230 measures.Control system 220 can also control movable equipment 200 according to the control signal from remote controler.For example, control system 220 can be flight control system (flying control), or for unmanned plane to fly the control circuit in control.
Processing system 240 can handle the image of the acquisition of sensor-based system 230.For example, processing system 240 can be image signal process (Image Signal Processing, ISP) class chip.
It should be understood that each building block of division and name above-mentioned to(for) movable equipment 200 are only exemplary, it is not construed as the limitation to the embodiment of the present invention.
It should also be understood that movable equipment 200 can also include unshowned other component in Fig. 2, the embodiment of the present invention does not limit this.
In some possible designs, above-mentioned control system 220 and processing system 240 be can be set in a chips, i.e., control system 220 and processing system 240 can be the subsystem in chip, which can use the technical solution of following embodiment of the present invention.
Fig. 3 shows the schematic diagram of the chip 300 of the embodiment of the present invention.Chip 300 includes multiple subsystems, schematically illustrates the first subsystem 310 and the second subsystem 320 in Fig. 3, but the embodiment of the present invention does not limit this.
The first interface 312 of the first system bus 311 and peripheral bus is provided in the first subsystem 310 in multiple subsystems of chip 300, the first interface 312 is connect with the first system bus 311.
The second interface 322 of second system bus 321 and the peripheral bus is provided in the second subsystem 320 in the multiple subsystem, the second interface 322 is connect with the second system bus 321.
Specifically, the first system bus 311 can connect multiple system bus interfaces, it is connect by multiple system bus interfaces with other subsystems in chip 300.Similarly, second system bus 321 also can connect multiple system bus interfaces, be connect by multiple system bus interfaces with other subsystems in chip 300.In embodiments of the present invention, the first system bus 311 and second system bus 321 are also connected with peripheral bus interface, that is the first interface 312 that connects above-mentioned peripheral bus of the first system bus 311, second system bus 321 connects the second interface 322 of above-mentioned peripheral bus, in this way, it, can be by including that the peripheral bus of the first interface 312 and the second interface 322 is communicated for the first subsystem 310 and the second subsystem 320.
Specifically, first subsystem 310 can access the first interface 312 by the first system bus 311, second subsystem 320 can access the second interface 322 by the second system bus 321, so that first subsystem 310 can be communicated with second subsystem 320 by the peripheral bus.
The first system bus 311 and the second system bus 321 can be the system bus of interconnection in various chips, such as ahb bus or AXI bus, but the embodiment of the present invention does not limit this.
The peripheral bus can between spi bus, integrated circuit (Inter-Integrated Circuit, I2C) bus or universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) bus, but the embodiment of the present invention does not also limit this.
Optionally, the first system bus 311 is not connected to the second system bus 321.
That is, the first subsystem 310 is not directly connected to the second subsystem 320 by system bus.
It should be understood that, since the first subsystem 310 can be connect by system bus with other subsystems, second subsystem 320 can also be connect by system bus with other subsystems, in such a case, it is possible to think that the first subsystem 310 is indirectly connected with the second subsystem 320 by system bus.
Optionally, the first system bus 311 is connect with the second system bus 321 by system bus.
Optionally, the first system bus 311 is connected with the second system bus 321 except through the peripheral bus outer, also it is connected by system bus, it can choose a part request and subsequent interaction completed by system bus, a part request and subsequent interaction are completed by peripheral bus and peripheral bus interface.For example, the first subsystem 310 completes the request of the second subsystem 320 and subsequent interaction by system bus, the second subsystem 320 completes the request of the first subsystem 310 and subsequent interaction by peripheral bus.
Two interfaces of peripheral bus, i.e., in first interface 312 and second interface 322, an interface is master interface, another interface is slave interface.For example, first interface 312 is master interface, second interface 322 is slave interface.In this case, the first interface 312 is used to send the operational order of first subsystem to the second interface.That is, first interface 312 actively initiates operation, and then, first interface 312 and second interface 322 are transmitted accordingly respectively in the case that first interface 312 is master interface.
Optionally, in an embodiment of the invention, the first interface 312 is used to receive the first data of first subsystem, and transmits first data to the second interface.
Such as, in the case where the first subsystem 310 writes the first data to the second subsystem 320, first data are sent to first interface 312 by the first subsystem 310, first interface 312 is by peripheral bus by first data transmission to second interface 322, the second last subsystem 320 obtains the first data from second interface 322, to complete the process that the first subsystem 310 writes the first data to the second subsystem 320.
In the case where first data transmission failure, such as, in the case that second subsystem 320 is hung extremely, since the first subsystem 310 has arrived first data storage in first interface 312, such as store into the caching of first interface 312, therefore, in this case, first subsystem 310 can continue subsequent operation, will not send because of first data and not go out and hang dead.
Optionally, for the first interface 312 when transmitting first data failure to the second interface 322, the first subsystem of Xiang Suoshu 310 sends the first error indication signal, and/or, reset the first interface.
Specifically, when transmitting first data failure to the second interface 322, the first interface 312 can send error indication signal to first subsystem 310, to indicate the first data transmission failure, in this way, first subsystem 310 can transmit first data again；The first interface 312 can also reset the first interface 312, to remove first data that the first interface 312 is stored, in order to which first subsystem 310 transmits first data again.
Optionally, in an embodiment of the invention, the second interface 322 is used to receive the second data of second subsystem 320, and transmits second data to the first interface 312.
Such as, in the case where the first subsystem 310 reads the second data from the second subsystem 320, second data are sent to second interface 322 by the second subsystem 320, second data are transferred to first interface 312 by peripheral bus by second interface 322, last first subsystem 310 obtains the second data from first interface 312, to complete the process that the first subsystem 310 reads the second data from the second subsystem 320.
Similarly, in the case where the second data transmission fails, such as, in the case that first subsystem 310 is hung extremely, since the second subsystem 320 has arrived second data storage in second interface 322, such as storage is into the caching of second interface 322, therefore, in this case, the first subsystem 310 can continue subsequent operation, will not send because of first data and not go out and hang dead.
Optionally, for the second interface when transmitting second data failure to the first interface, the second subsystem of Xiang Suoshu sends the second error indication signal, and/or, reset the second interface.
Specifically, when transmitting first data failure to the first interface 312, the second interface 322 can send error indication signal to second subsystem 320, to indicate second data transmission fails, in this way, second subsystem 320 can transmit second data again；The second interface 322 can also reset the second interface 322, to remove second data that the second interface 322 is stored, in order to which second subsystem 320 transmits second data again.
It should be understood that if the first subsystem 310 is only needed actively to initiate the second subsystem 320 operation, it is master interface that first interface 312, which can be set, and second interface 322 is slave interface between the first subsystem 310 and the second subsystem 320；If the second subsystem 320 is only needed actively to initiate the first subsystem 310 operation, it is master interface that second interface 322, which can be set, and first interface 312 is slave interface；If the first subsystem 310 and the second subsystem 320 require actively to initiate operation, two pairs of peripheral bus interfaces then can be set, a pair of of interface is master interface in the first subsystem 310, another pair interface is master interface in the second subsystem 320, or, a pair of of peripheral bus interface is set, two-way operation is completed by using the mode of system break.
One subsystem can also be separately connected multiple subsystems by multiple peripheral bus interfaces.For example, can also be connected using the peripheral bus between similar first subsystem 310 and the second subsystem 320, between the first subsystem 310 and third subsystem for sake of simplicity, no longer repeating one by one.
The technical solution of the embodiment of the present invention, by peripheral bus realize chip interior subsystem connection, can prevent system bus is hung as caused by timing requirements extremely and subsystem extension it is dead, so as to promote the performance of chip.
Below with reference to Fig. 4, the technical solution of the embodiment of the present invention is described so that chip includes AP subsystem and flies control subsystem as an example.It should be understood that Fig. 4 is a kind of example, the restriction to the embodiment of the present invention should not be construed as.
As shown in figure 4, chip 400 includes AP subsystem 410 and flies to control subsystem 420.The ahb bus 411 of AP subsystem 410 connects the master interface 412 of spi bus.The ahb bus 421 for flying control subsystem 420 connects the slave interface 422 of spi bus.In this way, AP subsystem 410 and winged control subsystem 420 pass through spi bus and realize connection inside chip 400.It is not accessed mutually between the ahb bus 411 of AP subsystem 410 and the ahb bus 421 for flying control subsystem 420.
When being communicated, AP subsystem 410 can access the master interface 412 of spi bus by ahb bus 411 for AP subsystem 410 and winged control subsystem 420, and flying control subsystem 420 can be by the slave interface 422 of the access spi bus of ahb bus 421.
For example, AP subsystem 410 sends read operation order to winged control subsystem 420 by master interface 412 when AP subsystem 410 will read the data for flying control subsystem 420.After winged control subsystem 420 receives the multioperation order, slave interface 422 is sent the data to, for example, the data are possibly stored in the caching of slave interface 422.Then slave interface 422 sends the data to master interface 412 according to the clocked sequential that master interface 412 provides, and AP subsystem 410 reads data from master interface 412 again.
If communication occurs abnormal due to certain problems between master interface 412 and slave interface 422, can individually reset the two interfaces, and restart to interact, will not sub-system and ahb bus impact.For example, will not influence the stability of ahb bus 421 if AP subsystem 410 hangs dead or even 412 logic of master interface for some reason hangs the mistake for extremely also only influencing whether that slave interface 422 transmits data, so that winged control subsystem 420 will not be caused to hang extremely.
Therefore, through the above scheme, it can be ensured that other subsystems are when access flies control subsystem, even if other subsystems are hung in the dust for some reason, flying control subsystem be can still work normally.
The embodiment of the invention also provides a kind of processor, which may include the chip of the various embodiments of aforementioned present invention.
Fig. 5 shows the schematic block diagram of the computer system 500 of the embodiment of the present invention.
As shown in figure 5, the computer system 500 may include processor 510 and memory 520.
It should be understood that can also include component usually included in other computer systems in computer system, for example, input-output equipment, communication interface etc., the embodiment of the present invention does not limit this.
Memory 520 is for storing computer executable instructions.
Memory 520 can be various memories, it such as may include high-speed random access memory (Random Access Memory, RAM), can also include non-labile memory (non-volatile memory), for example, at least a magnetic disk storage, the embodiment of the present invention do not limit this.
Processor 510 executes the computer executable instructions for accessing the memory 520.
In some possible designs, processor 510 may include the chip of the various embodiments of aforementioned present invention.That is, processor 510 can be using the multiple subsystem chip in the various embodiments of aforementioned present invention.
The embodiment of the invention also provides a kind of movable equipment, which may include the chip, processor or computer system of the various embodiments of aforementioned present invention.
Fig. 6 shows the schematic diagram of the movable equipment 600 of one embodiment of the invention.
Fig. 6 is using the movable equipment 200 of the chip of the embodiment of the present invention, and the function of each system therein is identical as the movable equipment 200 in Fig. 2.Control system 220 and processing system 240 are set in a chip 610 using the technical solution of the embodiment of the present invention in Fig. 6, wherein, control system 220 and processing system 240 can correspond respectively to the first subsystem and the second subsystem in multiple subsystems in the chip of the embodiments of the present invention.In this way, control system 220 will not be hung extremely since the extension of the processing system 240 of access control system 220 is dead, so as to ensure the normal movement of movable equipment 600.
It should be understood that in embodiments of the present invention, term "and/or" is only a kind of incidence relation for describing affiliated partner, indicate may exist three kinds of relationships.For example, A and/or B, can indicate: individualism A exists simultaneously A and B, these three situations of individualism B.In addition, character "/" herein, typicallys represent the relationship that forward-backward correlation object is a kind of "or".
It is described above; only a specific embodiment of the invention; but scope of protection of the present invention is not limited thereto; anyone skilled in the art is in the technical scope disclosed by the present invention; various equivalent modifications or substitutions can be readily occurred in, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (16)
- A kind of chip, which is characterized in that the chip includes multiple subsystems；The first interface of the first system bus and peripheral bus is provided in the first subsystem in the multiple subsystem, the first interface is connect with the first system bus；The second interface of second system bus and the peripheral bus is provided in the second subsystem in the multiple subsystem, the second interface is connect with the second system bus.
- Chip according to claim 1, it is characterized in that, first subsystem passes through first interface described in the first system bus access, second subsystem is communicated with second subsystem by the peripheral bus by second interface described in the second system bus access, first subsystem.
- Chip according to claim 1 or 2, which is characterized in that the first system bus is not connected to the second system bus.
- Chip according to claim 1 or 2, which is characterized in that the first system bus is connect with the second system bus by system bus.
- Chip according to any one of claim 1 to 4, which is characterized in that the first interface is used to send the operational order of first subsystem to the second interface.
- Chip according to any one of claim 1 to 5, which is characterized in that the first interface is used to receive the first data of first subsystem, and transmits first data to the second interface.
- Chip according to claim 6, which is characterized in that the first interface is used for when transmitting first data failure to the second interface, and the first subsystem of Xiang Suoshu sends the first error indication signal, and/or, reset the first interface.
- Chip according to any one of claim 1 to 7, which is characterized in that the second interface is used to receive the second data of second subsystem, and transmits second data to the first interface.
- Chip according to claim 8, which is characterized in that the second interface is used for when transmitting second data failure to the first interface, and the second subsystem of Xiang Suoshu sends the second error indication signal, and/or, reset the second interface.
- Chip according to any one of claim 1 to 9, which is characterized in that the first system bus and the second system bus are Advanced High-Performance Bus AHB or level expansion interface AXI bus.
- Chip according to any one of claim 1 to 10, which is characterized in that the peripheral bus I2C bus or universal asynchronous receiving-transmitting transmitter bus between serial peripheral equipment interface SPI bus, integrated circuit.
- Chip according to any one of claim 1 to 11, which is characterized in that first subsystem is application processor AP subsystem；Second subsystem is to fly control subsystem.
- Chip according to claim 12, which is characterized in that the peripheral bus is spi bus.
- A kind of processor, which is characterized in that including chip according to any one of claim 1 to 13.
- A kind of computer system characterized by comprisingChip according to any one of claim 1 to 13 or processor according to claim 14.
- A kind of movable equipment characterized by comprisingChip according to any one of claim 1 to 13；Alternatively,Processor according to claim 14；Alternatively,Computer system according to claim 15.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/073788 WO2019144267A1 (en) | 2018-01-23 | 2018-01-23 | Chip, processor, computer system, and mobile device |
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| CN110337643A true CN110337643A (en) | 2019-10-15 |
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| CN201880012524.9A Pending CN110337643A (en) | 2018-01-23 | 2018-01-23 | Chip, processor, computer system and movable equipment |
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| US (1) | US20200349104A1 (en) |
| CN (1) | CN110337643A (en) |
| WO (1) | WO2019144267A1 (en) |
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| CN110156078B (en) * | 2019-04-17 | 2020-07-24 | 北京航空航天大学 | Preparation method and application of potassium-vanadium-oxygen ternary compound |
| CN114880267B (en) * | 2022-07-11 | 2022-10-04 | 南京芯驰半导体科技有限公司 | Multi-chip interconnection system and method thereof |
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2018
- 2018-01-23 CN CN201880012524.9A patent/CN110337643A/en active Pending
- 2018-01-23 WO PCT/CN2018/073788 patent/WO2019144267A1/en active Application Filing
-
2020
- 2020-07-22 US US16/935,746 patent/US20200349104A1/en not_active Abandoned
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| Publication number | Publication date |
|---|---|
| WO2019144267A1 (en) | 2019-08-01 |
| US20200349104A1 (en) | 2020-11-05 |
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