CN110336538B - CMOS capacitor neutralization active mixer - Google Patents

CMOS capacitor neutralization active mixer Download PDF

Info

Publication number
CN110336538B
CN110336538B CN201910304159.5A CN201910304159A CN110336538B CN 110336538 B CN110336538 B CN 110336538B CN 201910304159 A CN201910304159 A CN 201910304159A CN 110336538 B CN110336538 B CN 110336538B
Authority
CN
China
Prior art keywords
nmos transistor
capacitor
stage
frequency voltage
intermediate frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910304159.5A
Other languages
Chinese (zh)
Other versions
CN110336538A (en
Inventor
郭本青
王雪冰
陈鸿鹏
龚静
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201910304159.5A priority Critical patent/CN110336538B/en
Publication of CN110336538A publication Critical patent/CN110336538A/en
Application granted granted Critical
Publication of CN110336538B publication Critical patent/CN110336538B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides a CMOS (complementary metal oxide semiconductor) capacitor neutralizing active mixer, belonging to the field of mixers. The active frequency mixer comprises a transconductance input stage, a switch frequency mixing stage and an output load stage, wherein a received radio frequency voltage signal is converted into an intermediate frequency voltage signal through the frequency mixer and is output. The invention uses two capacitive cross coupling circuit units in the transconductance input stage in an improved way to generate low noise index, and the two capacitive cross coupling circuit units are connected through an NMOS/PMOS stacked structure, thereby effectively saving the power consumption of the circuit; the bandwidth is effectively enhanced by designing a passive matching network; the capacitance neutralization technology is used for compensating the source-drain parasitic effect of the transconductance input stage and enhancing the loop gain of the transconductance stage, thereby improving the isolation and the linearity of the mixer.

Description

CMOS capacitor neutralization active mixer
Technical Field
The invention belongs to the field of mixers, and particularly relates to a CMOS (complementary metal oxide semiconductor) capacitor neutralizing active mixer.
Background
Configurable wireless transceivers that accommodate multi-band and multi-mode communication protocols are being widely adopted worldwide, and in their hardware implementation, the parameters of the receiver's wideband, low noise, and high linearity require significant consideration for the circuit designer. In a typical receive chain, a down-conversion mixer, which is one of the key building blocks, has a significant impact on the noise and linearity of the receiver. Thus, the design of the mixer is fraught with challenges.
While passive mixers are becoming increasingly popular due to good linearity and low flicker noise, the inherent conversion loss and poor port isolation of such mixers typically create larger noise figure and IQ crosstalk problems. In contrast, an active mixer has high conversion gain and excellent port isolation, and can provide better noise suppression for a subsequently constructed module. In an active mixer, commonly referred to as a gilbert mixer, a pair of switches driven by a large local oscillator signal is used to commutate the rf current and perform the rf to if frequency conversion.
The noise of the active mixer mainly comes from the thermal noise of the rf transconductance stage and the flicker noise of the switching stage. In order to reduce the Flicker Noise of the switching stage, it is common practice to use a current injection type active mixer (j.park, c. -h.lee, b. -s.kim, and j.laskar, "Design and Analysis of Low Flicker-Noise CMOS Mixers for D-direction-Conversion Receivers," IEEE trans.micro.thermal tech., vol.54, No.12, pp.4372-4380, dec.2006.) as shown in fig. 1. The constant current source provides most of bias current for the transconductance stage, so that direct current flowing through the switching tube is reduced, and flicker noise of the mixing switching stage is reduced. However, the consequence of this is that a large parasitic capacitance is introduced at the source of the switching stage, while the constant current source itself does not provide gain but introduces noise; and its load resistor is high in resistance, which degrades the linearity performance of the mixer. In addition, a low Noise Mixer circuit (b.guo, h.wang, and g.yang, "a wide band target CMOS Active Mixer amplification Noise Cancellation and linearity Enhancement," IEEE trans.micro.thermal tech., vol.62, No.9, pp.2084-2091, Se p.2014.) as shown in fig. 2 uses the coupling of the matching network to achieve an increase in bandwidth and the Noise Cancellation transconductance stage reduces the Noise figure of the circuit. Also, a switching transconductance mixer has been proposed (e.a. klumperink, s.m. louwsma, g.j.wienk, and b.nauta, "a cmos switched transconductor mixer," IEEE j.solid-State circuits, vol.39, No.8, pp.1231-1240,2004.) which inputs a local oscillator signal from a tail Circuit transistor so that the transconductance transistor is turned on with a low noise figure. However, because the tail current transistor needs to be operated in the triode region, a large ac local oscillator signal is required, which in turn poses a challenge to the performance of port isolation.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a CMOS capacitive-neutral active mixer, in which two capacitive cross-coupled circuit units are designed, and NMOS transistors and PMOS transistors in the two capacitive cross-coupled circuit units are stacked and connected, so that the circuit has low noise, high bandwidth, high linearity and isolation, and also has a good balance between power consumption.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a CMOS capacitor neutralization active frequency mixer comprises a transconductance input stage, a switch mixing stage and an output load stage, wherein the transconductance input stage receives a radio frequency voltage signal, converts the radio frequency voltage signal into a radio frequency current signal, then inputs the radio frequency current signal into the switch mixing stage, the switch mixing stage periodically commutates the current signal to convert the frequency of the current signal from the radio frequency to the intermediate frequency, then transmits the intermediate frequency current signal to the output load stage, and the output load stage converts the intermediate frequency current signal into an intermediate frequency voltage signal for outputntr1And a second neutralization capacitor Cntr2。
Further, the two capacitive cross-coupling circuit units are stacked and connected through NMOS transistors and PMOS transistors in the units.
Further, the transconductance input stage comprises a first PMOS transistor Mp1A second PMOS transistor Mp2And a first NMOS transistor Mn1A second NMOS transistor Mn2(ii) a Wherein the first PMOS transistor Mp1And a first nmos transistor Mn1Is connected to the drain of the first capacitor via a second neutralizing capacitor Cntr2Negative electrode connected with radio frequency voltage-VinSecond PMOS transistor Mp2And the second NMOS transistor Mn2Is connected through a first neutralizing capacitor Cntr1Positive electrode + V connected with radio frequency voltageinFirst PMOS transistor Mp1Is connected to the gate via a first capacitor Ccp1Is connected to the second PMOS transistor Mp2Source stage of (1), second PMOS transistor Mp2Is passed through a second capacitor Ccp2Is connected to the first PMOS transistor Mp1Source stage of (1), first NMOS transistor Mn1Is passed through a fourth capacitor Ccn2Is connected to the second NMOS transistor Mn2Source stage of (1), second NMOS transistor Mn2Is passed through a third capacitor Ccn1Is connected to the first NMOS transistor Mn1A source stage of (a); first electricityContainer Ccp1Second terminal of (2) is connected with a first inductor LspA second terminal of the first capacitor Ccp2First end of (2) is connected with a first inductor LspA first terminal of (C), a third capacitor Ccn1First end of the first inductor L is connected with the second inductor LsnFirst terminal of (1), fourth capacitor Ccn2Second end of (2) is connected with a second inductor LsnA second end of (a); first PMOS transistor Mp1And a second PMOS transistor Mp2Respectively connected with the first inductor LspFirst and second terminals of the first NMOS transistor Mn1And the second NMOS transistor Mn2Respectively connected with the second inductors LsnFirst and second terminals of a first inductor LspThe first end passes through a fifth capacitor C5Connected to positive + V of radio-frequency voltageinSecond inductance LsnThrough a sixth capacitor C6Connected to positive + V of radio-frequency voltageinFirst inductance LspThe second end passes through a seventh capacitor C7Connected to the negative pole-V of the radio-frequency voltageinSecond inductance LsnThrough an eighth capacitor C8Connected to the negative pole-V of the radio-frequency voltageinFirst inductance LspThird terminal of (2) is connected with a power supply VDDSecond inductance LsnThe transconductance input stage is used for receiving a radio frequency voltage signal and converting the radio frequency voltage signal into a radio frequency current signal, so that the circuit noise is reduced.
Further, the switching mixer stage comprises a third NMOS transistor M3A fourth NMOS transistor M4The fifth NMOS transistor M5And a sixth NMOS transistor M6(ii) a Wherein the third NMOS transistor M3And a fourth NMOS transistor M4Are connected together via a third inductance L3Is connected to the first PMOS transistor Mp1And the first NMOS transistor Mn1Drain of, a fifth NMOS transistor M5And a sixth NMOS transistor M6Are connected together via a fourth inductance L4Is connected to a second PMOS transistor Mp2And the second NMOS transistor Mn2Drain of, third NMOS transistor M3And a drain ofFive NMOS transistors M5Is connected with the intermediate frequency voltage anode IF +, and a fourth NMOS transistor M4And a sixth NMOS transistor M6The drain electrodes are connected together and connected with a cathode IF of the intermediate-frequency voltage; third NMOS transistor M3Grid connected to the positive pole V of local oscillator voltageLO+Fourth NMOS transistor M4Grid connected to local oscillator voltage cathode VLO-, fifth NMOS transistor M5Grid connected to local oscillator voltage cathode VLO-, sixth NMOS transistor M6Grid connected to the positive pole V of local oscillator voltageLO+(ii) a The switch mixing stage is controlled by a local oscillator signal, periodically commutates the current signal, converts the frequency from radio frequency to intermediate frequency, and completes frequency down-conversion.
Further, the output load stage comprises a first resistor R1A second resistor R2And a ninth capacitor C9(ii) a Wherein the first resistor R1First termination power supply VDDThe second end is connected with the intermediate frequency voltage anode IF +, and the second resistor R2First termination power supply VDDThe second end is connected with the cathode IF of the intermediate frequency voltage, and a ninth capacitor C9The first end of the output load stage is connected with the intermediate frequency voltage anode IF +, the second end of the output load stage is connected with the intermediate frequency voltage cathode IF-, and the output load stage is used for converting the intermediate frequency current signal into an intermediate frequency voltage signal.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. by stacking and connecting the NMOS transistor and the PMOS transistor in the capacitive cross-coupling circuit unit, transconductance is enhanced, parasitic effects are reduced, excessive noise factors are half of those of a traditional common-gate topology, a transconductance input stage can have lower noise output, and the power consumption of the whole circuit is reduced due to the stacked and connected NMOS transistor and PMOS transistor.
2. The inductor in the transconductance input stage is used for absorbing the parasitic effect at the input port, so that the circuit has good broadband performance; and the inductor is stacked and connected with the drains of the NMOS transistor and the PMOS transistor to form a broadband pi-type matching network, so that the conversion gain of the mixer is flattened, and the indirect noise output of the mixer is reduced by resonance with parasitic effect.
3. The capacitor neutralization technology compensates the reduction of the isolation degree through the Miller effect, and enhances the loop gain of the transconductance stage, thereby improving the linearity of the mixer.
Drawings
Fig. 1 is a circuit diagram of a conventional current injection type active mixer.
Fig. 2 is a circuit diagram of a conventional low noise mixer.
Fig. 3 is a circuit diagram of a CMOS capacitor neutralizing active mixer of the present invention.
Fig. 4 is an equivalent model diagram of the capacitive neutralization of the CMOS capacitive-neutralized active mixer of the present invention.
Fig. 5 is a simplified half mixer model diagram for bandwidth analysis of a CMOS capacitive-and-active mixer of the present invention.
FIG. 6 is a graph of the input reflection coefficient of the CMOS capacitor and active mixer of the present invention.
Fig. 7 is a graph of conversion gain and noise factor for a CMOS capacitive and active mixer of the present invention.
Fig. 8 is a graph of the linearity of the CMOS capacitor and active mixer of the present invention.
Fig. 9 is a graph of port isolation in a CMOS capacitor and active mixer of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.
Fig. 3 is a circuit diagram of a CMOS capacitor neutralizing active mixer according to the present invention, and the technical solution of the present invention is: a CMOS capacitance-neutralized active mixer, comprising: a transconductance input stage, a switching mixer stage and an output load stage. The transconductance input stage receives a radio-frequency voltage signal and converts the radio-frequency voltage signal into a current signal; the switch mixing stage is controlled by a local oscillator signal, periodically commutates the current signal, converts the frequency from radio frequency to intermediate frequency, and completes frequency down-conversion. The commutating IF current signal is then converted to an IF voltage at the output load stage. Wherein the transconductance input stage comprises a first PMOS transistor Mp1A second PMOS transistor Mp2And a first NMOS transistor Mn1A second NMOS transistor Mn2The transconductance input stage is connected with the second neutralizing capacitor Cntr2Negative electrode connected with radio frequency voltage-VinThrough a first neutralization capacitor Cntr1Positive electrode + V connected with radio frequency voltagein(ii) a The switching mixer stage comprises a third NMOS transistor M3A fourth NMOS transistor M4The fifth NMOS transistor M5And a sixth NMOS transistor M6The switching mixing stage passes through a third inductor L3And a fourth inductance L4Is connected with the transconductance input stage; the output load stage comprises a first resistor R1A second resistor R2And a ninth capacitor C9. Particularly, the capacitor neutralization technology is applied to the transconductance input stage to improve the isolation degree and the linearity of the mixer, and the power consumption of the transconductor is greatly saved due to the structure that the NMOS transistor and the PMOS transistor are connected in a stacked mode. In addition, passive matching networks are used to improve bandwidth and gain flatness.
Transconductance input stage total effective transconductance GmeffCan be written as
Figure GDA0002250121950000041
Parameter gm1And Cgs1Are respectively a transistor Mn1And Mp1The composite transconductance and parasitics of (a). In general we have Cc>>Cgs1(note: capacitance value C)c＝Ccn1+Ccp1，Cgs1＝Cgsn1+Cgsp1) Then the signal source impedance R needs to be maintaineds＝1/2gm1To ensure that the inputs match. Assuming further that the switching pair of the mixer is ideal, the conversion gain can be expressed as:
Figure GDA0002250121950000042
the coefficient 2/pi is a frequency conversion factor, and g is increasedm1Better gain performance, resistance R can be obtainedL＝R1＝R2. Under certain current constraints, i.e., the current magnitude through NMOS and PMOS transistors is uniform, we design a stacked NMOS/PMOS structure for transconductance to provide enhanced transconductance with less parasitic effects.
Performing small-signal analysis on the noise source in the transconductance input stage by a linear superposition method to obtain the following noise index
Figure GDA0002250121950000051
Where the parameter gamma represents the noise factor of the device and the device alpha of the saturation region ≈ 1. Reuse of Cc>>Cgs1The excess noise factor as the second term of (3) is half of that of the conventional common-gate topology, and the transconductance input stage can have a lower noise output.
Neutralization capacitance C between input and output of transconductance input stagentr(CntrComprising Cntr1And Cntr2) Has a dual effect on the circuit. As in FIG. 4, the triangle with-1 in the figure indicates a gain of-1, first cross-coupled Cntr1The resulting capacitive neutralization can compensate for the reduction in isolation by the miller effect. Miller capacitor C of transconductance input stageds1Connected between input and output, and can be equivalent to directly grounded input and output capacitors, and a capacitor C is further addedntrTo compensate for Cds1And (4) effect. Input and output equivalent capacitive reactance Cin,ds1And Cout,ds1As shown below
sCin,ds1＝sCds1(1-Av)+sCntr(1+Av)≈0 (4)
Figure GDA0002250121950000052
Figure GDA0002250121950000053
WhereingmswIs the transconductance of a switching mixer stage, AνFor conversion gain of the mixer, a is used in (4) and (5)ν>1, is determined. If we have Cntr＝Cds1The miller effect on the input port can be avoided and then the isolation will be improved.
Secondly, the capacitance CntrThe feedback effect can improve the loop gain of the transconductance input stage, thereby improving the linearity. Since the distortion of the active mixer comes mainly from the transconductance input stage, we neglect the distortion of the switching mixer stage for simplicity. The input third-order intermodulation point (IIP3) of the proposed transconductance input stage is:
Figure GDA0002250121950000054
wherein ZLTo output the impedance of the load stage, it can be seen that the transconductance input stage based on the capacitive neutralization technique increases its loop gain by (1+2 sC) compared to the conventional capacitive cross-coupled transconductance input stagentrZL)/(1+sCntrZL) Therefore, the IIP3 can be greatly improved.
Fig. 5 shows a simplified half mixer model for bandwidth analysis. The 3dB bandwidth of the mixer is in principle equal to Cgs1，Cp2And Cp3The three poles that are created are related. The total time constant of the mixer is
Figure GDA0002250121950000061
Wherein C isp2Is V in FIG. 5XParasitic capacitance at the node, Cp3Is a parasitic capacitance of the switching mixer stage, ro1And RswAre respectively an input transistor Mn1/Mp1And the source resistance of the switch pair, and Cgs1Is equal to Cgsn1+Cgsp1. Capacitive neutralization only compensates for Cds1Isolation degradation of effects, but for Cgs1And (4) invalidation. Therefore, in order to have good inputMatching, the inductor L must be useds(including L)spAnd Lsn) To absorb the parasitic effects at the input port and resonate at the center frequency of 6 GHz. Since the load of the input network Q factor is equal to Rs/sLsAnd therefore the value is low, which gives the circuit good broadband characteristics. In addition, the inductance L3And an inductance L4Inserted in a circuit to form a broadband pi-type matching network, then CP2And CP3Large resonances occur which flatten the conversion gain of the mixer and resonances with these parasitic effects also contribute to the reduction of the indirect noise output of the mixer.
The invention adopts 28nm CMOS process for design, uses SpectreRF software for simulation, the input reflection coefficient of the mixer is shown in figure 6, and the post-simulation input reflection coefficient S11 is observed in the frequency range of 2-9.6GHz<10dB, the frequency deviation of the front and back simulations can be attributed to increased parasitics after layout extraction. Similarly, the gain CG and noise performance NF of the mixer have been pre-and post-simulated, the proposed mixer is driven by a-1 dBm sinusoidal local oscillator power, and FIG. 7 shows the variation of the analog voltage conversion gain of the proposed mixer with respect to the input RF frequency when the IF frequency is fixed around 100MHz, the mixer having a flat gain curve of 11.5dB over a wider frequency range. Using the same intermediate frequency, the variation of the noise figure with respect to the radio frequency is also shown in fig. 7, the analog rear Double Sideband (DSB) noise figure NF varies from 3.9dB to 4.7dB over the passband, the mixer achieving an excellent low noise figure. Simulations of the mixer using capacitive neutralization showed excellent linearity and port isolation, as shown in FIG. 8, two-tone testing with 10MHz tone spacing over a 3dB bandwidth showed IIP3 varying in the range of 3.7-6.3 dBm, whereas if neutralized CntrThe connection is broken (i.e. w/oC in FIG. 8)ntrCurve), the IIP3 drops to around 0 dBm. Fig. 9 shows a graph of the port isolation of the mixer, with an average isolation of RF-IF (radio frequency-intermediate frequency) up to 52.5dB and a minimum isolation of LO-IF (local oscillator-intermediate frequency) exceeding 30 dB. Likewise, when CntrWhen the connection is broken (i.e. w/oC in FIG. 9)ntrCurve), bandwidthThe RF-IF isolation in is reduced by about 10 dB.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims (3)

1. A CMOS capacitance neutralization active frequency mixer comprises a transconductance input stage, a switch mixing stage and an output load stage, wherein the transconductance input stage receives a radio frequency voltage signal, converts the radio frequency voltage signal into a radio frequency current signal, then inputs the radio frequency current signal into the switch mixing stage, the switch mixing stage periodically commutates the current signal to convert the frequency of the current signal from the radio frequency to the intermediate frequency, and then transmits the intermediate frequency current signal to the output load stage, and the output load stage converts the intermediate frequency current signal into the intermediate frequency voltage signal for output;
the two capacitor cross-coupling circuit units are connected in a stacking mode through NMOS transistors and PMOS transistors in the units;
the transconductance input stage comprises a first PMOS transistor (M)p1) A second PMOS transistor (M)p2) And a first NMOS transistor (M)n1) A second NMOS transistor (M)n2) (ii) a Wherein the first PMOS transistor (M)p1) And the first NMOS transistor (M)n1) Is connected via a second neutralization capacitor (C)ntr2) Negative electrode (-V) connected with radio frequency voltagein) Second PMOS transistor (M)p2) And a second NMOS transistor (M)n2) Is connected via a first neutralizing capacitor (C)ntr1) Positive electrode (+ V) connected with radio frequency voltagein) A first PMOS transistor (M)p1) Is connected to the gate via a first capacitor (C)cp1) Is connected to a second PMOS transistor (M)p2) A second PMOS transistor (M)p2) Through a second capacitor (C)cp2) Is connected to the first PMOS transistor (M)p1) Source stage of (1), first NMOS transistor (M)n1) Through a fourth capacitor (C)cn2) Is connected to the second NMOS transistor (M)n2) Source stage of (1), second NMOS transistor (M)n2) Through a third capacitor (C)cn1) Is connected to the first NMOS transistor (M)n1) A source stage of (a); a first capacitor (C)cp1) Second terminal of (L) is connected to the first inductor (L)sp) A second terminal of (C), a second capacitance (C)cp2) First terminal of (L) is connected to the first inductor (L)sp) First terminal of (C), third capacitor (C)cn1) First terminal of (L) is connected to the second inductor (L)sn) First terminal of (1), fourth capacitance (C)cn2) Second terminal of (L) is connected to the second inductor (L)sn) A second end of (a); first PMOS transistor (M)p1) And a second PMOS transistor (M)p2) Respectively connected with a first inductor (L)sp) First and second terminals of a first NMOS transistor (M)n1) And a second NMOS transistor (M)n2) Respectively connected with a second inductor (L)sn) First and second terminals, a first inductance (L)sp) The first terminal passes through a fifth capacitor (C)5) Connected to the positive pole (+ V) of the radio-frequency voltagein) Second inductance (L)sn) Through a sixth capacitor (C)6) Connected to the positive pole (+ V) of the radio-frequency voltagein) First inductance (L)sp) The second terminal passes through a seventh capacitor (C)7) Connected to the negative (-V) of the radio-frequency voltagein) Second inductance (L)sn) Through an eighth capacitor (C)8) Connected to the negative (-V) of the radio-frequency voltagein) First inductance (L)sp) Third terminal power supply (V)DD) Second inductance (L)sn) The transconductance input stage is used for receiving a radio frequency voltage signal and converting the radio frequency voltage signal into a radio frequency current signal, so that the circuit noise is reduced.
2. A CMOS capacitance-neutralized active mixer according to claim 1, characterized in that the switching mixing stage comprises a third NMOS transistor (M)3) And a fourth NMOS transistor (M)4) And a fifth NMOS transistor (M)5) And a sixth NMOS transistor (M)6) (ii) a Wherein the third NMOS transistor (M)3) And a fourth NMOS transistor (M)4) Are connected together via a third inductance (L)3) Is connected to the first PMOS transistor (M)p1) And the first NMOS transistor (M)n1) Drain of (d), fifth NMOS transistor (M)5) And a sixth NMOS transistor (M)6) Are connected together via a fourth inductance (L)4) Is connected to a second PMOS transistor (M)p2) And a second NMOS transistor (M)n2) Drain of (d), third NMOS transistor (M)3) And a fifth NMOS transistor (M)5) Is connected to the intermediate frequency voltage anode (IF +), a fourth NMOS transistor (M)4) And a sixth NMOS transistor (M)6) The drain electrodes are connected together and connected with a cathode (IF-) of the intermediate frequency voltage; third NMOS transistor (M)3) Grid of the grid is connected with the positive pole (V) of the local oscillator voltageLO+) Fourth NMOS transistor (M)4) Grid connected to the negative of local oscillator voltage (V)LO-) Fifth NMOS transistor (M)5) Grid connected to the negative of local oscillator voltage (V)LO-) Sixth NMOS transistor (M)6) Grid of the grid is connected with the positive pole (V) of the local oscillator voltageLO+) (ii) a The switch mixing stage is controlled by a local oscillator signal, periodically commutates the current signal, converts the frequency from radio frequency to intermediate frequency, and completes frequency down-conversion.
3. A CMOS capacitance-neutralized active mixer according to claim 1, characterized in that the output load stage comprises a first resistor (R;)1) A second resistor (R)2) And a ninth capacitance (C)9) (ii) a Wherein the first resistor (R)1) First termination power supply (V)DD) The second end is connected with an intermediate frequency voltage anode (IF +), and a second resistor (R)2) First termination power supply (V)DD) The second end is connected with the cathode of the intermediate frequency voltage (IF-), and a ninth capacitor (C)9) Is connected to the intermediate frequency voltage positive pole (IF +), and is connected to the intermediate frequency voltage negative pole (IF-), and the output load stage is used to convert the intermediate frequency current signal into the intermediate frequency voltage signal.
CN201910304159.5A 2019-04-16 2019-04-16 CMOS capacitor neutralization active mixer Active CN110336538B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910304159.5A CN110336538B (en) 2019-04-16 2019-04-16 CMOS capacitor neutralization active mixer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910304159.5A CN110336538B (en) 2019-04-16 2019-04-16 CMOS capacitor neutralization active mixer

Publications (2)

Publication Number Publication Date
CN110336538A CN110336538A (en) 2019-10-15
CN110336538B true CN110336538B (en) 2021-02-02

Family

ID=68139928

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910304159.5A Active CN110336538B (en) 2019-04-16 2019-04-16 CMOS capacitor neutralization active mixer

Country Status (1)

Country Link
CN (1) CN110336538B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111865221A (en) * 2020-08-18 2020-10-30 成都信息工程大学 Silicon-based millimeter wave receiving front-end circuit
CN114826162B (en) * 2022-05-18 2023-11-10 成都通量科技有限公司 5G millimeter wave dual-band dual-mode mixer and wireless communication terminal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107196607A (en) * 2017-04-28 2017-09-22 天津大学 A kind of down-conversion mixer
CN109347444A (en) * 2018-09-15 2019-02-15 天津大学 A kind of up-conversion mixer of low noise high-conversion-gain
CN109379047A (en) * 2018-09-11 2019-02-22 天津大学 A kind of no on-chip inductor low-power consumption high linearity double balanced mixer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347780B (en) * 2011-08-19 2014-10-15 中国科学技术大学 Radio frequency receiving front-end circuit with adjustable gain
CN103259553A (en) * 2012-02-17 2013-08-21 Imec公司 A front-end system for radio devices
CN106385240B (en) * 2016-11-30 2018-09-21 东南大学 A kind of RF front-end circuit that gain is continuously adjustable
CN107645300B (en) * 2017-10-16 2020-04-10 中国科学院上海高等研究院 Current multiplexing low-power consumption radio frequency receiver

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107196607A (en) * 2017-04-28 2017-09-22 天津大学 A kind of down-conversion mixer
CN109379047A (en) * 2018-09-11 2019-02-22 天津大学 A kind of no on-chip inductor low-power consumption high linearity double balanced mixer
CN109347444A (en) * 2018-09-15 2019-02-15 天津大学 A kind of up-conversion mixer of low noise high-conversion-gain

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CMOS有源混频器噪声及射频接收前端关键技术研究;郭本青;《中国博士学位论文全文数据库 信息科技辑》;20121215;第I135-65页 *
Inductorless linearization of low-power active mixers;Li Xu 等;《2015 IEEE International Symposium on Circuits and Systems》;20150730;第2213-2216页 *

Also Published As

Publication number Publication date
CN110336538A (en) 2019-10-15

Similar Documents

Publication Publication Date Title
CN110138351B (en) CMOS broadband balun radio frequency receiving front-end circuit
Zijie et al. A 1-to 10-GHz RF and Wideband IF Cross-Coupled Gilbert Mixer in 0.13-$\mu\hbox {m} $ CMOS
CN109714005B (en) Reconfigurable dual-band mixer
CN102075145A (en) High-linearity folding image mixer
CN110336538B (en) CMOS capacitor neutralization active mixer
CN111865221A (en) Silicon-based millimeter wave receiving front-end circuit
WO2024125234A1 (en) Low-noise amplifier and radio frequency receiving module
CN102868377A (en) Total 3G (Third Generation Telecommunication) CMOS (Complementary Metal-Oxide-Semiconductor Transistor) differential low-noise amplifier based on controllable active inductor
WO2019233217A1 (en) Reconfigurable, low-power consumption and low-cost receiver front-end supporting multi-band and multi-mode
CN104124923B (en) A kind of low-noise mixer circuit
Guo et al. A CMOS low-noise active mixer with enhanced linearity and isolation by exploiting capacitive neutralization technique
CN109309480B (en) Low-noise switch transconductance mixer
US10097223B2 (en) Low power supply voltage double-conversion radio frequency receiving front end
Lin et al. A 60 GHz Sub-Harmonic Resistive FET Mixer Using 0.13$\mu {\rm m} $ CMOS Technology
CN109004905B (en) Up-conversion mixer with balun
CN101662261B (en) High-linearity folding mixer
CN114785295B (en) Ultra-wideband power amplifier and phased array transmitter
CN106603013B (en) Mixer circuit with complementary CMOS structure
WO2020000614A1 (en) Frequency mixer circuit
Guo et al. A 1–3 GHz CMOS mixer-first receiver frontend with dual-feedback OTA achieving 306 MHz IF bandwidth, 2.1 dB NF, and 33 dB gain
CN104935260A (en) High-gain low-noise frequency mixer
CN101447793A (en) Frequency mixer and direct down-conversion receiver
US7049878B2 (en) Down-converter using an on-chip bias circuit for enhancing symmetry and linearity and testing device thereof
Tseng et al. A 0.9-GHz fully integrated 45% PAE class-Ε power amplifier fabricated using a 0.18-μm CMOS process for LoRa applications
Mustaffa et al. A reconfigurable LNA for multi-standard receiver using 0.18 μm CMOS technology

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant