CN110335815A - The preparation method and flexible chip of flexible chip - Google Patents
The preparation method and flexible chip of flexible chip Download PDFInfo
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- CN110335815A CN110335815A CN201910523339.2A CN201910523339A CN110335815A CN 110335815 A CN110335815 A CN 110335815A CN 201910523339 A CN201910523339 A CN 201910523339A CN 110335815 A CN110335815 A CN 110335815A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 claims abstract description 185
- 229920006254 polymer film Polymers 0.000 claims abstract description 61
- 230000001360 synchronised effect Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 47
- 238000005538 encapsulation Methods 0.000 claims description 33
- 239000003292 glue Substances 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 claims description 25
- 230000009467 reduction Effects 0.000 claims description 13
- 239000004642 Polyimide Substances 0.000 claims description 5
- -1 benzocyclobutane alkenes Chemical class 0.000 claims description 5
- 238000007731 hot pressing Methods 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 238000000197 pyrolysis Methods 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 230000008569 process Effects 0.000 description 24
- 238000005452 bending Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000000227 grinding Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000000047 product Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 239000004033 plastic Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000005022 packaging material Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 229920002521 macromolecule Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920000344 molecularly imprinted polymer Polymers 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The preparation method of the flexible chip of the application, comprising: provide fan-out-type wafer-level packaging part, fan-out-type wafer-level packaging part includes rerouting layer, encapsulated layer and positioned at the multiple chips rerouted between layer and encapsulated layer；The encapsulated layer side of fan-out-type wafer-level packaging part is carried out thinned, multiple chips is made to be synchronized to be thinned with encapsulated layer；The encapsulated layer side of fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains flexible fan-out-type wafer-level packaging part；Flexible fan-out-type wafer-level packaging part is cut, multiple flexible chips are obtained.The application can be realized the flexible package of ultra-thin chip.
Description
Technical field
This application involves chip technology fields, and in particular to a kind of preparation method and flexible chip of flexible chip.
Background technique
The fast-developing electron end product of Flexible Displays and flexible circuit plate technique brings revolutionary variation, makes
The electronic product for obtaining wearable device and electric terminal field shows more and more plastic deformation abilities.
It has been recognised by the inventors that although display screen and circuit board in electronic product have been carried out partially flexible, due to electricity
Chip employed in sub- product and its encapsulation are the rigid devices that cannot be deformed, and this strongly limits the whole of electronic product
Body flexibility deformability.Therefore, the flexibility of chip and its encapsulation is the key that electronic product overall flexibility.
Flexible chip, which refers to, to be become by the way that Silicon Wafer is thinned to certain thickness hereinafter, enabling wafer that bending appropriate occurs
Shape, the ability that equally there is the ultra-thin chip as made of the wafer cutting flexible bending to deform.Flexible chip does not require nothing more than encapsulation
Body can play the role of protection to chip and connect with electrical property, but also require packaging body equally and have with it is soft similar in chip
Property deformability.
However, conventional encapsulation, which does not require nothing more than packed chip, to be had certain rigidity, cannot occur bending and deformation, also want
Seeking packaging body cannot deform to avoid intracorporal rigid chips damage is encapsulated.Therefore, conventional encapsulation design and encapsulation work
Skill is difficult to meet the preparation demand of flexible chip.
Summary of the invention
In view of the above technical problems, the application provides a kind of preparation method of flexible chip, by having completed to encapsulate
Fan-out package part carry out thinned and encapsulate again so that chip and original encapsulated layer obtain synchronous flexibility and are thinned, and
So that chip is in the entirely protection in encapsulation process all by untouched dress again, to realize the flexibility after chip package and reduce not
Yield.
In order to solve the above technical problems, a kind of preparation method of flexible chip provided by the present application, comprising:
A. provide fan-out-type wafer-level packaging part, the fan-out-type wafer-level packaging part include reroute layer, encapsulated layer and
Multiple chips between the rewiring layer and the encapsulated layer；
B. the encapsulated layer side of the fan-out-type wafer-level packaging part is carried out thinned, makes the multiple chip and the envelope
Dress layer is synchronized to be thinned；
C. the encapsulated layer side of the fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains flexible fan
Type wafer-level packaging part out；
D. the flexible fan-out-type wafer-level packaging part is cut, multiple flexible chips are obtained.
Wherein, step b includes:
Mechanical reduction is carried out to the encapsulated layer side of the fan-out-type wafer-level packaging part, make the multiple chip with it is described
Encapsulated layer is synchronized to be thinned；
The encapsulated layer side of the fan-out-type wafer-level packaging part is thinned again, makes the multiple chip and the envelope
Dress layer is synchronized to be thinned.
Wherein, step b includes:
The rewiring layer side of the fan-out-type wafer-level packaging part is attached on the first rigid support plate；
From the encapsulated layer side of the fan-out-type wafer-level packaging part towards the direction of the described first rigid support plate, to described
Fan-out-type wafer-level packaging part carries out thinned, and the multiple chip is made to be synchronized to be thinned with the encapsulated layer.
Wherein, the step d when the rewiring layer side of the fan-out-type wafer-level packaging part includes solder bump, comprising:
Scribing is carried out to the flexible fan-out-type wafer-level packaging part, includes at least one chip in each scribe region；
The rewiring layer side of flexible fan-out-type wafer-level packaging part after scribing is separated with the described first rigid support plate,
Obtain multiple flexible chips.
Wherein, when the rewiring layer side of the fan-out-type wafer-level packaging part do not include solder bump when, step d it
Before, further includes:
The polymer film layer side of the flexible fan-out-type wafer-level packaging part is attached on the second rigid support plate；
The rewiring layer side of the flexible fan-out-type wafer-level packaging part is separated with the described first rigid support plate；
Solder bump is formed on the rewiring layer of the flexible fan-out-type wafer-level packaging part.
Wherein, step d, comprising:
Scribing is carried out to the flexible fan-out-type wafer-level packaging part after formation solder bump, includes extremely in each scribe region
A few chip；
By the polymer film layer side of the flexible fan-out-type wafer-level packaging part after scribing and the second rigid support plate
Separation, obtains multiple flexible chips.
Wherein, the rewiring layer side of the fan-out-type wafer-level packaging part is attached to described on first rigid support plate
The step of in, and, be attached to second in the polymer film layer side by the flexible fan-out-type wafer-level packaging part
In step on rigid support plate, realize that attachings connects using bonding glue, the bonding glue be the bonding of UV solution, be pyrolyzed be bonded or
The bonding glue of laser solution bonding.
Wherein, in step c, the polymer film layer is formed by spin coating, spraying or hot pressing.
Wherein, the polymer film layer is epoxy resin, polyimide or benzocyclobutane alkenes high molecular polymerization
Object.
Wherein, mechanical reduction is carried out to the encapsulated layer side of the fan-out-type wafer-level packaging part, makes the multiple chip
With the encapsulated layer be synchronized to be thinned to a thickness of 25 μm~35 μm, the polymer film layer with a thickness of 20 μm~50 μ
m。
The application also provides a kind of flexible chip, and the flexible chip uses the preparation method of flexible chip as described above
It is prepared.
The preparation method of the flexible chip of the application provides fan-out-type wafer-level packaging part, fan-out-type wafer-level packaging part
Including rerouting layer, encapsulated layer and positioned at the multiple chips rerouted between layer and encapsulated layer, to fan-out-type wafer-level packaging part
Encapsulated layer side carry out thinned, make multiple chips be synchronized to be thinned with encapsulated layer, the fan-out-type wafer-level packaging after being thinned
The encapsulated layer side of part forms polymer film layer, obtains flexible fan-out-type wafer-level packaging part, cuts flexible fan-out-type wafer
Grade packaging part, obtains multiple flexible chips.In this way, the present invention is in fan-out-type wafer-level packaging (Fan-out wafer
Level package, FOWLP) on the basis of, the new method of a kind of chip and the common flexibility of encapsulation is proposed, by
The fan-out package part for completing encapsulation is carried out thinned and is encapsulated again, so that chip obtains synchronous flexibility with original encapsulated layer
It is thinned, and makes chip in the entirely protection in encapsulation process all by untouched dress again, to realize the flexibility after chip package
And reduce fraction defective.
Detailed description of the invention
Fig. 1 is the flow diagram according to the preparation method of the flexible chip shown in the application first embodiment；
Fig. 2 is the process schematic representation according to the preparation method of the flexible chip shown in the application first embodiment；
Fig. 3 is the flow diagram according to the preparation method of the flexible chip shown in the application second embodiment；
Fig. 4 is the process schematic representation according to the preparation method of the flexible chip shown in the application second embodiment；
Fig. 5 is the flow diagram according to the preparation method of the flexible chip shown in the application 3rd embodiment；
Fig. 6 is the process schematic representation according to the preparation method of the flexible chip shown in the application 3rd embodiment.
Specific embodiment
Presently filed embodiment is illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the application easily.
In described below, with reference to attached drawing, attached drawing describes several embodiments of the application.It should be appreciated that also can be used
Other embodiments, and can be carried out without departing substantially from spirit and scope mechanical composition, structure, electrically with
And operational change.Following detailed description should not be considered limiting, and the range of embodiments herein
Only limited by the claims for the patent announced.Term used herein is merely to describe specific embodiment, and be not
It is intended to limit the application.
Although term first, second etc. are used to describe various elements herein in some instances, these elements
It should not be limited by these terms.These terms are only used to distinguish an element with another element.
Furthermore as used in herein, singular " one ", "one" and "the" are intended to also include plural number shape
Formula, unless there is opposite instruction in context.It will be further understood that term "comprising", " comprising " show that there are the spies
Sign, step, operation, element, component, project, type, and/or group, but it is not excluded for one or more other features, step, behaviour
Presence, appearance or the addition of work, element, component, project, type, and/or group.Term "or" used herein and "and/or" quilt
It is construed to inclusive, or means any one or any combination.Therefore, " A, B or C " or " A, B and/or C " mean " with
Descend any one: A；B；C；A and B；A and C；B and C；A, B and C ".Only when element, function, step or the combination of operation are in certain sides
When inherently mutually exclusive under formula, it just will appear the exception of this definition.
First embodiment
Fig. 1 is the flow diagram according to the preparation method of the flexible chip shown in the application first embodiment.Such as Fig. 1 institute
Show, a kind of preparation method of flexible chip, comprising:
Step 110, fan-out-type wafer-level packaging part is provided, fan-out-type wafer-level packaging part includes rerouting layer, encapsulated layer
And positioned at the multiple chips rerouted between layer and encapsulated layer.
Incorporated by reference to Fig. 2 (a), fan-out-type wafer-level packaging part includes rerouting layer 21, encapsulated layer 22 and being located to reroute layer
Multiple chips 23 between 21 and encapsulated layer 22, wherein chip 23 includes silicon base layer and the circuit layer for being located at silicon base layer side,
Referred to as bare chip is a kind of product form manufactured before completing and being unencapsulated in semiconductor components and devices.
Fan-out-type wafer-level packaging part includes two kinds of forms, and bare chip is specially reconstructed into wafer shape (wafer
Level packaging) or plate (panel level packaging) fan-out package.Current fan-out-type wafer scale
Packaging part is rigid encapsulation, for encapsulating the encapsulated layer 22 of chip 23 using plastic packaging material, such as epoxy-plastic packaging material (Epoxy
Molding Compound, EMC), after encapsulation, formed in the circuit layer side rewiring that wafer-level packaging part corresponds to bare chip
Layer (RDL) 21 is rerouted, metallization process manufacture I/O interface is provided, in general, can also further be formed on rerouting layer 21
Solder bump, solder bump can play the role of mechanically interconnected, electrical interconnection, heat interconnection between chip 23 and circuit board.
In the prior art, after the completion of prepared by fan-out-type wafer-level packaging part, directly further by fan-out-type wafer scale
Packaging part is cut into multiple units, so that multiple chips are obtained, since the thickness of the bare chip included is larger and uses rigidity
Plastic packaging material is packaged, so that the chip that encapsulation obtains is unable to satisfy the demand of Flexible Displays and flexible circuit plate technique.
Step 120, the encapsulated layer side of fan-out-type wafer-level packaging part is carried out thinned, makes multiple chips and encapsulated layer quilt
It synchronizes thinned.
Incorporated by reference to Fig. 2 (b), 22 side of encapsulated layer of fan-out-type wafer-level packaging part does not have circuit structure, thinning process
Be for chip 23 silicon base layer and encapsulated layer 22 carry out it is thinned, be thinned after, chip 23 is equal with the thickness of encapsulated layer 22, core
One side surface of piece 23 and the flush of encapsulated layer 22 and the outside for being exposed to encapsulated layer 22.By to completed chip envelope
The fan-out package part of dress carries out thinned, and chip 23 and encapsulated layer 22 are thinned simultaneously, also, chip 23 is entirely being subtracted
Protection during thin all by encapsulated layer 22 avoids and packaging technologies operation, the drop such as is directly cut, picked up to bare chip
The damaged probability of low chip 23.
Wherein, thinned process is carried out to 22 side of encapsulated layer of fan-out-type wafer-level packaging part, may particularly include:
Mechanical reduction is carried out to the encapsulated layer side of fan-out-type wafer-level packaging part, is synchronized multiple chips with encapsulated layer
It is thinned；
The encapsulated layer side of fan-out-type wafer-level packaging part is thinned again, multiple chips is made to be synchronized to subtract with encapsulated layer
It is thin.Being thinned again can be carried out by way of dry plasma etch.
Firstly, using the machine of being thinned, by corase grinding and fine grinding technology process, by 23 He of chip of fan-out-type wafer-level packaging part
The thickness of encapsulated layer 22 be thinned to 50 μm hereinafter, be thinned after chip 23 and encapsulated layer 22 thickness it is smaller, flexibility bendable
The ability of song deformation is stronger.
After mechanical reduction, ICP (Inductive Coupled Plasma Emission can be passed through
Spectrometer, inductively coupled plasma spectrum generator) dry plasma etch is carried out, to the surface of silicon and encapsulated layer 22
Grinding residual stress layer be removed, the thickness of removal is about 1 μm~5 μm.Preferably, chip 23 and encapsulation in the present embodiment
Layer 22 be thinned after with a thickness of 25 μm~35 μm.It is appreciated that the purpose of carrying out the step of dry plasma etch is to remove
The residual stress generated during mechanical reduction, therefore, the step of dry plasma etch is optional step.
It wherein, can be first by fan-out-type crystalline substance when 22 side of encapsulated layer to fan-out-type wafer-level packaging part carries out thinned
21 side of rewiring layer of circle grade packaging part is attached on a rigid support plate, makes the encapsulated layer 22 1 of fan-out-type wafer-level packaging part
Side back is to the rigidity support plate, then, right from 22 side of encapsulated layer of fan-out-type wafer-level packaging part towards the direction of rigid support plate
Fan-out-type wafer-level packaging part carries out thinned, and multiple chips 23 is made to be synchronized to be thinned with encapsulated layer 22.In actual implementation, using facing
21 side of rewiring layer of fan-out-type wafer-level packaging part is attached on rigid support plate by Shi Jianhe glue, and bonding glue is that UV solves key
It closes, the bonding glue of pyrolysis bonding or the bonding of laser solution, so as to pass through the side such as UV radiation, heating, laser after completing technique
Formula changes the viscosity of bonding glue, discharges the rewiring layer 21 of fan-out-type wafer-level packaging part.
Step 130, the encapsulated layer side of the fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains
Flexible fan-out-type wafer-level packaging part.
Incorporated by reference to Fig. 2 (c), before forming polymer film layer 24, to the envelope of the fan-out-type wafer-level packaging part after being thinned
It fills 22 side of layer and carries out plasma cleaning, then, 22 side of encapsulated layer of the fan-out-type wafer-level packaging part after being thinned is formed
One layer of polymer film layer 24, so that the surface of chip 23 and encapsulated layer 22 after the covering of polymer film layer 24 is thinned, forms
Flexible package layer, to obtain flexible fan-out-type wafer-level packaging part, flexible fan-out-type wafer-level packaging part includes rerouting layer
21, chip 23 after being thinned, be thinned after encapsulated layer 22 and polymer film layer 24, flexible fan-out-type wafer-level packaging part refers to
Chip 23 after rerouting layer 21, being thinned, be thinned after encapsulated layer 22 and the structures such as polymer film layer 24 be provided with flexible change
The ability of shape.In the application, the effect of polymer film layer 24 is that chip 23 is sealed and is protected, and can both stop moisture
The interface between chip 23 and encapsulated layer 22 is invaded, generation tensile stress between chip 23 and encapsulated layer 22 is also inhibited to split in bending
Line, while protecting chip 23 not because external force is damaged.
Type used by polymer film layer 24 is including but not limited to following several: epoxy resin, PI polyimides
The high Molecularly Imprinted Polymers such as class, BCB benzocyclobutane alkenes, macromolecule membrane packaging method can be the side such as spin coating, spraying, hot pressing
Method, to form polymer film layer 24 by above-mentioned material and technique.
In the present embodiment, preferably 20 μm~50 μm of the thickness of polymer film layer 24, polymer film layer 24 is thinner,
More be conducive to the flexible bending deformation of packaging body.But thinner film layer inhibits to the intrusion of moisture and the suppression of bending tensile stress
Make weaker, therefore, when preparation comprehensively considers the thickness of selection polymer film layer 24.
Step 140, flexible fan-out-type wafer-level packaging part is cut, multiple flexible chips are obtained.
Incorporated by reference to Fig. 2 (d), by laser or saw blade, scribing is carried out to flexible fan-out-type wafer-level packaging part, scribing
Depth is greater than the thickness of flexible fan-out-type wafer-level packaging part, and each individual packaging body after having cut may include 1
Chip 23 or the chipset being made of multiple chips 23.
By above-mentioned process flow steps, the chip 23 of obtained ultrathin and its encapsulation all have flexible, flexible
The ability of deformation is able to bear the bending of specific degrees.When flexible chip patch is assembled on circuit board flexible, Ke Yisui
Circuit board carries out flexible bending deformation together.Circuit board flexible refers to FPC (Flexible Printed Circuit, flexibility
Circuit board) or COF (Chip On Flex or Film, flip chip) circuit board.
In this way, the present invention is on the basis of fan-out-type wafer-level packaging, proposes a kind of chip and encapsulation is common
The new method of flexibility, by the way that the fan-out package part for having completed encapsulation is carried out thinned and is encapsulated again so that chip and
Original encapsulated layer obtains synchronous flexibility and is thinned, and makes chip in the entirely guarantor in encapsulation process all by untouched dress again
Shield, to realize the flexibility after chip package and reduce fraction defective.
Second embodiment
Fig. 3 is the flow diagram according to the preparation method of the flexible chip shown in the application second embodiment.Such as Fig. 3 institute
Show, when the rewiring layer side of fan-out-type wafer-level packaging part does not include solder bump, the system of the flexible chip of the present embodiment
Preparation Method the following steps are included:
Step 310, fan-out-type wafer-level packaging part is provided, fan-out-type wafer-level packaging part includes rerouting layer, encapsulated layer
And positioned at the multiple chips rerouted between layer and encapsulated layer.
The step 110 in first embodiment is please referred to, details are not described herein.
In the present embodiment, the fan-out-type wafer-level packaging part of solder bump is not included as former using rewiring layer side
Beginning material, namely using no fan-out-type wafer-level packaging part for cutting separation, planting ball without microbonding ball as original material.
Step 320, the rewiring layer side of fan-out-type wafer-level packaging part is attached on the first rigid support plate.
It will be first fanned out to before 22 side of encapsulated layer to fan-out-type wafer-level packaging part is thinned incorporated by reference to Fig. 4 (a)
21 side of rewiring layer of type wafer-level packaging part is attached on the first rigid support plate 50, makes the envelope of fan-out-type wafer-level packaging part
22 side of layer is filled backwards to the first rigid support plate 50,22 side of encapsulated layer of fan-out-type wafer-level packaging part does not have circuit structure,
In actual implementation, 21 side of rewiring layer of fan-out-type wafer-level packaging part is attached to the first rigid support plate using bonding glue 40
On 50, bonding glue 40 is the interim bonding glue of the bonding of UV solution, pyrolysis bonding or the bonding of laser solution, so as to complete technique
Afterwards, change the viscosity of bonding glue 40 by modes such as UV radiation, heating, laser, discharge the heavy cloth of fan-out-type wafer-level packaging part
Line layer 21.First rigid support plate 50 can be glass support plate, be also possible to metal support plate, in the present embodiment, UV is temporarily bonded
Glue and glass support plate are optimum combination.
Step 330, from the encapsulated layer side of fan-out-type wafer-level packaging part towards the direction of the first rigid support plate, to being fanned out to
Type wafer-level packaging part carries out thinned, and multiple chips is made to be synchronized to be thinned with encapsulated layer.
Incorporated by reference to Fig. 4 (b), thinning process be for chip 23 silicon base layer and encapsulated layer 22 carry out it is thinned, be thinned after,
Chip 23 is equal with the thickness of encapsulated layer 22, a side surface of chip 23 and the flush of encapsulated layer 22 and is exposed to encapsulated layer
22 outside.Thinned by carrying out to the fan-out package part for having completed the encapsulation of chip 23, chip 23 and encapsulated layer 22 obtain
It is thinned simultaneously, also, makes protection of the chip 23 in entire thinning process all by encapsulated layer 22, avoid directly to naked core
Piece such as is cut, is picked up at the packaging technologies operation, reduces the damaged probability of chip 23.
Wherein, thinned process is carried out to fan-out-type wafer-level packaging part, may particularly include:
Mechanical reduction is carried out to the encapsulated layer side of fan-out-type wafer-level packaging part, is synchronized multiple chips with encapsulated layer
It is thinned；
The encapsulated layer side of fan-out-type wafer-level packaging part is thinned again, multiple chips is made to be synchronized to subtract with encapsulated layer
It is thin.Being thinned again can be carried out by way of dry plasma etch.
Firstly, using the machine of being thinned, by corase grinding and fine grinding technology process, by 23 He of chip of fan-out-type wafer-level packaging part
The thickness of encapsulated layer 22 be thinned to 50 μm hereinafter, be thinned after chip 23 and encapsulated layer 22 thickness it is smaller, flexibility bendable
The ability of song deformation is stronger.
After mechanical reduction, ICP (Inductive Coupled Plasma Emission can be passed through
Spectrometer, inductively coupled plasma spectrum generator) dry plasma etch is carried out, to the surface of silicon and encapsulated layer 22
Grinding residual stress layer be removed, the thickness of removal is about 1 μm~5 μm.Preferably, chip 23 and encapsulation in the present embodiment
Layer 22 be thinned after with a thickness of 25 μm~35 μm.It is appreciated that the purpose of carrying out the step of dry plasma etch is to remove
The residual stress generated during mechanical reduction, therefore, the step of dry plasma etch is optional step.
Step 340, the encapsulated layer side of the fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains
Flexible fan-out-type wafer-level packaging part.
Incorporated by reference to Fig. 4 (c), before forming polymer film layer 24, to the envelope of the fan-out-type wafer-level packaging part after being thinned
It fills 22 side of layer and carries out plasma cleaning, then, 22 side of encapsulated layer of the fan-out-type wafer-level packaging part after being thinned is formed
One layer of polymer film layer 24, so that the surface of chip 23 and encapsulated layer 22 after the covering of polymer film layer 24 is thinned, forms
Flexible package layer, to obtain flexible fan-out-type wafer-level packaging part, flexible fan-out-type wafer-level packaging part includes rerouting layer
21, chip 23 after being thinned, be thinned after encapsulated layer 22 and polymer film layer 24, flexible fan-out-type wafer-level packaging part refers to
Chip 23 after rerouting layer 21, being thinned, be thinned after encapsulated layer 22 and the structures such as polymer film layer 24 be provided with flexible change
The ability of shape.In the application, the effect of polymer film layer 24 is that chip 23 is sealed and is protected, and can both stop moisture
The interface between chip 23 and encapsulated layer 22 is invaded, generation tensile stress between chip 23 and encapsulated layer 22 is also inhibited to split in bending
Line, while protecting chip 23 not because external force is damaged.
Type used by polymer film layer 24 is including but not limited to following several: epoxy resin, PI polyimides
The high Molecularly Imprinted Polymers such as class, BCB benzocyclobutane alkenes, macromolecule membrane packaging method can be the side such as spin coating, spraying, hot pressing
Method, to form polymer film layer 24 by above-mentioned material and technique.
In the present embodiment, preferably 20 μm~50 μm of the thickness of polymer film layer 24, polymer film layer 24 is thinner,
More be conducive to the flexible bending deformation of packaging body.But thinner film layer inhibits to the intrusion of moisture and the suppression of bending tensile stress
Make weaker, therefore, when preparation comprehensively considers the thickness of selection polymer film layer 24.
Step 350, the polymer film layer side of flexible fan-out-type wafer-level packaging part is attached to the second rigid support plate
On.
Step 360, the rewiring layer side of flexible fan-out-type wafer-level packaging part is separated with the first rigid support plate.
Incorporated by reference to Fig. 4 (d) and Fig. 4 (e), after completing to be thinned and encapsulate, the subsequent manufacture craft for carrying out solder bump.?
Before making solder bump, 24 side of polymer film layer of flexible fan-out-type wafer-level packaging part is first attached to the second rigidity and is carried
On plate 70.In actual implementation, 24 side of polymer film layer of flexible fan-out-type wafer-level packaging part is pasted using bonding glue 40
It being attached on the second rigid support plate 70, bonding glue 40 is the interim bonding glue of the bonding of UV solution, pyrolysis bonding or the bonding of laser solution, thus
The viscosity of bonding glue 40 can be changed by modes such as UV radiation, heating, laser after completing technique, discharge flexible fan-out-type
The polymer film layer 24 of wafer-level packaging part, the second rigid support plate 70 can be glass support plate, be also possible to metal support plate,
In the present embodiment, UV is temporarily bonded glue and glass support plate is optimum combination.Then, by the weight of flexible fan-out-type wafer-level packaging part
21 side of wiring layer is separated with the first rigid support plate 50, makes 21 side of rewiring layer of flexible fan-out-type wafer-level packaging part backwards
Second rigid support plate 70.In actual implementation, the viscosity for changing UV and being temporarily bonded glue 40 is radiated by UV, and it is brilliant to discharge flexible fan-out-type
The rewiring layer 21 of circle grade packaging part, so as to reroute 21 side of layer formation solder bump.
Step 370, solder bump is formed on the rewiring layer of flexible fan-out-type wafer-level packaging part.
Incorporated by reference to Fig. 4 (f), when forming solder bump 211, by conventional solder electroplating bumps or ball technique is planted, in weight
Plant soldered ball is carried out on the pad of 21 side of wiring layer, details are not described herein.
Step 380, scribing, each scribe region are carried out to the flexible fan-out-type wafer-level packaging part after formation solder bump
Interior includes at least one chip.
Incorporated by reference to Fig. 4 (g), by laser or saw blade, scribing is carried out to flexible fan-out-type wafer-level packaging part, scribing
Depth is greater than the thickness of flexible fan-out-type wafer-level packaging part namely the depth of scribing reaches bonding glue 40, every after having cut
One individual packaging body may include 1 chip 23 or the chipset being made of multiple chips 23.
Step 390, by the polymer film layer side of the flexible fan-out-type wafer-level packaging part after scribing and the second rigidity
Support plate separation, obtains multiple flexible chips.
Incorporated by reference to Fig. 4 (h), after completing scribing, the viscosity for changing UV and being temporarily bonded glue 40 is radiated by UV, release is flexible
The polymer film layer 24 of fan-out-type wafer-level packaging part, obtains multiple flexible chips, and multiple flexible chip includes weight cloth
Line layer 21, chip 23, encapsulated layer 22, polymer film layer 24 and solder bump 211.
By above-mentioned process flow steps, the chip 23 of obtained ultrathin and its encapsulation all have flexible, flexible
The ability of deformation is able to bear the bending of specific degrees.When flexible chip patch is assembled on circuit board flexible, Ke Yisui
Circuit board carries out flexible bending deformation together.Circuit board flexible refers to FPC circuit board or COF circuit board.
In this way, the present invention is on the basis of fan-out-type wafer-level packaging, proposes a kind of chip and encapsulation is common
The new method of flexibility, by the way that the fan-out package part for having completed encapsulation is carried out thinned and is encapsulated again so that chip and
Original encapsulated layer obtains synchronous flexibility and is thinned, and makes chip in the entirely guarantor in encapsulation process all by untouched dress again
Shield, to realize the flexibility after chip package and reduce fraction defective.
3rd embodiment
Fig. 5 is the flow diagram according to the preparation method of the flexible chip shown in the application 3rd embodiment.Such as Fig. 5 institute
Show, when the rewiring layer side of fan-out-type wafer-level packaging part includes solder bump, the preparation of the flexible chip of the present embodiment
Method the following steps are included:
Step 510, fan-out-type wafer-level packaging part is provided, fan-out-type wafer-level packaging part includes rerouting layer, encapsulated layer
And positioned at the multiple chips rerouted between layer and encapsulated layer.
Incorporated by reference to Fig. 6 (a), fan-out-type wafer-level packaging part includes rerouting layer 21, encapsulated layer 22 and being located to reroute layer
Multiple chips 23 between 21 and encapsulated layer 22, wherein chip 23 includes silicon base layer and the circuit layer for being located at silicon base layer side,
Referred to as bare chip is a kind of product form manufactured before completing and being unencapsulated in semiconductor components and devices.
Fan-out-type wafer-level packaging part includes two kinds of forms, and bare chip is specially reconstructed into wafer shape (wafer
Level packaging) or plate (panel level packaging) fan-out package.Current fan-out-type wafer scale
Packaging part is rigid encapsulation, for encapsulating the encapsulated layer 22 of chip 23 using plastic packaging material, such as epoxy-plastic packaging material (Epoxy
Molding Compound, EMC), after encapsulation, the circuit layer side rewiring shape of bare chip 23 is corresponded in wafer-level packaging part
At reroute layer (RDL) 21, provide metallization process manufacture I/O interface, in general, can also further reroute layer 21 on shape
At solder bump, solder bump can play the role of mechanically interconnected, electrical interconnection, heat interconnection between chip 23 and circuit board.
In the present embodiment, it is sealed using rerouting the fan-out-type wafer scale that 21 side of layer includes solder bump (not shown go out)
Piece installing is as original material, namely using no cutting separation, microbonding ball plants the fan-out-type wafer-level packaging part of ball as former
Beginning material.
Step 520, the rewiring layer side of fan-out-type wafer-level packaging part is attached on the first rigid support plate.
It will be first fanned out to before 22 side of encapsulated layer to fan-out-type wafer-level packaging part is thinned incorporated by reference to Fig. 6 (b)
21 side of rewiring layer of type wafer-level packaging part is attached on the first rigid support plate 50, makes the envelope of fan-out-type wafer-level packaging part
22 side of layer is filled backwards to the first rigid support plate 50,22 side of encapsulated layer of fan-out-type wafer-level packaging part does not have circuit structure,
In actual implementation, 21 side of rewiring layer of fan-out-type wafer-level packaging part is attached to the first rigid support plate using bonding glue 40
On 50, bonding glue 40 is the interim bonding glue of the bonding of UV solution, pyrolysis bonding or the bonding of laser solution, so as to complete technique
Afterwards, change the viscosity of bonding glue 40 by modes such as UV radiation, heating, laser, discharge the heavy cloth of fan-out-type wafer-level packaging part
Line layer 21.First rigid support plate 50 can be glass support plate, be also possible to metal support plate, in the present embodiment, UV is temporarily bonded
Glue and glass support plate are optimum combination.
Step 530, from the encapsulated layer side of fan-out-type wafer-level packaging part towards the direction of the first rigid support plate, to being fanned out to
Type wafer-level packaging part carries out thinned, and multiple chips is made to be synchronized to be thinned with encapsulated layer.
Incorporated by reference to Fig. 6 (c), thinning process be for chip 23 silicon base layer and encapsulated layer 22 carry out it is thinned, be thinned after,
Chip 23 is equal with the thickness of encapsulated layer 22, a side surface of chip 23 and the flush of encapsulated layer 22 and is exposed to encapsulated layer
22 outside.Thinned by carrying out to the fan-out package part for having completed the encapsulation of chip 23, chip 23 and encapsulated layer 22 obtain
It is thinned simultaneously, also, makes protection of the chip 23 in entire thinning process all by encapsulated layer 22, avoid directly to naked core
Piece 23 such as is cut, is picked up at the packaging technologies operation, reduces the damaged probability of chip 23.
Wherein, thinned process is carried out to fan-out-type wafer-level packaging part, may particularly include:
Mechanical reduction is carried out to 22 side of encapsulated layer of fan-out-type wafer-level packaging part, keeps multiple chips and encapsulated layer same
Step is thinned；
The encapsulated layer side of fan-out-type wafer-level packaging part is thinned again, multiple chips is made to be synchronized to subtract with encapsulated layer
It is thin.Being thinned again can be carried out by way of dry plasma etch.
Firstly, using the machine of being thinned, by corase grinding and fine grinding technology process, by 23 He of chip of fan-out-type wafer-level packaging part
The thickness of encapsulated layer 22 be thinned to 50 μm hereinafter, be thinned after chip 23 and encapsulated layer 22 thickness it is smaller, flexibility bendable
The ability of song deformation is stronger.
After mechanical reduction, ICP (Inductive Coupled Plasma Emission can be passed through
Spectrometer, inductively coupled plasma spectrum generator) dry plasma etch is carried out, to the surface of silicon and encapsulated layer 22
Grinding residual stress layer be removed, the thickness of removal is about 1 μm~5 μm.Preferably, chip 23 and encapsulation in the present embodiment
Layer 22 be thinned after with a thickness of 25 μm~35 μm.It is appreciated that the purpose of carrying out the step of dry plasma etch is to remove
The residual stress generated during mechanical reduction, therefore, the step of dry plasma etch is optional step.
Step 540, the encapsulated layer side of the fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains
Flexible fan-out-type wafer-level packaging part.
Incorporated by reference to Fig. 6 (d), before forming polymer film layer 24, to the envelope of the fan-out-type wafer-level packaging part after being thinned
It fills 22 side of layer and carries out plasma cleaning, then, 22 side of encapsulated layer of the fan-out-type wafer-level packaging part after being thinned is formed
One layer of polymer film layer 24, so that the surface of chip 23 and encapsulated layer 22 after the covering of polymer film layer 24 is thinned, forms
Flexible package layer, to obtain flexible fan-out-type wafer-level packaging part, flexible fan-out-type wafer-level packaging part includes rerouting layer
21, chip 23 after being thinned, be thinned after encapsulated layer 22 and polymer film layer 24, flexible fan-out-type wafer-level packaging part refers to
Chip 23 after rerouting layer 21, being thinned, be thinned after encapsulated layer 22 and the structures such as polymer film layer 24 be provided with flexible change
The ability of shape.In the application, the effect of polymer film layer 24 is that chip 23 is sealed and is protected, and can both stop moisture
The interface between chip 23 and encapsulated layer 22 is invaded, generation tensile stress between chip 23 and encapsulated layer 22 is also inhibited to split in bending
Line, while protecting chip 23 not because external force is damaged.
Type used by polymer film layer 24 is including but not limited to following several: epoxy resin, PI polyimides
The high Molecularly Imprinted Polymers such as class, BCB benzocyclobutane alkenes, macromolecule membrane packaging method can be the side such as spin coating, spraying, hot pressing
Method, to form polymer film layer 24 by above-mentioned material and technique.
In the present embodiment, preferably 20 μm~50 μm of the thickness of polymer film layer 24, polymer film layer 24 is thinner,
More be conducive to the flexible bending deformation of packaging body.But thinner film layer inhibits to the intrusion of moisture and the suppression of bending tensile stress
Make weaker, therefore, when preparation comprehensively considers the thickness of selection polymer film layer 24.
Step 550, scribing is carried out to flexible fan-out-type wafer-level packaging part, includes at least one core in each scribe region
Piece.
Incorporated by reference to Fig. 6 (e), by laser or saw blade, scribing is carried out to flexible fan-out-type wafer-level packaging part, scribing
Depth is greater than the thickness of flexible fan-out-type wafer-level packaging part namely the depth of scribing reaches bonding glue 40, every after having cut
One individual packaging body may include 1 chip 23 or the chipset being made of multiple chips 23.
Step 560, by the rewiring layer side of the flexible fan-out-type wafer-level packaging part after scribing and the first rigid support plate
Separation, obtains multiple flexible chips.
Incorporated by reference to Fig. 6 (f), after completing scribing, the viscosity for changing UV and being temporarily bonded glue 40 is radiated by UV, release is flexible
The rewiring layer 21 of fan-out-type wafer-level packaging part, obtains multiple flexible chips, and multiple flexible chip includes rewiring layer
21, chip 23, encapsulated layer 22, polymer film layer 24 and solder bump.
By above-mentioned process flow steps, the chip 23 of obtained ultrathin and its encapsulation all have flexible, flexible
The ability of deformation is able to bear the bending of specific degrees.It, can be with electricity when flexible chip patch is assembled on flexible circuit board
Road plate carries out flexible bending deformation together.Flexible circuit board refers to FPC circuit board or COF circuit board.
The preparation method of the flexible chip of the application provides fan-out-type wafer-level packaging part, fan-out-type wafer-level packaging part
Including rerouting layer, encapsulated layer and positioned at the multiple chips rerouted between layer and encapsulated layer, to fan-out-type wafer-level packaging part
Encapsulated layer side carry out thinned, make multiple chips be synchronized to be thinned with encapsulated layer, the fan-out-type wafer-level packaging after being thinned
The encapsulated layer side of part forms polymer film layer, obtains flexible fan-out-type wafer-level packaging part, cuts flexible fan-out-type wafer
Grade packaging part, obtains multiple flexible chips.In this way, the present invention proposes on the basis of fan-out-type wafer-level packaging
A kind of chip and the new method for encapsulating common flexibility, by be thinned to the fan-out package part for having completed encapsulation and again
Secondary encapsulation so that chip and original encapsulated layer obtain synchronous flexibility and be thinned, and makes chip entirely again in encapsulation process
Protection all by untouched dress, to realize the flexibility after chip package and reduce fraction defective.
The principles and effects of the application are only illustrated in above-described embodiment, not for limitation the application.It is any ripe
Know the personage of this technology all can without prejudice to spirit herein and under the scope of, carry out modifications and changes to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from spirit disclosed herein and institute under technical idea such as
At all equivalent modifications or change, should be covered by claims hereof.
Claims (11)
1. a kind of preparation method of flexible chip characterized by comprising
A. fan-out-type wafer-level packaging part is provided, the fan-out-type wafer-level packaging part includes rerouting layer, encapsulated layer and being located at
The multiple chips rerouted between layer and the encapsulated layer；
B. the encapsulated layer side of the fan-out-type wafer-level packaging part is carried out thinned, makes the multiple chip and the encapsulated layer
It is synchronized to be thinned；
C. the encapsulated layer side of the fan-out-type wafer-level packaging part after being thinned forms polymer film layer, obtains flexible fan-out-type
Wafer-level packaging part；
D. the flexible fan-out-type wafer-level packaging part is cut, multiple flexible chips are obtained.
2. the preparation method of flexible chip according to claim 1, which is characterized in that step b includes:
Mechanical reduction is carried out to the encapsulated layer side of the fan-out-type wafer-level packaging part, makes the multiple chip and the encapsulation
Layer is synchronized to be thinned；
The encapsulated layer side of the fan-out-type wafer-level packaging part is thinned again, makes the multiple chip and the encapsulated layer
It is synchronized to be thinned.
3. the preparation method of flexible chip according to claim 1, which is characterized in that step b includes:
The rewiring layer side of the fan-out-type wafer-level packaging part is attached on the first rigid support plate；
From the encapsulated layer side of the fan-out-type wafer-level packaging part towards the direction of the described first rigid support plate, it is fanned out to described
Type wafer-level packaging part carries out thinned, and the multiple chip is made to be synchronized to be thinned with the encapsulated layer.
4. the preparation method of flexible chip according to claim 3, which is characterized in that when the fan-out-type wafer-level packaging
When the rewiring layer side of part includes solder bump, step d includes:
Scribing is carried out to the flexible fan-out-type wafer-level packaging part, includes at least one chip in each scribe region；
The rewiring layer side of flexible fan-out-type wafer-level packaging part after scribing is separated with the described first rigid support plate, is obtained
Multiple flexible chips.
5. the preparation method of flexible chip according to claim 3, which is characterized in that when the fan-out-type wafer-level packaging
When the rewiring layer side of part does not include solder bump, before step d, further includes:
The polymer film layer side of the flexible fan-out-type wafer-level packaging part is attached on the second rigid support plate；
The rewiring layer side of the flexible fan-out-type wafer-level packaging part is separated with the described first rigid support plate；
Solder bump is formed on the rewiring layer of the flexible fan-out-type wafer-level packaging part.
6. the preparation method of flexible chip according to claim 5, which is characterized in that step d includes:
Scribing is carried out to the flexible fan-out-type wafer-level packaging part after formation solder bump, includes at least one in each scribe region
A chip；
The polymer film layer side of flexible fan-out-type wafer-level packaging part after scribing is separated with the described second rigid support plate,
Obtain multiple flexible chips.
7. the preparation method of flexible chip according to claim 5, which is characterized in that described by the fan-out-type wafer
The rewiring layer side of grade packaging part is attached in the step on the first rigid support plate, and, the flexibility is fanned out to described
The polymer film layer side of type wafer-level packaging part is attached in the step on the second rigid support plate, realizes institute using bonding glue
Attaching connection is stated, the bonding glue is the bonding glue of the bonding of UV solution, pyrolysis bonding or the bonding of laser solution.
8. the preparation method of flexible chip described in any one of -7 claims according to claim 1, which is characterized in that step c
In, the polymer film layer is formed by spin coating, spraying or hot pressing.
9. the preparation method of flexible chip according to claim 8, which is characterized in that the polymer film layer is epoxy
Resinae, polyimide or benzocyclobutane alkenes high molecular polymer.
10. the preparation method of flexible chip according to claim 1, which is characterized in that sealed to the fan-out-type wafer scale
The encapsulated layer side of piece installing carries out mechanical reduction, make that the multiple chip and the encapsulated layer be synchronized to be thinned to a thickness of 25
μm~35 μm, the polymer film layer with a thickness of 20 μm~50 μm.
11. a kind of flexible chip, which is characterized in that using the preparation such as flexible chip of any of claims 1-10
Method is prepared.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613579A (en) * | 2020-05-17 | 2020-09-01 | 西北工业大学 | Flexible manufacturing method of IC chip |
| CN112687650A (en) * | 2019-10-17 | 2021-04-20 | 浙江荷清柔性电子技术有限公司 | Packaging structure and flexible integrated packaging method of ultrathin chip |
| CN113035796A (en) * | 2021-03-01 | 2021-06-25 | 青岛歌尔智能传感器有限公司 | Antenna packaging structure, preparation method thereof and electronic device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
| CN101436554A (en) * | 2007-11-15 | 2009-05-20 | 南茂科技股份有限公司 | Method for manufacturing package structure with reconfigured crystal particle by aligning mark |
| CN102593016A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院微电子研究所 | Method for mounting thin chip on flexible substrate |
| CN103681458A (en) * | 2012-09-03 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional flexible stacked packaging structure of embedded ultrathin chip |
| KR101393701B1 (en) * | 2012-11-29 | 2014-05-13 | 서울과학기술대학교 산학협력단 | Manufacturing of fan-out wafer level packaging for preventing warpage and emittingthermal energy of wafer |
| CN104701196A (en) * | 2013-12-09 | 2015-06-10 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| US9524959B1 (en) * | 2015-11-04 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | System on integrated chips and methods of forming same |
| CN106601628A (en) * | 2016-12-30 | 2017-04-26 | 通富微电子股份有限公司 | Chip packaging method and chip packaging structure |
| CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
-
2019
- 2019-06-17 CN CN201910523339.2A patent/CN110335815A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
| CN101436554A (en) * | 2007-11-15 | 2009-05-20 | 南茂科技股份有限公司 | Method for manufacturing package structure with reconfigured crystal particle by aligning mark |
| CN102593016A (en) * | 2012-03-20 | 2012-07-18 | 中国科学院微电子研究所 | Method for mounting thin chip on flexible substrate |
| CN103681458A (en) * | 2012-09-03 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional flexible stacked packaging structure of embedded ultrathin chip |
| KR101393701B1 (en) * | 2012-11-29 | 2014-05-13 | 서울과학기술대학교 산학협력단 | Manufacturing of fan-out wafer level packaging for preventing warpage and emittingthermal energy of wafer |
| CN104701196A (en) * | 2013-12-09 | 2015-06-10 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| US9524959B1 (en) * | 2015-11-04 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | System on integrated chips and methods of forming same |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN106601628A (en) * | 2016-12-30 | 2017-04-26 | 通富微电子股份有限公司 | Chip packaging method and chip packaging structure |
| CN106876291A (en) * | 2016-12-30 | 2017-06-20 | 清华大学 | A kind of thin chip flexibility is fanned out to method for packing and prepared encapsulating structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687650A (en) * | 2019-10-17 | 2021-04-20 | 浙江荷清柔性电子技术有限公司 | Packaging structure and flexible integrated packaging method of ultrathin chip |
| CN111613579A (en) * | 2020-05-17 | 2020-09-01 | 西北工业大学 | Flexible manufacturing method of IC chip |
| CN111613579B (en) * | 2020-05-17 | 2023-09-26 | 西北工业大学 | Flexible manufacturing method of IC chip |
| CN113035796A (en) * | 2021-03-01 | 2021-06-25 | 青岛歌尔智能传感器有限公司 | Antenna packaging structure, preparation method thereof and electronic device |
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Application publication date: 20191015 |