CN110324025A - Ultra-wideband pulse circuits and design method with suppressing NBI function - Google Patents
Ultra-wideband pulse circuits and design method with suppressing NBI function Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
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Abstract
Ultra-wideband pulse circuits and design method with suppressing NBI function, is related to ultra-wideband pulse IR-UWB.It is made of digital triangular pulse generation circuit and output-stage circuit and load；Wherein digital triangular pulse generation circuit is made of multiple time-delay unit circuits, nor gate, NAND gate, output stage is made of multiple PMOS tube and NMOS, the triangular pulse signal that the number triangular pulse generation circuit generates inputs each nor gate and NAND gate through each time-delay unit circuit, successively generate negative triangular pulse and positive triangle pulse signal, it is connected together by output-stage circuit, combines continuous Gaussian pulse signal through overload.This circuit generates pulse in such a way that two Gaussian pulse signals combine, it is higher than single Gaussian pulse to the utilization rate of UWB spectrum to combine signal, to which largerization ground utilizes Emission Mask, reduce and the narrowband systems of any position frequency range are interfered, achievees the purpose that reduce cost, reduces power consumption.
Description
Technical field
The present invention relates to ultra-wideband pulse IR-UWB technical fields, and in particular to a kind of ultra-wide with suppressing NBI function
Tape pulse circuits and design method, the wireless communication system suitable for high-speed, low-power consumption and positioning function.
Background technique
Ultra wide band (UWB) technology is initially that the application such as accurate ULTRA-WIDEBAND RADAR and antijam wireless communication is provided for military project.
In recent years, the frequency range of growing tension, which divides, makes the wireless technology of shared frequency spectrum become research hotspot, and representative is exactly super
Broadband wireless communication technique.Ultrabroad-band spectrum occupies very wide frequency band, and only carrying out limitation to its transmission power could be with
Existing narrowband systems coexist.
UWB frequency range as defined in Federal Communications Commission (FCC) is 3.1GHz~10.6GHz (such as Fig. 1 and Fig. 2), and
And the power spectral density (ESD) of the Emission Mask specification IR-UWB of UWB signal has been issued, to reduce to narrow-bandpass filter, but
UWB signal can not be fully solved to other narrow band signals, such as GPS, bluetooth and WLAN (IEEE 802.11a/b)
Interference.Now there are mainly two types of methods to solve the problems, such as this narrow-bandpass filter, and one of method is existing using not including
The UWB signal of narrowband slice, such as the frequency range of WLAN signal is 5.15~5.35GHz, and the working frequency range of UWB is selected 3.1
~selected between 5GHz and 6~10.6GHz, but Emission Mask can not be maximally utilized.Second method is by designing IR-
UWB waveform generates trap at the working frequency of narrowband systems, such as design power spectrum can generate the wave of trap at 5GHz
Shape can inhibit the interference to 5GHz frequency range narrow-band communication system.
Emission Mask is maximally utilized currently, being mainly concentrated on the market to the research of super-broadband tech, to pulse
The research of waveform and circuit design is seldom, and especially to the collision problem of existing narrow band communication, there is no solve.
Summary of the invention
To solve the above-mentioned problems, the present invention provides a kind of ultra-wideband pulse circuit with suppressing NBI function with set
Meter method.
Ultra-wideband pulse circuit with suppressing NBI function, by digital triangular pulse generation circuit and output-stage circuit and
Load composition；Wherein digital triangular pulse generation circuit is by time-delay unit circuit 111, time-delay unit circuit 112, delay unit electricity
Road 113, time-delay unit circuit 211, time-delay unit circuit 212, time-delay unit circuit 213, nor gate 133, nor gate 132 or
NOT gate 131, NAND gate 121, NAND gate 123 and NAND gate 122 are constituted, and output stage is by PMOS tube P1, PMOS tube P2, PMOS tube P3
With NMOS tube N1, NMOS tube N2, NMOS tube N3 composition, an input of 111 one end of time-delay unit circuit connection NAND gate 123
Hold and as signal input part, the other end and one end of time-delay unit circuit 112, an input terminal of nor gate 133 and with it is non-
Another input terminal connection of door 123, another input terminal of the other end AND OR NOT gate 133 of time-delay unit circuit 112, NAND gate
122 1 input terminals are connected with 113 one end of time-delay unit circuit, the input of 113 other end AND OR NOT gate 132 1 of time-delay unit circuit
End, another input terminal of NAND gate 122 and the defeated connection of time-delay unit circuit 211 1,211 other end of time-delay unit circuit and delay are single
First 212 one end of circuit, another input terminal of nor gate 132 are connected with 121 1 input terminal of NAND gate, and time-delay unit circuit 212 is another
End is connect with 213 one end of time-delay unit circuit, another input terminal of NAND gate 121 and 131 1 input terminal of nor gate, delay unit electricity
213 other end of road connects another input terminal of nor gate 131；
Grid connection 123 output end of NAND gate, the source electrode of PMOS tube P1 connects power supply, drain electrode and the drain electrode of NMOS tube N1 and connects
It connects, the output end of the grid connection nor gate 133 of NMOS tube N1, source electrode ground connection,
Grid connection 122 output end of NAND gate, the source electrode of PMOS tube P2 connects power supply, drain electrode and the drain electrode of NMOS tube N2 and connects
It connects, the output end of the grid connection nor gate 132 of NMOS tube N2, source electrode ground connection,
Grid connection 121 output end of NAND gate, the source electrode of PMOS tube P3 connects power supply, drain electrode and the drain electrode of NMOS tube N3 and connects
It connects, the output end of the grid connection nor gate 131 of NMOS tube N3, source electrode ground connection；
Load is connect through capacitor with the drain electrode of PMOS tube P1, PMOS tube P2 and PMOS tube P3.
The time-delay unit circuit is managed by MP2, MN2 pipe, MP1 pipe, MP1a pipe and MP1b pipe are constituted, MP2 pipe and MN2 pipe
Grid connects and as input terminal, drain electrode and drain electrode connection and as output end, and the source electrode of MN2 pipe is grounded and the grid with MP1 pipe
The source electrode of pole connection, MP2 pipe is connect with the drain electrode of MP1 pipe, MP1a pipe and MP1b pipe, the source electrode of MP1 pipe, MP1a pipe and MP1b pipe
It is connected and connects to power supply, MP1a pipe connects control terminal with the grid of MP1b pipe.
The PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N1, NMOS tube N2, NMOS tube N3, MP2 pipe, MN2
Pipe, MP1 pipe, MP1a pipe and MP1b pipe are transistor or field-effect tube.
The triangular pulse signal that the number triangular pulse generation circuit generates inputs each or non-through each time-delay unit circuit
Door and NAND gate, successively generate negative triangular pulse and positive triangle pulse signal, are connected together by output-stage circuit, exported
Node generates output waveform, combines continuous Gaussian pulse signal through overload.
For the output-stage circuit during every group pulse signal generates, only one metal-oxide-semiconductor is conducting.
Ultra-wideband pulse circuit design method with suppressing NBI function is divided first using two Gaussian pulse signals
Analyse two n rank Gaussian pulse Gn(t) and Gn(t- τ), Gn(t- τ) is the delay of previous pulse, and delay time τ then combines arteries and veins
Punching are as follows:
Gc(t)=Gn(t)+Gn(t-τ)(1-1) (1-1)
It enablesThen
Fc(f)=Fn(f)+Fn+ τ (f)=Fn(f)[1+exp(-j2πfτ)] (1-2)
Correspondingly, the power spectral density P of assembled pulsec(f) are as follows:
Pc(f)=2Pn(f)[1+cos(2πfτ)] (1-3)
Above formula shows that the ESD of assembled pulse is equal to ESD and cosine function multiplication of single pulse.So combination arteries and veins
The ESD of punching can also occur while cosine function " wave crest " occurs with " trough ":
fmin=(k+1/2)/τ (1-4)
fmax=k/ τ (1-5)
Wherein k is positive integer, fmaxAnd fminIt is the frequency at assembled pulse ESD " trough " and " wave crest " respectively；From upper
Formula can be seen that the frequency of " trough " and " wave crest " and delay τ is inversely proportional, and even two n rank Gaussian pulse delay τ are bigger, fmax
With fminFrequency it is lower, the number for occurring peaks and troughs in same frequency range is more, and the number of trap is also more.
The beneficial effects of the present invention are: this circuit uses two Gaussian pulse signals, one of Gaussian pulse is another
The delay of a Gaussian pulse, latter two right signal is superimposed in the time domain, and each Gaussian pulse transforms to UWB spectrum on frequency domain
Different zones, when signal combination, composite signal is higher than single Gaussian pulse to the utilization rate of UWB spectrum, thus largerization
Ground utilizes Emission Mask, reduces and interferes the narrowband systems of any position frequency range, achievees the purpose that reduce cost, reduces power consumption；
Assembled pulse is used simultaneously, a trap can be introduced in UWB spectrum, such as when trap is in 5.9GHz, it will reduce IR-
Interference of the UWB system to Wi-Fi wireless system, and different delays is used, the position of trap is also different, and the number of trap is same
At sample more than one；Many places trap is generated by assembled pulse, had not only solved the problems, such as the UWB Emission Mask availability of frequency spectrum, but also solve
UWB signal and other wireless systems interfere with each other problem.
Detailed description of the invention
Fig. 1 is interior UWB transmission power as defined in FCC and frequency spectrum limitation figure.
Fig. 2 is power spectral density plot of the FCC about the Emission Mask specification IR-UWB of UWB signal.
Fig. 3 is the assembled pulse time domain waveform and power spectral density plot under different delays.
Fig. 4 is the time domain and frequency-domain waveform figure that the present invention inhibits 5GHz band interference.
Fig. 5 is electrical block diagram of the embodiment of the present invention.
Fig. 6 is composite pulse generation circuit schematic diagram of the present invention.
Fig. 7 is the positive and negative pulse-generating circuit of the present invention and time-delay unit circuit schematic diagram.
Fig. 8 is output-stage circuit partial enlarged view of the present invention.
Fig. 9 is the positive negative pulse stuffing schematic diagram of each node of the present invention.
Figure 10 is assembled pulse waveform Transient figure of the present invention.
Figure 11 is the assembled pulse power spectral density plot that the present invention inhibits narrowband interference.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples:
Shown in refering to fig. 1~11, the ultra-wideband pulse circuit with suppressing NBI function generates electricity by digital triangular pulse
Road 1 and output-stage circuit 2 and 3 composition of load；Wherein digital triangular pulse generation circuit 1 is single by time-delay unit circuit 111, delay
First circuit 112, time-delay unit circuit 113, time-delay unit circuit 211, time-delay unit circuit 212, time-delay unit circuit 213 or
NOT gate 133, nor gate 132, nor gate 131, NAND gate 121, NAND gate 123 and NAND gate 122 are constituted, and output stage 2 is by PMOS
Pipe P1, PMOS tube P2, PMOS tube P3 and NMOS tube N1, NMOS tube N2, NMOS tube N3 composition, the time-delay unit circuit 111 1
End connects an input terminal of NAND gate 123 and as the signal input part (output signal with the digital baseband of upper level circuit
Connect, be not shown), the other end is another with one end of time-delay unit circuit 112, an input terminal of nor gate 133 and NAND gate 123
The connection of one input terminal, another input terminal, 122 1 input terminal of NAND gate of the other end AND OR NOT gate 133 of time-delay unit circuit 112
It is connected with 113 one end of time-delay unit circuit, 113 other end AND OR NOT gate of time-delay unit circuit, 132 1 input terminal, NAND gate 122
Another input terminal and the defeated connection of time-delay unit circuit 211 1,211 other end of time-delay unit circuit and time-delay unit circuit 212 1
End, another input terminal of nor gate 132 are connected with 121 1 input terminal of NAND gate, 212 other end of time-delay unit circuit and delay unit
213 one end of circuit, another input terminal of NAND gate 121 are connected with 131 1 input terminal of nor gate, 213 other end of time-delay unit circuit
Connect another input terminal of nor gate 131；Grid connection 123 output end of NAND gate, the source electrode of PMOS tube P1 connect power supply, drain electrode with
The drain electrode of NMOS tube N1 connects, the output end of the grid connection nor gate 133 of NMOS tube N1, source electrode ground connection, the grid of PMOS tube P2
Pole connection 122 output end of NAND gate, source electrode connect power supply, drain electrode and the drain electrode of NMOS tube N2 and connect, the grid connection of NMOS tube N2
The output end of nor gate 132, source electrode ground connection, grid connection 121 output end of NAND gate, the source electrode of PMOS tube P3 connect power supply, drain electrode
It is connect with the drain electrode of NMOS tube N3, the output end of the grid connection nor gate 131 of NMOS tube N3, source electrode ground connection；Load 3 is through capacitor
It is connect with the drain electrode of PMOS tube P1, PMOS tube P2 and PMOS tube P3.
The time-delay unit circuit is managed by MP2, MN2 pipe, MP1 pipe, MP1a pipe and MP1b pipe are constituted, MP2 pipe and MN2 pipe
Grid connects and as input terminal, drain electrode and drain electrode connection and as output end, and the source electrode of MN2 pipe is grounded and the grid with MP1 pipe
The source electrode of pole connection, MP2 pipe is connect with the drain electrode of MP1 pipe, MP1a pipe and MP1b pipe, the source electrode of MP1 pipe, MP1a pipe and MP1b pipe
Be connected and connect to power supply, MP1a pipe connects control terminal with the grid of MP1b pipe (upper level circuit is not shown).
The PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N1, NMOS tube N2, NMOS tube N3, MP2 pipe, MN2
Pipe, MP1 pipe, MP1a pipe and MP1b pipe are transistor or field-effect tube.
The triangular pulse signal that the number triangular pulse generation circuit 1 generates inputs each or non-through each time-delay unit circuit
Door and NAND gate, successively generate negative triangular pulse and positive triangle pulse signal, are connected together by output-stage circuit 2, defeated
Node generates output waveform out, combines continuous Gaussian pulse signal through overload 3.
For the output-stage circuit 2 during every group pulse signal generates, only one metal-oxide-semiconductor is conducting.
This circuit design method uses two Gaussian pulse signals, analyzes two n rank Gaussian pulse G firstn(t) and Gn(t-
τ), Gn(t- τ) is delay of previous pulse, delay time τ, then assembled pulse are as follows:
Cc(t)=Cn(t)+Gn(t-τ)(1-1) (1-1)
It enablesThen
Fc(f)=Fn(f)+Fn+τ(f)=Fn(f)[1+exp(-j2πfτ)] (1-2)
Correspondingly, the power spectral density P of assembled pulsec(f) are as follows:
Pc(f)=2Pn(f)[1+cos(2πfτ)] (1-3)
Above formula shows that the ESD of assembled pulse is equal to ESD and cosine function multiplication of single pulse.So combination arteries and veins
The ESD of punching can also occur while cosine function " wave crest " occurs with " trough ":
fmin=(k+1/2)/τ (1-4)
fmax=k/ τ (1-5)
Wherein k is positive integer, fmaxAnd fminIt is the frequency at assembled pulse ESD " trough " and " wave crest " respectively.From upper
Formula can be seen that the frequency of " trough " and " wave crest " and delay τ is inversely proportional, and even two n rank Gaussian pulse delay τ are bigger, fmax
With fminFrequency it is lower, the number for occurring peaks and troughs in same frequency range is more, and the number of trap is also more.
The time domain waveform of assembled pulse under different delayed time and power spectral density simulation result such as Fig. 3, wherein a arteries and veins in Fig. 3
When punching delay τ is 0.0862ns, only one trap is 5.814GHz (as shown in b in Fig. 3), consistent with theory analysis, and
As the increase time domain waveform pulsewidth of delay time increases, trap number also be will increase, but all include 5.8GHz frequency range；Such as figure
When c pulse delay τ is 0.2586ns in 3, generating two traps is 5.814GHz and 9.674GHz (as shown in d in Fig. 3)；Such as figure
When e pulse delay τ is 0.431ns in 3, generation trap is 3.47GHz, 5.814GHz, 8.127GHz and 10.44GHz (such as Fig. 3
Shown in middle f)；As when g pulse delay τ is 0.6034ns in Fig. 3, there are 5 traps in the range as defined in UWB, it is respectively
Theoretically, we can pass through selection by 4.14GHz, 5.81GHz, 7.47GH, 9.11GHz and 10.8GHz (as shown in h in Fig. 3)
Suitable delay time is located to generate desired trap at an arbitrary position.
Fig. 4 show the time domain and frequency-domain waveform for inhibiting 5GHz band interference, inhibits the generation to 5GHz frequency range to interfere, benefit
With 5 rank Gaussian pulses by delay time Dealy=0.1ns, two 5 rank Gaussian functions are then combined, from the power spectrum of frequency domain
Degree, which can be seen that, produces trap in 5GHz (as shown in b in Fig. 4) frequency range, reaches the interference inhibited to the frequency range, such as a in Fig. 4
It is shown that table table 1 is summarized as follows to each pulse and amplitude.
Table 1
| Pulse | 1 | 2 | 3 | 4 | 5 | 6 |
| Pulsewidth (ps) | 82 | 70 | 51 | 51 | 70 | 82 |
| Amplitude (mV) | 375 | -660 | 485 | -480 | 640 | -350 |
Refering to Fig. 5 and Fig. 6, the triangular pulse that digital triangular pulse generation circuit 1 generates is the input of rear stage, input
Digit pulse and it is reversed after postpones signal successively pass through NAND gate and nor gate is used to generate negative triangular pulse and positive three
Angle pulse (in such as Fig. 6 shown in (a)).(b) shows the variation of A, B, C, D voltage node, the voltage wave of A, C, E node in Fig. 6
Shape is the negative triangular pulse from VDD to ground, B, D, F node voltage waveform be arrive the positive triangle pulse of VDD, each node voltage
Possess identical amplitude.In order to which four different signals of phase are synthesized to together, it is adjustable delay phase inverter delay when
Between control the pulse width of each node triangular pulse, then four signals are successively exported, in very short following period of time,
Triangular pulse waveform is approximately Gaussian pulse, alternatively referred to as class Gaussian pulse.Output-stage circuit 2 PMOS tube P1~P3,
The size of NMOS tube N1~N3 control output electric current, input signal is the class Gaussian pulse that prime generates, and adjusts PMOS tube P1
The voltage amplitude of the changeable Vout node of size of~P3, NMOS tube N1~N3, finally, under 50 Ω load 3, it is continuous by six
Together, obtained Gaussian pulse is approximately the assembled pulse of design to pulse combined.Since six pulses continuously combined are only
Vertical Gauss class pulse, therefore referred to as pulse combined method.During each assembled pulse generates, there was only one in output-stage circuit 2
A metal-oxide-semiconductor is conducting, this makes power consumption very low.
Refering to Fig. 7, in time-delay unit circuit (in such as Fig. 7 shown in (c)), transistor MP1, MP1a and MP1b mention for MP2
For source level electric current.The control voltage variable of MP1a and MP1b, for adjusting the source level electric current of MP2, thus when reaching change delay
Between purpose.In class Gaussian pulse generation circuit, input signal by delay after together with the signal not being delayed input with it is non-
Door obtains negative pulse when being all " 1 " (in such as Fig. 7 shown in (a))；It is similar, when signal is input to nor gate, when being all " 0 "
When, obtain positive pulse (in such as Fig. 7 shown in (b)).
Refering to Fig. 8, in output-stage circuit, when negative pulse generates, PMOS tube charges to capacitor, and negative pulse disappears later
It loses, and then positive pulse generates, and control NMOS discharges to capacitor, will appear as the wave of voltage in output loading in this way
It is dynamic.
Fig. 9 is the positive negative pulse stuffing of each node, is successively the node voltage of A, B, C, D, E, F in Fig. 6, Cong Zhongke from top to bottom
To find out, after delay unit, each node voltage is sequentially output.
Figure 10 is assembled pulse circuit waveform Transient as a result, indicating the voltage of output node Vout, the group with design
Multiplex shape is compared close to identical.
Figure 11 is with the assembled pulse power spectral density for inhibiting narrowband interference, the power spectrum of 10 time domain waveform of analysis chart
Degree obtains Figure 11, it can be seen that the power spectral density of the waveform produces trap at 5GHz.
This circuit uses two Gaussian pulse signals, and one of Gaussian pulse is the delay of another Gaussian pulse, so
Latter two signal is superimposed in the time domain, and each Gaussian pulse transforms to the different zones of UWB spectrum on frequency domain, when signal combines
When, composite signal is higher than single Gaussian pulse to the utilization rate of UWB spectrum, thus largerization ground utilize Emission Mask, reduce
Narrowband systems interference to any position frequency range achievees the purpose that reduce cost, reduces power consumption；Assembled pulse, meeting are used simultaneously
A trap is introduced in UWB spectrum, such as when trap is in 5.9GHz, it will it is wireless to Wi-Fi to reduce IR-UWB system
The interference of system, and different delays is used, the position of trap is also different, at the number same more than one of trap；Pass through group
It closes pulse and generates many places trap, not only solved the problems, such as the UWB Emission Mask availability of frequency spectrum, but also solve UWB signal and other nothings
Linear system system interferes with each other problem.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
The change or replacement expected without creative work should all be covered subject to the scope of the present invention.
Claims (6)
1. the ultra-wideband pulse circuit with suppressing NBI function, by digital triangular pulse generation circuit (1) and output-stage circuit
(2) it is formed with load (3)；It is characterized by: it is described number triangular pulse generation circuit (1) by time-delay unit circuit (111), prolong
When element circuit (112), time-delay unit circuit (113), time-delay unit circuit (211), time-delay unit circuit (212), delay it is single
First circuit (213), nor gate (133), nor gate (132), nor gate (131), NAND gate (121), NAND gate (122) He Yufei
Door (123) is constituted, and output stage (2) is by PMOS tube P1, PMOS tube P2, PMOS tube P3 and NMOS tube N1, NMOS tube N2, NMOS tube N3
Composition, described time-delay unit circuit (111) one end connect an input terminal of NAND gate (123) and as signal input parts, separately
The one end, an input terminal of nor gate (133) and another input terminal of NAND gate (123) of one end and time-delay unit circuit (112)
Connection, another input terminal of the other end AND OR NOT gate (133) of time-delay unit circuit (112), (122) one input terminal of NAND gate and
The connection of time-delay unit circuit (113) one end, (132) one input terminal of time-delay unit circuit (113) other end AND OR NOT gate, NAND gate
(122) another input terminal and the defeated connection of time-delay unit circuit (211) one, time-delay unit circuit (211) other end and delay unit
Circuit (212) one end, nor gate (132) another input terminal are connected with (121) one input terminal of NAND gate, time-delay unit circuit
(212) other end and (131) one input terminal of time-delay unit circuit (213) one end, another input terminal of NAND gate (121) and nor gate
Connection, time-delay unit circuit (213) other end connect nor gate (131) another input terminal；PMOS tube P1 grid connection with it is non-
Door (123) output end, source electrode connect power supply, drain electrode and the drain electrode of NMOS tube N1 and connect, and the grid of NMOS tube N1 connects nor gate
(133) output end, source electrode ground connection, grid connection NAND gate (122) output end, the source electrode of PMOS tube P2 connect power supply, drain electrode with
The drain electrode of NMOS tube N2 connects, the output end of grid connection nor gate (132) of NMOS tube N2, source electrode ground connection, PMOS tube P3's
Grid connection NAND gate (121) output end, source electrode connect power supply, drain electrode and the drain electrode of NMOS tube N3 and connect, the grid of NMOS tube N3
Connect output end, the source electrode ground connection of nor gate (131)；(3) are loaded through capacitor and PMOS tube P1, PMOS tube P2 and PMOS tube P3
Drain electrode connection.
2. the ultra-wideband pulse circuit according to claim 1 with suppressing NBI function, it is characterised in that: the delay
Element circuit is managed by MP2, MN2 pipe, MP1 pipe, MP1a pipe and MP1b pipe are constituted, and MP2 pipe is connect and as defeated with the grid of MN2 pipe
Enter end, drain electrode with drain electrode connection and as output end, the source electrode of MN2 pipe is grounded simultaneously to be connect, the source of MP2 pipe with the grid of MP1 pipe
Pole is managed with MP1, the drain electrode of MP1a pipe and MP1b pipe is connect, and the source electrode of MP1 pipe, MP1a pipe and MP1b pipe is connected and connects with power supply
It connects, MP1a pipe connects control terminal with the grid of MP1b pipe.
3. the ultra-wideband pulse circuit according to claim 1 or 2 with suppressing NBI function, it is characterised in that: described
PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N1, NMOS tube N2, NMOS tube N3, MP2 pipe, MN2 pipe, MP1 pipe, MP1a
Pipe and MP1b pipe are transistor or field-effect tube.
4. the ultra-wideband pulse circuit according to claim 1 with suppressing NBI function, it is characterised in that: the number
The triangular pulse signal that triangular pulse generation circuit (1) generates inputs each nor gate and NAND gate through each time-delay unit circuit, first
After generate negative triangular pulse and positive triangle pulse signal, connected together by output-stage circuit (2), output node generate it is defeated
Waveform out combines continuous Gaussian pulse signal through overload (3).
5. the ultra-wideband pulse circuit according to claim 1 with suppressing NBI function, it is characterised in that: the output
For grade circuit (2) during every group pulse signal generates, only one metal-oxide-semiconductor is conducting.
6. a kind of ultra-wideband pulse circuit design method with suppressing NBI function according to claim 1 or 4 or 5,
It is characterized by: analyzing two n rank Gaussian pulse G first using two Gaussian pulse signalsn(t) and Gn(t- τ), Gn(t-τ)
For the delay of previous pulse, delay time τ, then assembled pulse are as follows:
Gc(t)=Gn(t)+Gn(t-τ)(1-1) (1-1)
It enablesThen
Fc(f)=Fn(f)+Fn+τ(f)=Fn(f)[1+exp(-j2πfτ)] (1-2)
Correspondingly, the power spectral density P of assembled pulsec(f) are as follows:
Pc(f)=2Pn(f)[1+cos(2πfτ)] (1-3)
Above formula shows that the ESD of assembled pulse is equal to ESD and cosine function multiplication of single pulse；So assembled pulse
ESD can also occur while cosine function " wave crest " occurs with " trough ":
fmin=(k+1/2)/τ (1-4)
fmax=k/ τ (1-5)
Wherein k is positive integer, fmaxAnd fminIt is the frequency at assembled pulse ESD " trough " and " wave crest " respectively；It can from above formula
To find out, frequency and the delay τ of " trough " and " wave crest " are inversely proportional, and even two n rank Gaussian pulse delay τ are bigger, fmaxWith
fminFrequency it is lower, the number for occurring peaks and troughs in same frequency range is more, and the number of trap is also more.
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| US20070098044A1 (en) * | 2005-09-07 | 2007-05-03 | The Arizona Board Of Regents, A Body Corporate Acting On Behalf Of Arizona State University | Digital low-power CMOS pulse generator for ultra-wideband systems |
| CN1968006A (en) * | 2005-11-17 | 2007-05-23 | 中国科学院半导体研究所 | Circulation circuit voltage-controlled oscillator with temperature compensation effect |
| CN103762960A (en) * | 2012-08-14 | 2014-04-30 | 三星电子株式会社 | Apparatus and method for generating gaussian pulse |
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