CN110323927A - A kind of three-level inverter burst pulse suppressing method and device - Google Patents
A kind of three-level inverter burst pulse suppressing method and device Download PDFInfo
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- CN110323927A CN110323927A CN201910557381.6A CN201910557381A CN110323927A CN 110323927 A CN110323927 A CN 110323927A CN 201910557381 A CN201910557381 A CN 201910557381A CN 110323927 A CN110323927 A CN 110323927A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
Abstract
The invention discloses a kind of three-level inverter burst pulse suppressing method and devices, include the following steps: S1, open in conjunction with IGBT minimum, turn-off time, dead time, the factors such as switching frequency, determining minimum pulse width, calculate its duty ratio；S2, voltage vector magnitude is calculated, carries out marking change processing, and be compared with upper limit value, clipping then is modified to vector magnitude greater than the upper limit；S3, three-phase modulations wave duty ratio is calculated；S4, three-phase modulations wave duty ratio duty ratio corresponding with minimum pulse width is compared, the absolute value of any phase modulating wave duty ratio is less than the corresponding duty ratio of minimum pulse width, the modulating wave duty ratio of the phase is assigned to intermediate variable temp, three-phase modulations wave duty ratio subtracts temp simultaneously；S5, PWM register is updated.The present invention does not need to increase additional hardware circuit, and method is realized simply, relative to the method for using hardware circuit etc. to inhibit burst pulse, can effectively reduce volume, save the cost.
Description
Technical field
The invention belongs to pulse width modulating technology field, be related to a kind of burst pulse inhibit, compensation method, and in particular to one
Kind three-level inverter burst pulse suppressing method and device.
Background technique
With the development of photovoltaic industry, increasingly mature, the requirement to power quality and system effectiveness of inverter technology
Higher and higher, three-level inverter has many advantages, such as that harmonic wave is small compared to traditional two-level inverter, efficiency, high pressure resistant, obtains
Good application effect was obtained, with the development of technology, the promotion of digital processing unit performance, inverter switching frequency is increasingly
The influence of height, burst pulse is more obvious, and under the conditions of burst pulse, IGBT current changing rate dic/dt be will increase, since route exists
Stray inductance can generate higher shutdown voltage overshoot, will appear strong concussion in reversely restoring process, there are excessive pressure damages
Risk, while also resulting in IGBT stress and loss is uneven.
Summary of the invention
In order to solve the problems in the existing technology, the object of the present invention is to provide kind of a three-level inverter burst pulse suppressions
Method and device processed solves the problems, such as the problem of loss of IGBT caused by burst pulse, harmonic wave increase, even aircraft bombing damages.
In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is that:
A kind of three-level inverter burst pulse suppressing method, which comprises the steps of:
Step 1 determines the corresponding duty ratio of minimum pulse width；It is opened in conjunction with IGBT minimum, turn-off time and dead time, really
Determine the corresponding duty ratio of minimum pulse width；
IGBT minimum is opened, closes short time and corresponding dead time with different manufacturers, the IGBT of different model and reality
The factors such as operating switch frequency are different and different, and minimum pulse width should be determined according to IGBT actual condition.
Step 2 calculates voltage vector magnitude, carries out marking change, and be compared with upper limit value, is greater than upper limit value then to electricity
Pressure vector magnitude is modified clipping, and the upper limit value is that maximum duty cycle 1 subtracts the corresponding duty ratio of minimum pulse width；
Step 3 calculates three-phase modulations wave duty ratio according to three level SVPWMs or SPWM modulator approach；
Step 4, by three-phase modulations wave duty ratio duty ratio corresponding with the minimum pulse width that step 1 obtains that step 3 obtains
It is compared:
The absolute value of any phase modulating wave duty ratio is less than the corresponding duty ratio of minimum pulse width, by the modulating wave duty of the phase
Than being assigned to intermediate variable temp, three-phase modulations wave duty ratio subtracts temp simultaneously；To three-phase modulations wave near zero-crossing point, wave processed
The absolute value of duty ratio is less than the burst pulse that the corresponding duty ratio of minimum pulse width generates and is inhibited, compensated.
Step 5 updates PWM register: when the absolute value of three-phase modulations wave duty ratio is greater than the corresponding duty of minimum pulse width
Than then updating the PWM register of corresponding phase with the duty ratio of practical three-phase modulations wave, the PWM register for otherwise corresponding to phase is reset.
Compared with prior art, the present invention at least has the advantages that method of the invention is realized simply, does not need
Increase additional hardware circuit, relative to the method for using hardware circuit etc. to inhibit burst pulse, volume can be effectively reduced, save at
This；This method successively executes step 2 to step 5 in each switch periods, can substantially completely eliminate burst pulse, guarantee
IGBT can be turned on and off reliably in each switch periods, and real-time is stronger.
Detailed description of the invention
Fig. 1 is three level carrier modulation SPWM driving principle figure in the same direction；
Fig. 2 is that modulating wave positive zero crossing burst pulse generates schematic diagram；
Fig. 3 is that modulating wave negative sense zero crossing burst pulse generates schematic diagram；
Fig. 4 is burst pulse suppressing method flow chart；
Fig. 5 is the schematic device for inhibiting three-level inverter burst pulse.
Specific embodiment
With reference to the accompanying drawing, technical solution of the present invention is described in detail.
Fig. 1 is three level carrier modulation SPWM driving principle figure in the same direction；The burst pulse machine that modulating wave near zero-crossing point generates
Reason is as shown in Figure 2；It is as shown in Figure 3 to modulate the burst pulse generated at crest value.
In order to achieve the above-mentioned object of the invention, the present invention provides following technical schemes:
Referring to Fig. 4, in the present embodiment, a kind of three-level inverter burst pulse suppressing method includes the following steps:
Step 1 determines the corresponding duty ratio of minimum pulse width, opens in conjunction with IGBT minimum, turn-off time and dead time, really
Determine the corresponding duty ratio of minimum pulse width.IGBT minimum is opened, closes short time and corresponding dead time with different manufacturers, different shaped
Number IGBT and the factors such as real work switching frequency it is different and different, minimum pulse width should carry out really according to IGBT actual condition
It is fixed.
1) in the step 1, minimum pulse width is that IGBT minimum opens Ton_min, turn-off time Toff_minWith dead time TdIt
With.
2) in the step 1, the corresponding duty ratio T of minimum pulse widthmin_dutyCalculation method are as follows:
In above formula, Ts is switch periods value.
Step 2 calculates voltage vector magnitude, and is compared with upper limit value, then repairs to vector magnitude greater than the upper limit
Positive clipping, the upper limit are that maximum duty cycle subtracts the corresponding duty ratio of minimum pulse width.
1) vector upper limit value Tmax=1-Tmin_duty；
2) modification method are as follows: if the per unit value of voltage vector magnitude is greater than vector upper limit value Tmax, to vector multiplied by arrow
Amount upper limit value Tmax is calculated as new vector magnitude.
Step 3 calculates three-level three-phase modulating wave duty ratio, calculates three according to three level SVPWMs or SPWM modulator approach
Phase modulating wave duty ratio.
Three-phase modulations wave duty ratio duty ratio corresponding with minimum pulse width is compared by step 4, and any phase modulating wave accounts for
The absolute value of empty ratio is less than the corresponding duty ratio of minimum pulse width, and the modulating wave duty ratio of the phase is assigned to intermediate variable temp,
Three-phase modulations wave duty ratio subtracts temp simultaneously, is inhibited to the burst pulse that three-phase modulations wave near zero-crossing point generates, is compensated.
Step 5 updates PWM register, and the absolute value of three-phase modulations wave duty ratio is greater than the corresponding duty ratio of burst pulse, then
Register is updated with actual duty ratio, the PWM register for otherwise corresponding to phase is reset.
It is a kind of for inhibiting the device of three-level inverter burst pulse, including DSP, CPLD and three IGBT referring to Fig. 5
Three parts of driving plate, wherein the output end of DSP is connected with the input terminal of CPLD, and the different output ends of CPLD are respectively connected to not
With the input terminal of IGBT driving board, specifically: 4 A phase output terminals of CPLD are respectively connected to A phase IGBT driving board, and the 4 of CPLD
A B phase output terminal is respectively connected to B phase IGBT driving board, and 4 C phase output terminals of CPLD are respectively connected to C phase IGBT driving board.
Wherein DSP generates three-phase inverter for calculating three-level inverter three-phase modulations wave duty ratio in real time respectively
IGBT driving signal, and it is transferred to CPLD；DSP selects TI company C2000 series of digital signals processor, such as
TMS320F28377。
DSP specifically includes four SPI module, EPWM module, ADC sampling module and computing module parts.
ADC sampling module realizes the sampling such as complete machine voltage, electric current.
SPI module realizes the real time communication of CPLD, obtains the dead time Td of CPLD superposition.
Computing module is for calculating the corresponding duty ratio of minimum pulse width；It is calculated according to signals such as real-time collection voltages, electric currents
Three-phase modulations wave duty ratio.
EPWM module generates 6 road pwm signals, exports to CPLD for updating PWM register.Update the specific of register
Process are as follows: when the absolute value of three-phase modulations wave duty ratio is greater than the corresponding duty ratio of minimum pulse width, then with the three-phase being calculated
Modulating wave duty ratio updates the PWM register of corresponding phase, and the PWM register for otherwise corresponding to phase is reset.
CPLD is superimposed dead time for negating respectively to the two-way driving signal of each phase received,
Corresponding tetra- road PWM drive signal of Xiang is generated, and PWM drive signal is transferred to IGBT driving board；CPLD selects Altera public
Department, MAX II series CPLD, such as EPM1270.
Three IGBT driving boards carry out level to the driving signal that CPLD is issued and turn according to the parameter of the IGBT of actual use
It changes, power amplification is to guarantee corresponding IGBT reliably working.
The specific work process of the device are as follows: the dead time that DSP is superimposed by obtaining CPLD calculates minimum pulse width pair
The duty ratio answered；Three-phase modulations wave duty ratio is calculated by signals such as real-time collection voltages, electric currents, to three-phase modulations wave duty ratio
Its internal 3 EPWM module is updated after carrying out burst pulse inhibition, generates 6 road PWM drive signals；CPLD is to each phase received
Two-way pwm signal negated respectively, while being superimposed dead time, each phase generates 4 road pwm signals；Three-phase IGBT driving
Plate carries out level conversion and power amplification to the driving signal that CPLD is sent, reliable to drive IGBT work.
Claims (10)
1. a kind of three-level inverter burst pulse suppressing method, which comprises the steps of:
Step 1 determines the corresponding duty ratio of the minimum pulse width of three-level inverter；
Step 2 calculates voltage vector magnitude, carries out marking change, then be compared with upper limit value: if the mark of voltage vector magnitude
Value is greater than upper limit value, then is modified clipping to voltage vector magnitude, and the upper limit value is that maximum duty cycle subtracts most scun
The corresponding duty ratio of width；It is not handled if the per unit value of voltage vector magnitude is less than or equal to upper limit value；
Step 3 calculates three-phase modulations wave duty ratio；
Step 4 is accounted for the absolute value for the three-phase modulations wave duty ratio that step 3 obtains is corresponding with the minimum pulse width that step 1 obtains
Empty ratio is compared:
If the absolute value of any phase modulating wave duty ratio is less than the corresponding duty ratio of minimum pulse width, by the modulating wave duty ratio of the phase
It is assigned to intermediate variable temp, three-phase modulations wave duty ratio subtracts temp simultaneously；
Step 5, update PWM register: when three-phase modulations wave duty ratio absolute value be greater than the corresponding duty ratio of minimum pulse width, then
The PWM register that corresponding phase is updated with the three-phase modulations wave duty ratio that step 4 is calculated suddenly, otherwise corresponds to the PWM register of phase
It resets.
2. a kind of three-level inverter burst pulse suppressing method according to claim 1, which is characterized in that the step 1
In, minimum pulse width be IGBT minimum service time Ton_min, turn-off time Toff_minWith dead time TdThe sum of.
3. a kind of three-level inverter burst pulse suppressing method according to claim 2, which is characterized in that IGBT minimum is opened
Logical, pass short time and corresponding dead time are with factors such as different manufacturers, the IGBT of different model and real work switching frequencies
Different and different, minimum pulse width is determined according to IGBT actual condition.
4. a kind of three-level inverter burst pulse suppressing method according to claim 1, which is characterized in that in step 1: most
The corresponding duty ratio T of small pulsewidthmin_dutyCalculation method are as follows:
In above formula, Ton_minFor IGBT minimum service time, Toff_minFor the turn-off time, Ts is switch periods value.
5. a kind of three-level inverter burst pulse suppressing method according to claim 1, which is characterized in that the step 2
Specific step is as follows:
1) vector upper limit value Tmax=1-Tmin_duty, Tmin_dutyFor the corresponding duty ratio of minimum pulse width；
2) modification method are as follows: if the per unit value of voltage vector magnitude is greater than Tmax, to vector multiplied by Tmax as new vector
Amplitude is calculated.
6. a kind of three-level inverter burst pulse suppressing method according to claim 1, which is characterized in that in step 3, root
Three-phase modulations wave duty ratio is calculated according to three level SVPWMs or SPWM modulator approach.
7. a kind of three-level inverter burst pulse inhibits device, which is characterized in that including DSP, CPLD and three IGBT drivings
Plate, wherein the output end of DSP is connected with the input terminal of CPLD, and the different output ends of CPLD are respectively connected to different IGBT driving boards
Input terminal, specifically: four A phase output terminals of CPLD are respectively connected to A phase IGBT driving board, and four B phases of CPLD export
End is respectively connected to B phase IGBT driving board, and four C phase output terminals of CPLD are respectively connected to C phase IGBT driving board.
8. a kind of three-level inverter burst pulse according to claim 7 inhibits device, which is characterized in that DSP is for real
When calculate three-level inverter three-phase modulations wave duty ratio, and export the IGBT driving signal of three-phase inverter respectively, and transmit
To CPLD；
CPLD is superimposed dead time for negating respectively to the two-way driving signal of each phase received, generates
Corresponding tetra- road PWM drive signal of Xiang, is transferred to IGBT driving board for PWM drive signal；
The driving signal that three-phase IGBT driving board is used to issue CPLD carries out level conversion and power amplification.
9. a kind of three-level inverter burst pulse according to claim 7 inhibits device, which is characterized in that wherein DSP packet
Include SPI module, EPWM modules A DC sampling module and computing module, the output end of the output end of ADC sampling module and CPLD with
The input terminal of computing module connects, and the input terminal of computing module is connected with the input terminal of EPWM module.
10. a kind of three-level inverter burst pulse according to claim 9 inhibits device, which is characterized in that ADC samples mould
Block is used for voltage and current sample；SPI module is used for and CPLD real time communication, the dead time Td of acquisition CPLD superposition；EPWM
Module generates 6 road pwm signals, exports to CPLD for updating PWM register；Computing module is corresponding for exporting minimum pulse width
Duty ratio, the collection voltages obtained according to ADC sampling module, electric current export three-phase modulations wave duty ratio.
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Cited By (11)
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| CN110829805A (en) * | 2019-11-27 | 2020-02-21 | 湖北师范大学 | Method and system for filtering narrow pulse of PWM driving signal of cascade converter |
| CN110855138A (en) * | 2019-10-25 | 2020-02-28 | 西安班特利奥能源科技有限公司 | Dead zone compensation method for three-level converter |
| CN111478613A (en) * | 2020-04-20 | 2020-07-31 | 上海正泰电源系统有限公司 | DSP implementation method for restraining inverter narrow pulse |
| CN111711346A (en) * | 2020-06-19 | 2020-09-25 | 漳州科华技术有限责任公司 | Drive signal updating method applied to switching tube control circuit and related device |
| CN113162448A (en) * | 2021-04-27 | 2021-07-23 | 深圳市能隙科技有限公司 | Three-level converter bus balance control method, device, equipment and medium |
| CN113242032A (en) * | 2021-05-13 | 2021-08-10 | 苏州英威腾电力电子有限公司 | Method, device, equipment and medium for determining minimum pulse width of PWM signal |
| CN113270996A (en) * | 2021-04-07 | 2021-08-17 | 中国第一汽车股份有限公司 | PWM modulation method for restraining narrow pulse |
| CN113938361A (en) * | 2021-09-03 | 2022-01-14 | 广东安朴电力技术有限公司 | Communication coding anti-interference method, system and storage medium |
| CN115411916A (en) * | 2021-05-27 | 2022-11-29 | 上海汽车电驱动有限公司 | Method, apparatus and medium for suppressing turn-off voltage spikes of controller power devices |
| WO2022247289A1 (en) * | 2021-05-28 | 2022-12-01 | 天津飞旋科技股份有限公司 | Narrow pulse suppression method and apparatus, and bridge switch circuit |
| WO2023246484A1 (en) * | 2022-06-23 | 2023-12-28 | 中国第一汽车股份有限公司 | Electric motor control method and apparatus, and vehicle |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855138A (en) * | 2019-10-25 | 2020-02-28 | 西安班特利奥能源科技有限公司 | Dead zone compensation method for three-level converter |
| CN110855138B (en) * | 2019-10-25 | 2021-08-03 | 西安班特利奥能源科技有限公司 | Dead zone compensation method for three-level converter |
| CN110829805A (en) * | 2019-11-27 | 2020-02-21 | 湖北师范大学 | Method and system for filtering narrow pulse of PWM driving signal of cascade converter |
| CN110829805B (en) * | 2019-11-27 | 2022-04-01 | 湖北师范大学 | Method and system for filtering narrow pulse of PWM driving signal of cascade converter |
| CN111478613A (en) * | 2020-04-20 | 2020-07-31 | 上海正泰电源系统有限公司 | DSP implementation method for restraining inverter narrow pulse |
| CN111711346A (en) * | 2020-06-19 | 2020-09-25 | 漳州科华技术有限责任公司 | Drive signal updating method applied to switching tube control circuit and related device |
| CN113270996A (en) * | 2021-04-07 | 2021-08-17 | 中国第一汽车股份有限公司 | PWM modulation method for restraining narrow pulse |
| WO2022213618A1 (en) * | 2021-04-07 | 2022-10-13 | 中国第一汽车股份有限公司 | Pwm method for suppressing narrow pulses |
| CN113270996B (en) * | 2021-04-07 | 2022-11-11 | 中国第一汽车股份有限公司 | PWM modulation method for restraining narrow pulse |
| CN113162448A (en) * | 2021-04-27 | 2021-07-23 | 深圳市能隙科技有限公司 | Three-level converter bus balance control method, device, equipment and medium |
| CN113162448B (en) * | 2021-04-27 | 2023-04-18 | 深圳市能隙科技有限公司 | Three-level converter bus balance control method, device, equipment and medium |
| CN113242032A (en) * | 2021-05-13 | 2021-08-10 | 苏州英威腾电力电子有限公司 | Method, device, equipment and medium for determining minimum pulse width of PWM signal |
| CN115411916A (en) * | 2021-05-27 | 2022-11-29 | 上海汽车电驱动有限公司 | Method, apparatus and medium for suppressing turn-off voltage spikes of controller power devices |
| WO2022247289A1 (en) * | 2021-05-28 | 2022-12-01 | 天津飞旋科技股份有限公司 | Narrow pulse suppression method and apparatus, and bridge switch circuit |
| CN113938361A (en) * | 2021-09-03 | 2022-01-14 | 广东安朴电力技术有限公司 | Communication coding anti-interference method, system and storage medium |
| CN113938361B (en) * | 2021-09-03 | 2024-04-16 | 广东安朴电力技术有限公司 | Communication coding anti-interference method, system and storage medium |
| WO2023246484A1 (en) * | 2022-06-23 | 2023-12-28 | 中国第一汽车股份有限公司 | Electric motor control method and apparatus, and vehicle |
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