CN110323257A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN110323257A CN110323257A CN201910293689.4A CN201910293689A CN110323257A CN 110323257 A CN110323257 A CN 110323257A CN 201910293689 A CN201910293689 A CN 201910293689A CN 110323257 A CN110323257 A CN 110323257A
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises: a substrate base plate; the display area comprises a first display area, and a notch is formed by the first edge towards the inner part of the array substrate along the first direction in a concave mode; the first display area comprises first sub-pixels, and the orthographic projection of at least one row of first sub-pixels in the first display area on the substrate and the orthographic projection of the peripheral circuit area on the substrate have an overlapping area; the shortest distance between the outer edges of the first sub-pixels of the two adjacent columns in the first display area in the first direction is D1; the second display area comprises second sub-pixels, the shortest distances between the outer edges of the second sub-pixels of two adjacent columns in the first direction are equal and are D2, wherein D1> D2. On the premise of ensuring that the number of pixel columns is not increased, the invention enables the orthographic projection part of the first sub-pixel at the gap area and the peripheral circuit area on the substrate to be overlapped, thereby being beneficial to the design of a narrow frame.
Description
Technical field
The present invention relates to field of display technology, more particularly, to a kind of array substrate, display panel and display device.
Background technique
With the development of electronic technology, display panel manufacture also tends to be mature, and the display panel that the prior art provides includes
Liquid crystal display panel, organic light emitting display panel, Plasmia indicating panel etc..In order to increase the display picture of display device and outer
The aesthetic feeling of sight, the screen accounting for improving display device are increasingly becoming a kind of development trend.Traditional display device, such as display,
The screen of television set, mobile phone, tablet computer etc. is usually the rectangle of rule.But with the development of science and technology, people are to aobvious
The demand of showing device screen is more and more diversified, and simple rectangle display device is no longer satisfied consumer demand, therefore,
The display device of various shapes is come into being.The shape for some display panels that the prior art provides is frequently designed to regular square
Shape other than shape, this kind of display panel are commonly known as special-shaped display panel, and special-shaped display panel can make display device
Design is presented in screen shape.
In addition, needing to be arranged in special-shaped display panel groove body based on the structure design shielded comprehensively to install camera, listen
Cylinder, inductor etc..But after setting groove body, groove body edge metal cabling will become very intensive, can make the coupling between cabling
It acts on larger, influences the exhibit stabilization of display panel.Increase the width between cabling to reduce coupling, and groove body can be made
The border width at place broadens.
Summary of the invention
In view of this, the present invention provides a kind of array substrate, display panel and display device, to solve groove body edge
The problem of metal routing intensive image exhibit stabilization.
On the one hand, the invention discloses a kind of array substrates, comprising:
Underlay substrate；
Viewing area and periphery circuit region, the viewing area include the first viewing area, and first viewing area includes the first side
Edge, the first edge form notch towards the array substrate inner recess along first direction；
First viewing area includes the first sub-pixel, in first viewing area, at least one column first sub-pixel
There is overlapping region with orthographic projection of the periphery circuit region on the underlay substrate in the orthographic projection on the underlay substrate；
The adjacent two column outer peripheral most short distance of the first sub-pixel in first viewing area in said first direction
From for D1；
The viewing area further includes the second viewing area, second viewing area in a first direction with first viewing area phase
Neighbour, second viewing area include the second sub-pixel, in said first direction adjacent two column the second sub-pixel outer edge
The shortest distance be equal, and be D2, wherein D1 > D2.
Optionally, the adjacent two column outer peripheral spacing of the first sub-pixel on first direction in first viewing area
It is gradually reduced.
Optionally, adjacent two column first sub-pixel is outer peripheral most short on first direction in first viewing area
Distance is gradually reduced with arithmetic progression.
Optionally, the viewing area further includes third viewing area, and two third viewing areas are distinguished in a second direction
Positioned at the two sides of the notch, and in this second direction first viewing area it is adjacent, in a first direction with described
Two viewing areas are adjacent, and the first direction and second direction intersection, the third viewing area includes third sub-pixel,
In,
In a first direction, the adjacent two column outer peripheral shortest distance of third sub-pixel is in the third viewing area
D3, wherein D3 > D2.
Optionally, in a first direction in the third viewing area at least one column third sub-pixel in the substrate base
Orthographic projection on plate has Chong Die with orthographic projection of the periphery circuit region on underlay substrate.
Optionally, the pixel includes first electrode, and the first electrode includes the first first electrode and the first second electrode,
In, first sub-pixel includes the first first electrode, and second sub-pixel includes the first second electrode, and the first first electrode exists
Frontal projected area on the underlay substrate is greater than frontal projected area of the first second electrode on the underlay substrate.
Optionally, the periphery circuit region of the indentation, there includes a plurality of connecting line, includes a plurality of in the third viewing area
The signal wire extended in a second direction；In a second direction positioned at the notch two sides, and it is located at described in two of same row
Signal wire is electrically connected by the connecting line, and the connecting line includes the first connecting line and the second connecting line, wherein described first
Connecting line and second connecting line are located at different film layers.
Optionally, orthographic projection of first connecting line on the underlay substrate and second connecting line are in the lining
Orthographic projection on substrate is least partially overlapped.
On the other hand, the present invention also provides a kind of display panels, including any of the above-described array substrate.
On the other hand, the present invention also provides a kind of display devices, including display panel described above.
Compared with prior art, array substrate provided by the invention, display panel and display device at least realize as follows
The utility model has the advantages that
Array substrate of the invention includes underlay substrate；Viewing area and periphery circuit region, the viewing area include first aobvious
Show area, first viewing area includes first edge, and the first edge is along first direction towards the array substrate inner-concave
It falls into and forms notch；First viewing area includes the first sub-pixel, in first viewing area, at least one column first sub- picture
Element has overlay region with orthographic projection of the periphery circuit region on the underlay substrate in the orthographic projection on the underlay substrate
Domain；The adjacent two column outer peripheral shortest distance of the first sub-pixel is in first viewing area in said first direction
D1；The viewing area further includes the second viewing area, and second viewing area is adjacent with first viewing area in a first direction, institute
Stating the second viewing area includes the second sub-pixel, and adjacent two column second sub-pixel is outer peripheral most short in said first direction
Distance is equal, and is D2, wherein D1 > D2.The present invention makes the first sub-pixel at relief area and periphery circuit region in substrate base
Orthographic projection on plate has overlapping region, and by changing the distance between adjacent two column, first sub-pixel in the first viewing area,
It is greater than the shortest distance between adjacent the first sub-pixel of two column between adjacent the second sub-pixel of two column in the second viewing area
The shortest distance not only can guarantee do not increase the columns of pixel in this way, but also is conducive to the design and implementation height of narrow frame and accounts for screen ratio.
Certainly, implementing any of the products of the present invention specific needs while must not reach all the above technical effect.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become apparent.
Detailed description of the invention
It is combined in the description and the attached drawing for constituting part of specification shows the embodiment of the present invention, and even
With its explanation together principle for explaining the present invention.
Fig. 1 is a kind of array substrate planar structure schematic diagram provided by the invention；
Fig. 2 is another array substrate planar structure schematic diagram provided by the invention；
Fig. 3 is the planar structure schematic diagram of another array substrate provided by the invention；
Fig. 4 is the planar structure schematic diagram of another array substrate provided by the invention；
Fig. 5 is the planar structure schematic diagram of another array substrate provided by the invention；
Fig. 6 is the planar structure schematic diagram of another array substrate provided by the invention；
Fig. 7 be in Fig. 6 A-A to sectional view；
Fig. 8 is B-B direction sectional view in Fig. 6；
Fig. 9 is the planar structure schematic diagram of another array substrate provided by the invention；
Figure 10 is C-C sectional view in Fig. 9；
Figure 11 is the planar structure schematic diagram of another array substrate provided by the invention；
Figure 12 is D-D sectional view in Figure 11；
Figure 13 is a kind of planar structure schematic diagram of display panel provided by the invention；
Figure 14 is a kind of planar structure schematic diagram of display device provided by the invention.
Specific embodiment
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the present invention
And its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, then in subsequent attached drawing does not need that it is further discussed.
The signal lead needs of the circuit region of gap edge in the prior art are walked around gap edge, gap edge area
Interior metal routing is very intensive, and the coupling between cabling is larger, affects the display effect of display panel.In order to reduce
Coupling increases the width between cabling in the prior art, so that gap edge sector width is become larger, is unfavorable for narrow frame design.
In order to solve this problem, it realizes narrow frame design, while reducing the work of the coupling between the intensive cabling of gap edge
With the invention proposes a kind of array substrates.About the embodiment of array substrate provided by the invention, it is discussed in detail below.
Referring to FIG. 1, Fig. 1 is a kind of array substrate planar structure schematic diagram provided by the invention；In Fig. 1, array substrate
100 include: underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02 include the first viewing area 04, and described the
One viewing area 04 includes first edge 05, and the first edge 05 is along first direction X towards 100 inner recess of array substrate
Form notch 06；First viewing area 04 includes the first sub-pixel 07, in first viewing area 04, a column first son
Pixel 07 is in the orthographic projection and orthographic projection of the periphery circuit region 03 on the underlay substrate 01 on the underlay substrate 01
With overlapping region, Fig. 1 only shows orthographic projection of first sub-pixel 07 on the underlay substrate 01 and the periphery circuit region
The 03 partly overlapping form of orthographic projection on the underlay substrate 01；First viewing area 04 on the first direction X
The interior adjacent two column outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area
08, X is adjacent with first viewing area 04 in a first direction for second viewing area 08, and second viewing area 08 includes second
Sub-pixel 09, the adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is
D2, wherein D1 > D2.Notch 06 in Fig. 1 only illustrates the side that array substrate is arranged in, and other positions can also be arranged in,
Here it is not specifically limited.The right side of array substrate can also be arranged in notch 06 in other optional embodiments of the invention
Side, the angle surrounding R or top.Second sub-pixel in the columns of first sub-pixel 07 and the second viewing area 08 in first viewing area 04
09 columns is only illustrative, and practical columns can be set according to actual needs.Underlay substrate 01 can be flexible substrates or
Person's non-flexible substrates.It can be understood that in addition to 04 He of the first viewing area in the viewing area 02 of 100 array substrate 100 of array substrate
Other than second viewing area 08, other parts are also again provided with sub-pixel, are not shown in Fig. 1.
In some alternative embodiments, referring to FIG. 2, Fig. 2 is another array substrate planar junction provided by the invention
Structure schematic diagram；In Fig. 2, array substrate 100 includes: underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02
Including the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X direction
100 inner recess of array substrate forms notch 06；First viewing area 04 includes the first sub-pixel 07, and described first is aobvious
Show in area 04, orthographic projection and the periphery circuit region 03 of two column first sub-pixels 07 on the underlay substrate 01 are in institute
The orthographic projection stated on underlay substrate 01 has overlapping region；On the first direction X adjacent two in first viewing area 04
Arranging the outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area 08, and described
X is adjacent with first viewing area 04 in a first direction for two viewing areas 08, and second viewing area 08 includes the second sub-pixel 09,
The adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2, wherein
D1>D2。
It is understood that Fig. 1 and Fig. 2 only illustrate orthographic projection of first sub-pixel 07 on underlay substrate 01 and week
Side circuit region 03 can also be certainly the case where the orthographic projection on the underlay substrate 01 has a column and two column overlapping regions
Three column or three column more than, can according to the actual situation depending on.Furthermore the shortest distance D1 between adjacent the first sub-pixel of two column 07
Can be equal, can also be unequal, as long as guaranteeing that D1 > D2 can be realized as realizing narrow side under the premise of not increasing pixel columns
Frame；This is because increase by 07 columns of the first sub-pixel, can make increased first sub-pixel 07 can not in third viewing area 10
Sub-pixel (not shown) is corresponding, and it is corresponding with the first sub-pixel 07 to need to increase data line, for for the first son
Pixel 07 transmits driving signal, and to will lead to limited space at notch 06 more crowded for the data line newly increased, and makes to make
It complicates as technique.
Array substrate provided by the invention, at least has the following technical effect that:
Array substrate 100 of the invention includes underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02
Including the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X direction
100 inner recess of array substrate forms notch 06；First viewing area 04 includes the first sub-pixel 07, and described first is aobvious
Show in area 04, orthographic projection and the periphery circuit region 03 of at least one column first sub-pixel 07 on the underlay substrate 01
Orthographic projection on the underlay substrate 01 has overlapping region；The phase in first viewing area 04 on the first direction X
It is D1 that neighbour two, which arranges the outer peripheral shortest distance of first sub-pixel 07,；The viewing area 02 further includes the second viewing area 08, institute
Stating the second viewing area 08, X is adjacent with first viewing area 04 in a first direction, and second viewing area 08 includes the second sub- picture
Element 09, the adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2,
Wherein, D1 > D2, it should be noted that display panel further includes pixel defining layer, and pixel defining layer includes multiple open regions (figure
In be not shown), the second sub-pixel 09 is located at the open region of pixel defining layer, wherein the outer edge of the second sub-pixel 09 be second
The edge of the corresponding pixel defining layer open region of sub-pixel 09.The present invention makes the first sub-pixel 07 and periphery electricity at 06th area of notch
Orthographic projection of the road area 03 on underlay substrate 01 has overlapping region, and by changing adjacent two column first in the first viewing area 04
The distance between sub-pixel 07 makes the shortest distance between adjacent the first sub-pixel of two column 07 be greater than the phase in the second viewing area 08
The shortest distance between adjacent two the second sub-pixels of column 09, not only can guarantee the columns for not increasing pixel, but also be conducive to narrow frame in this way
Design and Gao Zhanping ratio.
Optionally, referring to FIG. 3, Fig. 3 is the planar structure schematic diagram of another array substrate provided by the invention；Institute
It states in the first viewing area 04 the adjacent two column outer peripheral spacing of first sub-pixel 07 on first direction X to be gradually reduced, i.e. D11
> ... > D1n.
In Fig. 3, array substrate 100 includes underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02 are wrapped
Include the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X towards institute
It states 100 inner recess of array substrate and forms notch 06；First viewing area 04 includes the first sub-pixel 07, first display
In area 04, orthographic projection of column first sub-pixel 07 on the underlay substrate 01 is with the periphery circuit region 03 described
Orthographic projection on underlay substrate 01 has overlapping region；Adjacent two column in first viewing area 04 on the first direction X
The outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area 08, and described second
X is adjacent with first viewing area 04 in a first direction for viewing area 08, and second viewing area 08 includes the second sub-pixel 09,
The adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2, wherein and D1 >
D2.The present invention makes the first sub-pixel 07 at 06th area of notch have weight with orthographic projection of the periphery circuit region 03 on underlay substrate 01
Folded region, and by changing the distance between adjacent two column, first sub-pixel 07 in the first viewing area 04, make adjacent two column first
The shortest distance between sub-pixel 07 is greater than the shortest distance between adjacent the second sub-pixel of two column 09 in the second viewing area 08,
It not only can guarantee the columns for not increasing pixel in this way, but also be conducive to the design and high screen accounting of narrow frame, display brightness is made to become uniform.
By being gradually reduced the outer peripheral spacing of adjacent first sub-pixel 07 in the first viewing area 04, display effect is more preferable, and
There is first sub-pixel of column 07 in the top of periphery circuit region 03 in first viewing area 04, is conducive to the design of narrow frame.
Optionally, with continued reference to FIG. 3, in first viewing area 04 on first direction X it is adjacent two column described first
The outer peripheral shortest distance of sub-pixel 07 is gradually reduced with arithmetic progression, i.e. D1n=D11+ (n-1) × d, and wherein d is constant.
The present invention makes the first sub-pixel 07 and orthographic projection of the periphery circuit region 03 on underlay substrate 01 at 06th area of notch
With overlapping region, and by changing the distance between adjacent two column, first sub-pixel 07 in the first viewing area 04, make adjacent two
The shortest distance between the first sub-pixel of column 07 is greater than between adjacent the second sub-pixel of two column 09 in the second viewing area 08 most
Short distance not only can guarantee the columns for not increasing pixel in this way, but also be conducive to the design and high screen accounting of narrow frame.By making first
The outer peripheral shortest distance of adjacent the first sub-pixel of two column 07 is gradually reduced on first direction X in viewing area 04, and be with
Arithmetic progression is gradually reduced, and changes the shortest distance between adjacent the first sub-pixel of two column 07 in the first viewing area 04 more equal
It is even, it is conducive to promote display effect, it is more preferable to make.And at least column first sub-pixel 07 is in underlay substrate in the first viewing area 04
Orthographic projection and orthographic projection of the periphery circuit region 03 on underlay substrate 01 on 01 have overlapping region.Dot structure is at least partly
The design for covering frame cabling increases the area of viewing area on display panel, to realize the design of narrow frame.
Optionally, referring to FIG. 4, Fig. 4 is the planar structure schematic diagram of another array substrate provided by the invention；Fig. 4
In, the viewing area 02 further includes third viewing area 10, and two third viewing areas 10 are located at institute on second direction Y
State the two sides of notch 06, and on the second direction Y first viewing area 04 it is adjacent, in a first direction on X with described
Two viewing areas 08 are adjacent, and the first direction X and second direction Y intersection, the third viewing area 10 includes third picture
Element 11, wherein in a first direction on X, the adjacent two column third sub-pixel 11 is outer peripheral most in the third viewing area 10
Short distance is D3, wherein D3 > D2.
In Fig. 4, array substrate 100 includes underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02 are wrapped
Include the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X towards institute
It states 100 inner recess of array substrate and forms notch 06；First viewing area 04 includes the first sub-pixel 07, first display
In area 04, orthographic projection of column first sub-pixel 07 on the underlay substrate 01 is with the periphery circuit region 03 described
Orthographic projection on underlay substrate 01 has overlapping region；Adjacent two column in first viewing area 04 on the first direction X
The outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area 08, and described second
X is adjacent with first viewing area 04 in a first direction for viewing area 08, and second viewing area 08 includes the second sub-pixel 09,
The adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2, wherein and D1 >
D2.For the present invention by setting third viewing area 10, third viewing area 10 is adjacent with the first viewing area 04 and the second viewing area 08, the
Third pixel 11 is set in three viewing areas 10, is conducive to promote display effect.Two column of third viewing area 10 are only illustrated in Fig. 4
The columns of third sub-pixel 11, third sub-pixel 11 is set according to the actual situation.
Optionally, referring to FIG. 5, Fig. 5 is the planar structure schematic diagram of another array substrate provided by the invention；This hair
In bright in a first direction on X in the third viewing area 10 at least one column third sub-pixel 11 on the underlay substrate 01
The orthographic projection on underlay substrate 01 of orthographic projection and the periphery circuit region 03 have it is Chong Die.
In Fig. 5, array substrate 100 includes underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02 are wrapped
Include the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X towards institute
It states 100 inner recess of array substrate and forms notch 06；First viewing area 04 includes the first sub-pixel 07, first display
In area 04, orthographic projection of column first sub-pixel 07 on the underlay substrate 01 is with the periphery circuit region 03 described
Orthographic projection on underlay substrate 01 has overlapping region；Adjacent two column in first viewing area 04 on the first direction X
The outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area 08, and described second
X is adjacent with first viewing area 04 in a first direction for viewing area 08, and second viewing area 08 includes the second sub-pixel 09,
The adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2, wherein and D1 >
D2.The viewing area 02 further includes third viewing area 10, and two third viewing areas 10 are located at institute on second direction Y
State the two sides of notch 06, and on the second direction Y first viewing area 04 it is adjacent, in a first direction on X with described
Two viewing areas 08 are adjacent, and the first direction X and second direction Y intersection, the third viewing area 10 includes third picture
Element 11, wherein in a first direction on X, the adjacent two column third sub-pixel 11 is outer peripheral most in the third viewing area 10
Short distance is D3, wherein D3 > D2.Only being shown in third viewing area 10 in Fig. 5 has a column third sub-pixel 11 in the lining
Orthographic projection on substrate 01 has Chong Die with orthographic projection of the periphery circuit region 03 on underlay substrate 01.
It is to be appreciated that can also have two column or the third pixel 11 arranged greater than two in the lining in third viewing area 10
Orthographic projection on substrate 01 have with orthographic projection of the periphery circuit region 03 on underlay substrate 01 it is Chong Die, as long as D3 > D2.
In this way can guarantee third viewing area 10 in 11 columns of third pixel it is constant in the case where, raising account for screen ratio, display effect is good.
Optionally, Fig. 6, Fig. 7 and Fig. 8 are please referred to, Fig. 6 is that the planar structure of another array substrate provided by the invention is shown
It is intended to；Fig. 7 be in Fig. 6 A-A to sectional view；Fig. 8 is B-B direction sectional view in Fig. 6；The pixel includes first electrode 30, described
First electrode 30 includes the first first electrode 12 and the first second electrode 13, wherein first sub-pixel 07 includes the first first electrode
12, second sub-pixel 09 includes the first second electrode 13, positive throwing of the first first electrode 12 on the underlay substrate 01
Shadow area is greater than frontal projected area of the first second electrode 13 on the underlay substrate 01.
Referring to figs. 7 and 8, it is possible to understand that be array substrate include underlay substrate 01, buffer layer 14, gate insulating layer 15,
Interlayer insulating film 16, passivation layer 17, planarization layer 18, thin film transistor (TFT) TFT19, pixel defining layer 20, first electrode 30 (12 or
13), luminescent layer 22 and second electrode 23.
Underlay substrate 01 can be flexible substrates or non-flexible substrates.When for flexible substrates, flexible substrates can be by
It is formed with any appropriate insulating materials flexible.For example, flexible substrates can be by such as polyimides, polycarbonate, poly-
Ether sulfone, polyethylene terephthalate, equal (ethylene naphthalate), polyarylate or fiberglass reinforced plastics etc.
Polymer material is formed.Flexible substrates can be transparent, translucent or opaque.
Buffer layer 14 is located on underlay substrate 01, and buffer layer 14 covers the entire upper surface of underlay substrate 01.Buffer layer 14
It may include inorganic layer or organic layer.For example, buffer layer 14 can be by such as silica, silicon nitride, silicon oxynitride, aluminium oxide
The material shape either selected in the organic material of the inorganic material or acrylic of aluminium oxide etc., polyimides or polyester etc.
At.Buffer layer 14 may include single layer or multiple layers.Buffer layer stops oxygen and moisture, prevents moisture or magazine from passing through substrate base
Plate 01 is spread, and provides flat surface on 01 upper surface of underlay substrate.
Thin film transistor (TFT) TFT 19 is located on buffer layer 14, and the semiconductor including being located on buffer layer 14 has edge layer, partly leads
Body active layer includes the source region and drain region formed by doped N-type foreign ion or p type impurity ion, in source electrode
Region between region and drain region is the channel region of impurity of wherein undoping.
Gate insulating layer 15 includes such as inorganic layer of silica, silicon nitride or metal oxide, and may include list
Layer or multiple layers.Gate electrode is located in the specific region on gate insulating layer 15, gate electrode may include gold, silver, copper, nickel, platinum,
Palladium, aluminium, molybdenum or chromium single-layer or multi-layer.
Interlayer insulating film 16 is located on gate electrode.Interlayer insulating film 16 can be by the insulating inorganic of silicon oxide or silicon nitride etc.
Layer is formed.
Source electrode and drain electrode is located at 16 on interlayer insulating film.
Passivation layer 17 is located in source electrode and drain electrode, and passivation layer 17 can be by the inorganic layer shape of silicon oxide or silicon nitride etc.
It is formed at or by organic layer.
Planarization layer 18 is located at 17 on passivation layer.Planarization layer 18 includes acrylic, polyester-imide or benzocyclobutene etc.
Organic layer.
Organic luminescent device OLED is shown in Fig. 7 and Fig. 8 to be formed on thin film transistor (TFT) TFT 19.It is organic in order to be formed
Luminescent device OLED, first electrode 30 (anode) are electrically connected (or combination) by contact hole and cross drain electrode to source electrode.
First electrode 30 is used as anode and can be by various conductive material row.For example, first electrode 30 can be according to his
Purposes is formed as transparent or reflective electrode.When first electrode 30 is formed as transparent electrode, first electrode 30 may include
Tin indium oxide, indium zinc oxide, zinc oxide or indium oxide etc., when first electrode 30 is formed as reflecting electrode, reflecting layer can be by
Silver, magnesium, aluminium, platinum, gold, nickel chromium triangle or their mixture are formed.
Pixel defining layer 20 is located at the edge that first electrode 30 is covered on planarization layer 18.Pixel defining layer 20 can be by
The organic material of polyimides, polyamide, benzocyclobutene, acryl resin or phenolic resin etc. is formed.
Luminescent layer 22 is located in first electrode 30, this part for being provided with luminescent layer 22 of first electrode 30 not by
Pixel defining layer 20 covers and is exposed.Luminescent layer 22 can be formed by gas-phase deposition, and luminescent layer 22 is patterned
It is corresponding and corresponding with patterned first electrodes 30 for each sub-pixel.Luminescent layer 22 can by low molecular weight organic material or
The organic material of high molecular weight is formed.
Second electrode 23 (cathode as organic luminescent device OLED) is located on luminescent layer 22.With 30 phase of first electrode
Seemingly, second electrode 23 can be formed as transparent or reflective electrode.
In Fig. 6, array substrate 100 includes: underlay substrate 01；Viewing area 02 and periphery circuit region 03, the viewing area 02
Including the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X direction
100 inner recess of array substrate forms notch 06；First viewing area 04 includes the first sub-pixel 07, and described first is aobvious
Show in area 04, orthographic projection and the periphery circuit region 03 of column first sub-pixel 07 on the underlay substrate 01 are in institute
The orthographic projection stated on underlay substrate 01 has overlapping region；On the first direction X adjacent two in first viewing area 04
Arranging the outer peripheral shortest distance of first sub-pixel 07 is D1；The viewing area 02 further includes the second viewing area 08, and described
X is adjacent with first viewing area 04 in a first direction for two viewing areas 08, and second viewing area 08 includes the second sub-pixel 09,
The adjacent two column outer peripheral shortest distance of second sub-pixel 09 is equal on the first direction X, and is D2, wherein
D1>D2.The present invention make the first sub-pixel 07 at the first notch 06 and periphery circuit region 03 on underlay substrate 01 orthographic projection
With overlapping region, the distance between first sub-pixel of each column 07 is caused to change, while distance changes, the first first
Distance is no longer consistent between electrode 12 (anode) and the first second electrode 13 (anode), D1 > D2, i.e. the first first electrode 12 and film
Distance is greater than distance between the first second electrode 13 and the via hole of thin film transistor (TFT) TFT 19 between the via hole of transistor TFT 19, and
And after D1 > D2, have space that 12 area of the first first electrode is made to become larger, then the first first electrode 12 on underlay substrate 01 positive throwing
Shadow area be greater than the first second electrode 13 on underlay substrate 01 frontal projected area, Sa > Sc.Due to the face of the first first electrode 13
Product becomes larger, therefore the current density of corresponding sub-pixel becomes smaller, so that the service life is improved, this is because J=I/S, J are that electric current is close
Degree, I are current value, S is two-plate positive area；The life formula of display panel are as follows:L0For
Initial lifetime, t are the time, J is current density, τ is time constant, L (t) is t time lifetime；Becoming larger for area causes electric current close
The reduction of degree, the reduction of current density increase the display panel service life.The distance between optional first first electrode 12 can edge
First direction X every 1 μm/2 μm/3 μm by successively decreasing, until being decremented to the distance between first sub-pixel of pixel 07 and the second sub- picture
The distance between element 09 is consistent, improves the uniformity of display panel display brightness.
Optionally, Fig. 9 and Figure 10 are please referred to, Fig. 9 is the planar structure signal of another array substrate provided by the invention
Figure；Figure 10 is C-C sectional view in Fig. 9；Pixel in figure is not shown；The periphery electricity at the notch 06 is only illustrated in Fig. 9
Road area 03 includes 4 connecting lines, includes 4 signal wires 27 that Y extends in a second direction in the third viewing area 10；Second
Positioned at 06 two sides of notch on the Y of direction, and two signal wires 27 for being located at same row pass through 28 electricity of connecting line
Connection, the connecting line 28 include the first connecting line 28a and the second connecting line 28b, wherein the first connecting line 28a and institute
It states the second connecting line 28b and is located at different film layers.
Array substrate 100 includes: underlay substrate 01 in Fig. 9；Viewing area 02 and periphery circuit region 03, the viewing area 02 are wrapped
Include the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X towards institute
It states 100 inner recess of array substrate and forms notch 06；The viewing area 02 further includes the second viewing area 08, second viewing area
08 in a first direction X it is adjacent with first viewing area 04；The viewing area 02 further includes third viewing area 10, and two described
Three viewing areas 10 are located at the two sides of the notch 06 on second direction Y, and described first aobvious on the second direction Y
Show that area 04 is adjacent, the first direction X and the second direction Y phase adjacent with second viewing area 08 on X in a first direction
It hands over；Sub-pixel in Fig. 9 is not shown.The item number of data line 27 is only schematical in third viewing area 10 in Fig. 9, real data
27 numbers of line can according to the actual situation depending at notch 06 the item number of 03 connection wire 28 of periphery circuit region be also it is schematical, it is real
28 numbers of border connecting line can according to the actual situation depending on.In Figure 10, by by the first connecting line 28a and the second connecting line 28b not
Overlapping setting is completely coincident in different interlayer insulating films, the coupling between connecting line 28 can be greatly reduced, is improved
The stability of display, keeps the display effect more preferable.Since the first sub-pixel 07 is to the top of periphery circuit region 03 at 06 edge of notch
Mobile, the cabling comparatively dense of periphery circuit region 03, first electrode 30 and 03 cabling of periphery circuit region form overlap capacitance, therefore meeting
There is biggish crosstalk, influence display effect, the first connecting line 28a and the second connecting line 28b are not exclusively overlapped overlapping setting
In different interlayer insulating films, the display effect of the pixel of overlapping region is alleviated.
Optionally, Figure 11 and Figure 12 are please referred to, Figure 11 is that the planar structure of another array substrate provided by the invention is shown
It is intended to；Figure 12 is D-D sectional view in Figure 11；Pixel in figure is not shown；The first connecting line 28a is in the underlay substrate 01
On orthographic projection and orthographic projection of the second connecting line 28b on the underlay substrate 01 it is least partially overlapped.
Array substrate 100 includes: underlay substrate 01 in Figure 11；Viewing area 02 and periphery circuit region 03, the viewing area 02
Including the first viewing area 04, first viewing area 04 includes first edge 05, and the first edge 05 is along first direction X direction
100 inner recess of array substrate forms notch 06；The viewing area 02 further includes the second viewing area 08, second display
X is adjacent with first viewing area 04 in a first direction in area 08；The viewing area 02 further includes third viewing area 10, described in two
Third viewing area 10 is located at the two sides of the notch 06 on second direction Y, and described first on the second direction Y
Viewing area 04 is adjacent, the first direction X and the second direction Y adjacent with second viewing area 08 on X in a first direction
Intersection；Sub-pixel in Figure 11 is not shown.The item number of data line 27 is only schematical in third viewing area 10 in Figure 11, practical
27 numbers of data line can according to the actual situation depending at notch 06 the item number of 03 connection wire 28 of periphery circuit region be also schematic
, 28 numbers of practical connecting line can according to the actual situation depending on.Figure 11 and Figure 12 shows that the first connecting line 28a and second connects
Wiring is the case where the orthographic projection on underlay substrate 01 is completely coincident.First connecting line 28a interlocks two-by-two with the second connecting line 28b
It is divided into different interlayer insulating films, is completely cut off by insulating layer, the coupling between connecting line is reduced, exhibit stabilization increases
By force.First connecting line 28a and orthographic projection of second connecting line on underlay substrate 01 are least partially overlapped, make walking at notch 06
Line spacing becomes smaller, and is conducive to the design of narrow frame.
In other optional embodiments of the invention, the first connecting line 28a and the second connecting line are on underlay substrate 01
Orthographic projection can also partially overlap.
In some preferred embodiments, the first connecting line 28a can be with interlaced arrangement in different films from the second connecting line 28b
Layer, and the orthographic projection on underlay substrate 01 partly overlaps, and is conducive to the design of narrow frame in this way, and is conducive to reduce and connect
Coupling between wiring 28 improves exhibit stabilization.
Based on same invention thought, the present invention also provides a kind of display panels, including any of the above-described embodiment of the present invention
The array substrate of offer.
Figure 13 is please referred to, Figure 13 is a kind of planar structure schematic diagram of display panel provided by the invention.What Figure 13 was provided
Display panel 200 includes the array substrate 100 that any of the above-described embodiment of the present invention provides, and is provided in array substrate 100 thin
Film encapsulated layer (not shown), the thin-film encapsulation layer include organic packing layer and inorganic encapsulated layer, organic encapsulation layer and nothing
Machine encapsulated layer is alternately stacked into array substrate 100.Thin-film encapsulation layer can protect array substrate 100 from outside moisture and oxygen
Deng influence, play the role of protect array substrate 100.
Based on same invention thought, the present invention also provides a kind of display devices, provide including the above embodiment of the present invention
Display panel.
Figure 14 is please referred to, Figure 14 is a kind of planar structure schematic diagram of display device provided by the invention.What Figure 14 was provided
Display device 300 includes the display panel 200 that the above embodiment of the present invention provides.
Figure 14 embodiment only takes the mobile phone as an example, and is illustrated to display device, it is to be understood that the embodiment of the present invention mentions
The display device 300 of confession can be other display devices 300 having a display function such as computer, TV, display device for mounting on vehicle,
Present invention comparison is not specifically limited.Display device 300 provided by the invention, with display panel 200 provided by the invention
Beneficial effect, with specific reference to above-described embodiment illustrating for display panel 200, details are not described herein for the present embodiment.
Through the foregoing embodiment it is found that array substrate provided by the invention, display panel and display device, at least realize
It is following the utility model has the advantages that
Array substrate of the invention includes underlay substrate；Viewing area and periphery circuit region, the viewing area include first aobvious
Show area, first viewing area includes first edge, and the first edge is along first direction towards the array substrate inner-concave
It falls into and forms notch；First viewing area includes the first sub-pixel, in first viewing area, at least one column first sub- picture
Element has overlay region with orthographic projection of the periphery circuit region on the underlay substrate in the orthographic projection on the underlay substrate
Domain；The adjacent two column outer peripheral shortest distance of the first sub-pixel is in first viewing area in said first direction
D1；The viewing area further includes the second viewing area, and second viewing area is adjacent with first viewing area in a first direction, institute
Stating the second viewing area includes the second sub-pixel, and adjacent two column second sub-pixel is outer peripheral most short in said first direction
Distance is equal, and is D2, wherein D1 > D2.The present invention makes the first sub-pixel at relief area and periphery circuit region in substrate base
Orthographic projection on plate has overlapping region, and by changing the distance between adjacent two column, first sub-pixel in the first viewing area,
It is greater than the shortest distance between adjacent the first sub-pixel of two column between adjacent the second sub-pixel of two column in the second viewing area
The shortest distance not only can guarantee do not increase the columns of pixel in this way, but also is conducive to the design and implementation height of narrow frame and accounts for screen ratio.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that example above merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (10)
1. a kind of array substrate characterized by comprising
Underlay substrate；
Viewing area and periphery circuit region, the viewing area include the first viewing area, and first viewing area includes first edge, institute
It states first edge and forms notch towards the array substrate inner recess along first direction；
First viewing area includes the first sub-pixel, and in first viewing area, at least one column first sub-pixel is in institute
The orthographic projection and orthographic projection of the periphery circuit region on the underlay substrate stated on underlay substrate have overlapping region；
The adjacent two column outer peripheral shortest distance of the first sub-pixel is in first viewing area in said first direction
D1；
The viewing area further includes the second viewing area, and second viewing area is adjacent with first viewing area in a first direction,
Second viewing area includes the second sub-pixel, and adjacent two column second sub-pixel is outer peripheral most in said first direction
Short distance is equal, and is D2, wherein D1 > D2.
2. array substrate according to claim 1, which is characterized in that adjacent on first direction in first viewing area
The two column outer peripheral spacing of the first sub-pixel are gradually reduced.
3. array substrate according to claim 2, which is characterized in that adjacent on first direction in first viewing area
The two column outer peripheral shortest distances of the first sub-pixel are gradually reduced with arithmetic progression.
4. array substrate according to claim 1, which is characterized in that the viewing area further includes third viewing area, and two
The third viewing area is located at the two sides of the notch in a second direction, and described first shows in this second direction
Show that area is adjacent, adjacent with second viewing area in a first direction, the first direction and second direction intersection are described
Third viewing area includes third sub-pixel, wherein
In a first direction, the adjacent two column outer peripheral shortest distance of third sub-pixel is D3 in the third viewing area,
Wherein D3 > D2.
5. array substrate according to claim 4, which is characterized in that in a first direction in the third viewing area at least
Orthographic projection and the periphery circuit region positive throwing on underlay substrate of the one column third sub-pixel on the underlay substrate
Shadow has overlapping.
6. array substrate according to claim 1, which is characterized in that the pixel includes first electrode, first electricity
Pole includes the first first electrode and the first second electrode, wherein first sub-pixel includes the first first electrode, second sub-pixel
Including the first second electrode, frontal projected area of the first first electrode on the underlay substrate is greater than the first second electrode and exists
Frontal projected area on the underlay substrate.
7. array substrate according to claim 4, which is characterized in that the periphery circuit region of the indentation, there includes a plurality of company
Wiring includes a plurality of signal wire extended in a second direction in the third viewing area；It is located at the notch in a second direction
Two sides, and two signal wires for being located at same row are electrically connected by the connecting line, the connecting line includes the first company
Wiring and the second connecting line, wherein first connecting line and second connecting line are located at different film layers.
8. array substrate according to claim 7, which is characterized in that first connecting line is on the underlay substrate
Orthographic projection and orthographic projection of second connecting line on the underlay substrate are least partially overlapped.
9. a kind of display panel, including any array substrate of claim 1-8.
10. a kind of display device, which is characterized in that including display panel as claimed in claim 9.
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