CN110321312A - Reduce the coupled noise and power noise on PAM-4 I/O interface - Google Patents
Reduce the coupled noise and power noise on PAM-4 I/O interface Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
Disclosed herein is the technologies of the coupled noise and power noise that reduce on PAM-4 I/O interface, the method for specifically disclosing operation serial data bus, volume of data position is divided into one or more sequences, and by sequential coding be N grades of symbols, then transmitted in multiple discrete voltage levels.These methods can be used to communicate on serial data line, to improve bandwidth, and reduce crosstalk and other noise sources.
Description
Background technique
Modern high throughput systems in computing unit, memory device and are deposited using multiple high bandwidth input/output interfaces
Signaling network is formed between storage device.For example, multiple peripheral units are connected to centre by peripheral component interconnection high speed (PCI-E)
Manage unit (CPU) and graphics processing unit (GPU).These interfaces may include that multiple serial datas for running in high frequency are total
Line.
Pulse amplitude modulation (PAM) can be used for multi-channel serial data/address bus, with by by data encoding be different electricity
Voltage level carrys out the multiple data bit of simultaneous transmission.Here " channel " refers to the solid wire of serial data bus." data burst
(data burst) " refers to be placed in the data channel of serial data bus with identical bus clock interval (i.e. parallel)
Position.
One example of PAM communication is PAM-4.In each bus clock interim, PAM-4 is in serial data bus
Two bits (00,01,10,11) are encoded to one of four different voltages level (symbol) in each data channel.Due to
Two are encoded into each bus clock interval in each data channel, thus on serial data bus with comparable
Traditional second level (for example, PAM-2) signaling of Bus Clock Rate operation is compared, and PAM-4 may be implemented two in the ideal case
Bandwidth again.PAM-4 symbol uses four kinds of different voltage levels, therefore, compared with PAM-2, in PAM-4 between value of symbol
Voltage level difference is smaller.This makes PAM-4 communicate the influence for the effect that is easier to be interfered, such as counts on serial data bus
According to the coupled noise and power supply noise between channel, which reduce signal-to-noise ratio (SNR).
A kind of mechanism for mitigating these influence of noises is to utilize data bus inversion (DBI).For given data burst,
DBI passes through the polarity that the position on serial data bus in each data burst is intelligently arranged, by the data of serial data bus
The total size of voltage level conversion on channel reduces up to half.The metadata position that DBI needs each data burst additional
Data burst polarity setting (non-return data burst or reverse data burst) is transferred to receiver.This metadata position is logical
It is transmitted in the separated additional lines of the data channel (usual each data channel is also a line) of Chang Yu serial data bus.
Many serial data bus only include the individual data channel between transmitters and receivers.Therefore, addition is additional
Metadata route can cause in the number of, lines needed for serial data bus generate up to 100% expense.
The brief description of several views in attached drawing
For the ease of identifying discussion to any element-specific or movement, one of most significant bit or more in Ref. No.
Multiple numbers refer to the figure number for introducing the element for the first time.
Fig. 1 instantiates the data communication system 100 according to one embodiment.
Fig. 2 instantiates the embodiment of PAM-4 transceiver 200.
Fig. 3 instantiates an embodiment of conventional PAM-4 data channel voltage waveform 300.
Fig. 4 instantiates the PAM-433 encoder 400 according to one embodiment.
Fig. 5 instantiates an embodiment of PAM-433 data channel voltage waveform 500.
Fig. 6 instantiates an embodiment of data channel voltage waveform 600.
Fig. 7 instantiates an embodiment of data channel voltage waveform 700.
Fig. 8 instantiates an embodiment of data channel voltage waveform 800.
Fig. 9 instantiates an embodiment of data channel voltage waveform 900.
Figure 10 instantiates an embodiment of PAM-433 routine 1000.
Figure 11 instantiates an embodiment of PAM-N routine 1100.
Figure 12 instantiates an embodiment of PAM-4433 coding 1200.
Figure 13 instantiates an embodiment of PAM-4433 routine 1300.
Figure 14 instantiates an embodiment of variable PAM-433 coding 1400.
Figure 15 instantiates an embodiment of variable PAM-433 routine 1500.
Figure 16 be include GPU computing system 1600 block diagram, aspect of the invention can be effected or carried out wherein.
Detailed description
Referring to Fig.1, the sending device of data communication system 100 including such as data processor 102 etc, at the data
Managing device 102 includes processing core 114, PAM-4 symbol encoder 104 and PAM-4 transmitter 108.In some embodiments, data
Processor 102 may include graphics processing unit (GPU), central processing unit (CPU), system on chip (SoC) or other many institutes
Known data processing equipment.
Data processor 102 in such as bus of memory bus 118 etc with the reception of such as memory 112 etc
Device communication.PAM-4 receiver 110 and PAM-4 symbol decoder 106 are received and are handled in memory bus 118 from data
Processor 102 is transmitted to the PAM-4 signal of memory 112.
Data processor 102 using internal data bus 116 come by multi-channel internal data/address bus 116 to processing core
114 transmit and transmit data burst from processing core 114.PAM-4 symbol encoder 104 receives the number to be encoded from processing core 114
PAM-4 coding is executed according to burst, and to the data burst.PAM-4 transmitter 108 passes through memory bus 118 for the number of coding
PAM-4 receiver 110 is sent to according to burst.PAM-4 receiver 110 receives the data burst of coding, and the data of coding are dashed forward
PAM-4 symbol decoder 106 is sent to be decoded to the data burst.Once decoding, data burst, which is sent to, to be deposited
Reservoir 112.
This is simplified flow chart.In practice, usually there are encoder and decoding at the both ends of memory bus 118
Device, for reading and writing memory 112 from memory 112.
Fig. 2 instantiates the PAM-4 transceiver for the individual data channel of serial data bus in one embodiment
200.The PAM-4 transceiver 200 includes least significant bit transmitter 202, most significant bit transmitter 204,206 and of receiver
Data channel 208.PAM-4 transceiver 200 is using least significant bit transmitter 202 and most significant bit transmitter 204 in data
Level Four symbol is generated on channel 208.Here term " symbol " refers to by line driver in serial data bus data channel
The voltage level of generation, wherein voltage level indicates the value of one or more data bit.Therefore, " coded identification " means object
The line drive circuit of reason ground configuration serial data bus, by the voltage driving in data channel to particular value.
For example, least significant bit transmitter 202 and highest have if the two bits being encoded into symbol are (1,1)
The output of effect position transmitter 204 is combined to generate the voltage of such as 1.2V in data channel 208, and due to receiver
The Rt that pulls up transistor (both ends of data channel 208 are on same potential) on 206, the electric current in data channel 208 are for example
0mA.If two data being encoded in symbol are (1,0), least significant bit transmitter 202 and most significant bit are sent
The output of device 204 is combined to generate the voltage of for example, 1.0V, and the electricity in data channel 208 in data channel 208
Stream is such as 5mA.If two data being encoded in symbol are (0,1), least significant bit transmitter 202 and highest have
The output of effect position transmitter 204 is combined to generate the voltage of for example, 0.8V, and data channel in data channel 208
Electric current on 208 is such as 10mA.If two data being encoded in symbol are (0,0), least significant bit transmitter
202 and most significant bit transmitter 204 output be combined in data channel 208 generate for example, 0.6V voltage, and
And the electric current in data channel 208 is such as 15mA.0.6V is properly termed as transmitting voltage V substantially hereinb, other symbol voltages
Level can transmit voltage substantially from this and carry out increment.
Therefore, current drain of the value of symbol in data channel corresponding to the data channel during data burst.Therefore, may be used
To assign a weighting to the value of symbol for reflecting their current flow consuming costs.For example, can be to the symbol for position to (1,1)
Distribute weight 0；Weight 1 can be distributed to for symbol of the position to (1,0)；Power can be distributed to for symbol of the position to (0,1)
Weigh 2；Weight 3 can be distributed to for symbol of the position to (0,0).
In this example, one can be assigned using the data burst on 8 channel serial data/address bus of PAM-4 coding
Total weight, for range from 0 to 24, this is equivalent to the current drain range for example from 0 to 120mA.If all in data burst
Symbol all encodes position to (1,1), then total weight of data burst is 0；If all symbols in data burst all encode
Position is to (0,0), then total weight of data burst is 24.The data burst all formed by 0 consumes most electric currents, therefore from function
It is most expensive from the perspective of consumption.
With reference to Fig. 3, conventional PAM-4 data channel voltage waveform 300, which passes through, utilizes all 4 grades of symbols, between each clock
It is interposed between 2 data of coding in data channel.One 12 type sequences are 110001100011.This sequence can be used as one
Serial level Four symbol transmission, two positions of each symbolic coding.For bit sequence 110001100011, position 11 is encoded into the first string
Row data bus clock interval t0-t1；Lower two 00 are encoded into the second serial data bus clock interval t1-t2；Etc..This
Cause on serial data bus from t0-t1 and from 23 Δ V voltage level changes of t4-t5.
Symbol n Δ V is referred between clock interval in the data channel of serial data bus apart from reference voltage VbN- increase
Measure voltage change.For example, different symbols has the interval of 0.2V, reference voltage V referring again to Fig. 2bFor 0.6V, the change of 3 Δ V
The incremental voltage of 3 × 0.2V or 0.6V in the data channel between bus clock cycle will be corresponded to by changing.
Higher voltage increment can generate more noises, because they will lead to higher current wave in data channel
It is dynamic.Therefore in Fig. 3,3 Δ V increments between bus clock interval t0 and t1 and between t4 and t5 may be generated significantly
Noise.Reduce the signal-to-noise ratio that this maximum incremental voltage activity helps to improve the PAM-4 system such as PAM-4 transceiver 200.
The logical table of PAM-433 encoder 400 in one embodiment is as shown in Figure 4.For example discussed above position
Sequence 110001100011, PAM-433 encoder 400 eliminate the variation of 3 Δ V voltage levels on serial data bus.Such as patrol
It collects shown in table, (wherein x is 0 or 1 " don't care when between two 2 bit sequences that three bit sequences 000 are located at list 1x
(paying no attention to) " value), three bit sequences 000 are encoded as four 0111 (referring to the first row of logical table, third column).In other words,
When three bit sequences 000 bridge two 2 bit sequences, wherein each 2 bit sequence has most significant bit collection (1x), 7 total positions
It is recoded to 1x01111x.In the above example, wherein 7 total positions are 1100011, the sequence recompiled is
11011111.Then each of the sequence 2 are transmitted in the data channel of serial data bus to as PAM-4 symbol,
Obtain PAM-433 data channel voltage waveform 500 in Fig. 5.To sacrifice a serial data bus clock cycle as cost, use
DBI line eliminates the variation of 3 Δ V voltage levels in sequence 110001100011.In other words, it is assumed that the position of a random distribution
Sequence, compared with for every serial data bus clock interval 2.0 of traditional PAM-4, effective message transmission rate is flat
16.7% is reduced, 1.67 Bits Serial data/address bus clock intervals are reduced to.
Compared with conventional PAM-4 encoder, PAM-433 encoder 400 is not needing the case where transmitting any metadata
Under, the worst case for carrying out voltage level switching on the data line can reduce by 33%.PAM-433 encoder 400 will be in data
The bit sequence transmitted on channel is divided into five-digit number according to sequence: first 2 of every five, which are encoded into one, has 4 possible voltages
The symbol of level, last three of five are encoded into 2 symbols, and each symbol has 3 possible voltage levels.
In general, above-mentioned mechanism can be applied to PAM-N (symbol utilizes N number of possible discrete voltage levels).For example,
PAM-866 scheme can transmit three data symbols when transmitting first time, transmit five-digit number in next transmission twice
According to symbol (transmission 2.67 every time, 11.1% expense).PAM-866, which can switch maximum voltage from 7 Δ V (PAM-8), to drop
As low as 5 Δ V (reducing by 28.5%).Furthermore, it is possible to which the mechanism to be expanded to data symbol (such as the PAM- of any other combination
WXYZ), to obtain better reliability using the mechanism similar to PAM-433.
Fig. 6 to Fig. 9 is described each data channel voltage waveform when being encoded using PAM-433.It describes for according to channel
Transmit four kinds of data channel voltage waveforms of a variety of different bit patterns: data channel voltage waveform 600, data channel voltage wave
Shape 700, data channel voltage waveform 800 and data channel voltage waveform 900.
For Fig. 6 and data channel waveform shown in Fig. 7, the first three-level symbol 604 and the second three-level symbol 606 are used as
" bridge 610 " between the first level Four symbol 602 and the second level Four symbol 608 with identical most significant bit (MSB).Meet this
The example of kind mode is level Four symbol pair, such as: 11 (3 Δ V)/10 (2 Δ V) (Fig. 6) and 01 (1 Δ V)/00 (0 Δ V) (Fig. 7).
The voltage window of first three-level symbol 604 and the second three-level symbol 606 is snapped to the first level Four symbol 602 by PAM-433 coding
With the voltage level of the first three-level symbol 604, in this way, the maximum voltage increment in data channel voltage waveform is 2 Δs
V。
For Fig. 8 and data channel waveform shown in Fig. 9, the first three-level symbol 604 and the second three-level symbol 606 are used as
Bridge 610 between the first level Four symbol 602 and the second level Four symbol 608 with different MSB.In such a scenario, first
There may be a 3 Δ V voltage increments between three-level symbol 604 and the second three-level symbol 606.However, PAM-433 encoder
400 do not map the value that will lead to that this thing happens in logical table.PAM-433 encoder 400 is from prominent without using will lead to three-level
The symbol of 3 Δ V voltage increments between hair, so that the maximum voltage increment in data channel waveform be made to be maintained at 2 Δ V.
Referring to Fig.1 0, PAM-433 routine 1000 in one embodiment is by the volume of data on serial data bus
Position is divided into multiple sequences, and each sequence includes five (frame 1002).Next, PAM-433 routine 1000 is by each five sequences
The front two of column is encoded to 4 grades of symbols (frame 1004).Then, PAM-433 routine 1000 compiles lower three of each five bit sequence
Code is two three-level symbols (frame 1006).PAM-433 routine 1000 may be operative to the one or more of serial data bus
Symbol in a data channel is encoded.
In some embodiments, the two three-level symbols include the first three-level symbol and the second three-level symbol.PAM-433
Journey 1000 operates serial data bus, the voltage level coding of the first three-level symbol is one of the following: (a) lower than the level Four
Most two voltage steps of the voltage level of symbol, or (b) higher than most two voltage steps of voltage level of the level Four symbol.
Five bit sequence can also include the one or five bit sequence transmitted on the serial data bus, and at the one or five
The two or five bit sequence that sequence is transmitted later on the serial data bus.Then, PAM-433 routine 1000 can operate string
Row data/address bus is the voltage level of the second three-level symbol of the one or five bit sequence coding to be one of the following: (a) the two or five
Most two voltage steps below the voltage level of the level Four symbol of bit sequence, or (b) in the level Four symbol of the two or five bit sequence
Voltage level more than at most two voltage steps.
With reference to Figure 11, volume of data position is divided into several sequences, these positions by more general PAM-N routine 1100
Number N (frame 1102) of the number based on voltage level.If next, PAM-N routine 1100 will be before each several bit sequences
Dry position is encoded to N grades of bursts, and the first bits number is the logarithm (frame 1104) for being bottom N with 2.Then, PAM-N routine 1100 will be each
Several positions are encoded to two M grades of bursts under several bit sequences, under several positions be that log2 [(N^2)/2] and M are equal to apply
In the integer (frame 1106) of the subduplicate flow in upper plenum (ceiling function) of [(N^2)/2].PAM-N routine 1100
It may be operative to carry out data communication by serial data bus.
Referring to Fig.1 2, instantiate the embodiment of PAM-4433 coding 1200.1200 operation serial data of PAM-4433 coding
Bus, to use the first level Four symbol 1202, the second level Four symbol 1204, the first three-level symbol 1206 and the second three-level symbol
1208 sequence encodes and transmits seven bit data words.Therefore, it is possible between two level Four symbols in particular data channels
There are 3 Δ V voltage increments, such as the first level Four symbol 1202 and the second level Four symbol 1204.However, as shown in figure 12,3 Δ of current potential
V voltage increment may interlock across multiple data channel, which reduce in any specific data burst (in a clock interval phase
Between by serial data bus send all positions) maximum voltage increment.Multiple 3 Δ V voltage increments do not appear in same
In data burst, which reduce crosstalks and other noise sources.PAM-4433 coding 1200 has 12.5% bandwidth cost (each
Transmission 1.75), and there are maximum average 2.25 Δ V maximum voltage increments in this example (certainly in four data channel
The data channel of other quantity can be used in other embodiments).
One embodiment of 3, PAM-4433 routine 1300 will be uploaded in the data channel of serial data bus referring to Fig.1
Defeated volume of data position is divided into seven bit sequences (frame 1302).Next, PAM-4433 routine 1300 is by each seven bit sequence
First four be encoded to two level Four symbols (frame 1304).Then, PAM-4433 routine 1300 is by lower the three of each seven bit sequence
Position is encoded to two three-level symbols (frame 1306).This is repeated in multiple data channel of serial data bus, then, level Four symbol
Conversion between number can interlock in time across data channel and (be aligned on different serial data bus clock intervals).
Referring to Fig.1 4, if current sign corresponds to the data channel voltage of 0 Δ V or 3 Δ V, in one embodiment,
Variable PAM-433 coding 1400 will activation PAM-433 coding.This is referred to as " the trigger data for activating PAM-433 coding
1402".When encountering trigger data 1402, three-level symbol bridge 1404 appropriate is used after trigger data.Otherwise, if do not had
Have and encounter trigger data, variable PAM-433 coding 1400 encodes (all symbols are all level Four) using conventional PAM-4.It can
The PAM-433 coding 1400 of change leads to the maximum voltage increment of 2 Δ V in serial data bus data channel voltage waveform.
With reference to Figure 15, variable PAM-433 routine 1500 determines that the front two of five bit sequences is encoded to total with serial data
The corresponding level Four symbol (frame 1502) of the highest voltage level or lowest voltage level used in the data channel of line.In other words
It says, encounters trigger data.In response to encountering trigger data, variable PAM-433 routine 1500 is by lower three in five bit sequences
Position is encoded to two three-level symbols (frame 1504).
Figure 16 is the block diagram of one embodiment of computing system 1600, wherein may be implemented of the invention one or more
Aspect.Computing system 1600 includes system data bus 1636, CPU 1626, input unit 1630, system storage 1604, figure
Shape processing system 1602 and display device 1628.It in an alternate embodiment of the invention, can be by CPU 1626, graphic system 1602
Part, system data bus 1636 or any combination thereof is integrated into single processing unit.In addition, graphic system 1602
Function may include in chipset or the specialized processing units or coprocessor of some other types.
As shown, system data bus 1636 connects CPU 1626, input unit 1630, system storage 1604 and figure
Shape processing system 1602.In an alternate embodiment of the invention, system storage 1604 can be directly connected to CPU 1626.CPU 1626
User's input from input unit 1630 is received, the programming instruction that is stored in system storage 1604 is executed, to being stored in
Data in system storage 1604 are operated, and by configuration graphic system 1602 to execute the spy in graphics pipeline
Determine task.System storage 1604 generally includes dynamic random access memory (DRAM), is used to store CPU 1626 and figure
The programming instruction and data of the processing of shape processing system 1602.Graphic system 1602 receives the instruction transmitted by CPU 1626,
And process instruction inside computing system 1600 to execute various operations.
As shown, system storage 1604 include application program 1612, API 1618 (application programming interface) and
Graphics processing unit driver 1622 (GPU driver).Application program 1612 generates the calling to API 1618, to generate
Required result set.For example, program transportation is also executed shading operations to API 1618 by application program 1612, artificial intelligence is grasped
Work or graphical rendering operations.1618 function of API can usually be realized in graphics processing unit driver 1622.At figure
Reason unit driver 1622 is configured to advanced coloring process being converted to machine code.
Graphic system 1602 includes GPU 1610 (graphics processing unit), on piece GPU memory 1616, on piece GPU
Data/address bus 1632, GPU local memory 1606 and GPU data/address bus 1634.GPU 1610 is configured to through on piece GPU data
Bus 1632 is communicated on piece GPU memory 1616, and logical by GPU data/address bus 1634 and GPU local memory 1606
Letter.One or more of coding techniques described herein can be used in GPU data/address bus 1634.
GPU 1610 can receive the instruction transmitted by CPU 1626, and store the result into GPU local memory 1606
In.Then, if instruction is graphics command, GPU 1610 can be shown in display device 1628 certain is stored in the local GPU
Graph image in memory 1606.
GPU 1610 includes one or more logical blocks 1614.The operation of logical block 1614 may be implemented of the present invention
The embodiment of encoding scheme.Logical block 1614 can be used as instruction and be loaded on GPU, can also be used as instruction set architecture feature and exists
It is realized in circuit or the combination of the two.
GPU 1610 can also have any amount of on piece GPU memory 1616 and GPU local memory 1606, including
0, and can use on piece GPU memory 1616, GPU local memory 1606 and system storage 1604 with any combination into
Line storage operation.Data/commands bus between these memories and GPU 1610 can be used it is described herein a kind of or
More kinds of coding techniques.
On piece GPU memory 1616 is configured to include GPU programming 1620 and on piece buffer area 1624.GPU programming 1620 can
To be transferred on piece GPU memory 1616 from graphics processing unit driver 1622 by system data bus 1636.System
One or more of coding techniques described herein can be used in data/address bus 1636.
For example, GPU programming 1620 may include machine code vertex shading program, machine code geometry coloring journey
Sequence, machine code fragment shader program, artificial intelligence program or every kind of program any number of variant.On piece buffer area
1624 data for needing quickly to access commonly used in storage, to reduce the delay of this generic operation.
GPU local memory 1606 generally includes the outer dynamic random access memory (DRAM) of relatively inexpensive piece, and
For storing the data and programming that GPU 1610 is used.As shown, GPU local memory 1606 includes frame buffer zone 1608.
Frame buffer zone 1608 stores the data for driving at least one two-dimensional surface of display device 1628.In addition, frame buffer zone
1608 may include more than one two-dimensional surface, so that GPU 1610 can be rendered into a two-dimensional surface, while use second
Two-dimensional surface drives display device 1628.
Display device 1628 is can issue visual image corresponding with input data signal one or more defeated
Device out.It is, for example, possible to use cathode-ray tube (CRT) monitor, liquid crystal display or any other suitable display systems
To construct display device.The input data signal for being sent to display device 1628 is usually to pass through scanning to be stored in frame buffer zone
The contents of one or more frames of image data in 1608 generates.
Specific voltage, ampere and other details described above are for illustration purposes only.A variety of tools can be used in the present invention
Voltage level, electric current, resistance of body etc. are realized.Although the present invention transfers data to the upper of memory in such as processor
Described in the text up and down is stated, but the signaling technologies such as PAM-4 described herein can be practiced in various signaling systems, at this
In a little signaling systems, data are sent to reception device from sending device, or transmission etc. between R-T unit.
Term used herein should meet its ordinary meaning in the related technical field, or within a context by using
Meaning indicated by them then abides by the meaning but if providing specific definition.
" logic " of this paper refers to machine memory circuit, non-temporality machine readable media and/or circuit, passes through its material
Material and/or material energy configuration, including control and/or process signal, and/or setting and value (such as resistance, impedance, capacitor, electricity
Sense, current/voltage rated value etc.), it can be used for influencing device operation.Such as controller, field programmable gate array, processor
Electronic circuit with the memory (both volatile and non-volatiles) or the like for including processor-executable instruction is exactly logic
Example.Logic be particularly intended to exclude pure signal or software itself (but be not excluded for include software machine memory, to be formed
The configuration of substance).
Various logic feature operation described herein can be short with the noun or noun using the reflection operation or function
Language is realized the logic that refers to.For example, operation associated can be executed by " correlator " or " correlator ".Equally, switching can be with
It is executed, can also be selected by " selector " by " switch ", and so on.
Skilled artisans will appreciate that arriving, logic can be distributed in one or more devices or component, and/or can
It is combined into the group by memory, medium, processing circuit and controller, other circuits etc..Therefore, for clarity and correctly, patrol
Collecting may be not always to clearly demonstrate in the figure of device and system, although it is inherently present in wherein.It is described herein
Technology and program can be realized by the logic being distributed in one or more computing devices.According to realization, the tool of logic
Body distribution and selection will will be different.
In the disclosure, different entities (can be referred to variously as " unit ", " circuit ", other assemblies etc.) can be retouched
State or claim as " configuration " to be to execute one or more tasks or operation.This formula --- [entity] is configured to [execute
One or more tasks] --- it is used herein refer to for structure (i.e. for example, thing of physics, such as electronic circuit).More specifically
Say that this formula is used to indicate this structure and is arranged to execute one or more tasks during operation in ground.It can will tie
Structure " being configured to " executes certain tasks, even if the structure is currently without being operated." credit assignment circuit configuration is by credit assignment
To multiple processor cores " it is intended to cover, for example, integrated circuit, has the circuit for executing the function during operation, even if begging for
Integrated circuit in is currently not used by (such as not connected power supply).Therefore, it is described or is stated as " being configured to " and execute certain
The entity of a task refers to the thing of some physics, such as device, circuit, storage can be performed as the program instruction of realization task
Memory etc..This phrase is not used in herein refers to invisible thing.
Term " being configured to " is not intended to mean " can be configured to ".For example, unprogrammed FPGA is not to be regarded as " configuration
For " certain specific functions are executed, although possible " can be configured to " executes the function after programming for it.
With the executing one or more task-awares unawareness of record structure " being configured to " in the appended claims
Figure calls 35 article of the 112nd (f) money of United States Code No. for the claim element.It therefore, does not include for [executing function] "
" claims hereof of construction should not make an explanation device (means) according to 35 article of the 112nd (f) money of United States Code No..
As it is used herein, term "based" is used to describe to influence determining one or more factors.The term is simultaneously
A possibility that determining may be influenced by being not excluded for other factors.That is, determination may be based only on specified factor, Huo Zheji
In specified factor and other unspecified factors.Consider phrase " A is determined based on B ".It is for determining that this phrase, which specifies B,
A factor of A, or influence a factor of the determination of A.This phrase be not excluded for A determination may also based on it is some its
His factor, such as C.This phrase is also intended to covering and is based only upon the embodiment that B determines A.As it is used herein, phrase " being based on " with
Phrase " being at least partially based on " is synonym.
As it is used herein, phrase " in response to " describes one or more factors of triggering effect.This phrase
A possibility that other factors may influence or trigger this effect is not precluded.That is, an effect may be only pair
The response of these factors, or may be the response to prescription factors and other not specified factors.Consider phrase " in response to B
Execute A ".It is the factor for triggering A and executing that this phrase, which specifies B,.This phrase be not precluded may also in response to it is some its
He is factor (such as C) Lai Zhihang A.This phrase alsos attempt to covering and is only in response to B to execute the embodiment of A.
As it is used herein, term " first ", " second " etc. are used as the label before noun, it is unless otherwise stated, no
Any kind of sequence (for example, space, time, logic etc.) is not implied that then.For example, there is the register of 8 registers at one
In file, term " the first register " and " the second register " can be used to refer to any two in 8 registers of generation, and not only
It is only such as logic register 0 and 1.
When in detail in the claims use term "or" when, "or" be used as inclusive or, rather than it is exclusive or.
For example, phrase " at least one of x, y or z " indicates any one of x, y and z and any combination thereof.
Claims (18)
1. a kind of method for encoding volume of data position, comprising:
Volume of data position is divided into several sequences, the number of position is based on the voltage level used in PAM-N symbol
Number N；
The position of first number of each sequence is encoded to N grades of symbols, the position of first number is the N for being bottom with 2
Logarithm；
The position of next number of each sequence is encoded to two M grades of symbols, the position of next number is log2 [(N2)/
2], and M is equal to be applied to [(N2)/2] subduplicate flow in upper plenum integer；And
The N grades of symbol and described two M grades of symbol are communicated on serial data bus.
2. a kind of method for operating serial data bus, which comprises
The volume of data position for being used to communicate on serial data bus is divided into multiple sequences, each sequence includes five；
Front two in five bit sequence described each of on the serial data bus is encoded to level Four symbol；And
It is two three-level symbols by the lower tri-bit encoding in five bit sequence described each of on the serial data bus.
3. according to the method described in claim 2, wherein selecting described two three-level symbols to eliminate the serial data bus
A possibility that there are maximum voltage increments between upper level Four symbol.
4. according to the method described in claim 2, further comprising:
Lower three of five bit sequence each of are selectively encoded on the serial data bus, condition is each described five
On the front two of bit sequence highest symbol voltage level used in the serial data bus or minimum symbol voltage level
It is encoded to level Four symbol.
5. according to the method described in claim 2, wherein described two three-level symbols include the first three-level symbol and the second three-level
The voltage level of symbol, the first three-level symbol is one of the following: (a) being lower than the voltage level most two of the level Four symbol
A voltage step, or (b) higher than most two voltage steps of voltage level of the level Four symbol.
6. according to the method described in claim 2, wherein described two three-level symbols include the first three-level symbol and the second three-level
Symbol, and further comprise:
Five bit sequence includes the one or five bit sequence for communicating on the serial data bus, and for described
The two or five bit sequence communicated on the serial data bus after one or five bit sequence；And
The voltage level of second three-level symbol of the one or five bit sequence is one of the following: (a) being lower than the two or five sequence
Most two voltage steps of voltage level of the level Four symbol of column, or (b) it is higher than described the four of the two or five bit sequence
Most two voltage steps of voltage level of grade symbol.
7. a kind of method for operating serial data bus, which comprises
The volume of data position for being used to communicate on the serial data bus is divided into seven bit sequences；
First four of each seven bit sequence are encoded in two level Four symbolic codings to the serial data bus；And
It is in two three-level symbolic codings to the serial data bus by the lower tri-bit encoding of each seven bit sequence.
8. according to the method described in claim 7, wherein the serial data bus includes the first data channel and the second data
Channel, transmission of described two level Four symbols between first data channel and second data channel are wrong in time
It opens.
9. according to the method described in claim 8, described two level Four symbols that are wherein staggered are in first data channel and institute
Stating the transmission between the second data channel includes two level Four in different clock intervals, for first data channel
The transmission of symbol is different from for the transmission of two level Four symbols of second data channel.
10. according to the method described in claim 7, further comprising:
Lower three of each seven bit sequence are selectively encoded on the serial data bus, condition is each described seven
The second two highest symbol voltage levels used in the serial data bus of bit sequence or minimum symbol voltage electricity
Level Four symbol is encoded as on flat.
11. according to the method described in claim 7, wherein described two three-level symbols include the first three-level symbol and the second three-level
The voltage level of symbol, the first three-level symbol is one of the following: (a) lower than second four in described two level Four symbols
Most two voltage steps of voltage level of grade symbol, or (b) higher than second level Four symbol in described two level Four symbols
Most two voltage steps of voltage level.
12. according to the method described in claim 7, wherein described two three-level symbols include the first three-level symbol and the second three-level
Symbol, and further comprise:
Seven bit sequence includes the one or seven bit sequence for communicating on the serial data bus, and for described
The two or seven sequence that one or seven bit sequence communicates on the serial data bus after communicating on the serial data bus
Column；And
The voltage level of the second three-level symbol of one or seven bit sequence is one of the following: (a) being lower than the described 1st
Most two voltage steps of the voltage level of second level Four symbol of described two level Four symbols of bit sequence, or (b) be higher than
Most two voltage steps of the voltage level of second level Four symbol of described two level Four symbols of the one or seven bit sequence.
13. a kind of serial data bus transmitter, comprising:
Multiple line driver circuits；
Logic is coupled with the line driver circuit, for the front two of five bit sequences to be encoded to level Four symbol, and will be every
The lower tri-bit encoding of a five bit sequence is two three-level symbols.
14. it is institute that serial data bus transmitter according to claim 13, which further comprises by the lower tri-bit encoding,
The logic of two three-level symbols is stated, condition is that the front two of each five bit sequence is used on the serial data bus
Highest voltage level or lowest voltage level on be encoded as level Four symbol.
15. serial data bus transmitter according to claim 13, wherein described two three-level symbols include the one or three
Grade symbol and the second three-level symbol, and the voltage level of the first three-level symbol is lower than the voltage level of the level Four symbol
Most two voltage steps.
16. serial data bus transmitter according to claim 13, wherein described two three-level symbols include the one or three
Grade symbol and the second three-level symbol, and the voltage level of the first three-level symbol is higher than the voltage level of the level Four symbol
Most two voltage steps.
17. serial data bus transmitter according to claim 13, wherein described two three-level symbols include the one or three
Grade symbol and the second three-level symbol, and
The serial data bus transmitter further comprises logic, for by the second three-level symbol of the one or five bit sequence
The voltage level level Four symbol that is set below the two or five bit sequence most two voltage steps of voltage level.
18. serial data bus transmitter according to claim 13, wherein described two three-level symbols include the one or three
Grade symbol and the second three-level symbol, and
The serial data bus transmitter further comprises logic, for by the second three-level symbol of the one or five bit sequence
Voltage level be set above most two voltage steps of voltage level in the level Four symbol of the two or five bit sequence.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201862650168P | 2018-03-29 | 2018-03-29 | |
| US62/650,168 | 2018-03-29 | ||
| US15/929,094 US11966348B2 (en) | 2019-01-28 | 2019-01-28 | Reducing coupling and power noise on PAM-4 I/O interface |
| US15/929,094 | 2019-01-28 |
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| CN110321312B (en) | 2023-11-24 |
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