CN110321260A - A kind of AXI bus interface read-write data comparing method and UVM verification platform based on UVM - Google Patents
A kind of AXI bus interface read-write data comparing method and UVM verification platform based on UVM Download PDFInfo
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- CN110321260A CN110321260A CN201910577515.0A CN201910577515A CN110321260A CN 110321260 A CN110321260 A CN 110321260A CN 201910577515 A CN201910577515 A CN 201910577515A CN 110321260 A CN110321260 A CN 110321260A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
In order to overcome existing read-write data to compare the technical problem of conceptual design complexity, the AXI bus interface data read-write comparative approach and UVM verification platform, the present invention that the present invention provides a kind of based on UVM are writing data link: according to write address, write bit is wide and writes the write gate information in bursty data period and carries out write operation to effectively writing data；Reading data link: obtaining read command identity according to reading data identity first, then according to the corresponding read address of read command identity, read bit it is wide to valid reading according to read operation is carried out, finally carry out the judgement for reading data.
Description
Technical field
The invention belongs to chip checking technical fields, are related to a kind of AXI bus interface read-write data side based on UVM
Method and UVM verification platform.
Background technique
Build UVM (Universal Verification Methodology, generic validation methodology) verification environment into
The IP of row AXI (Advanced eXtensible Interface, advanced expansible bus interface) bus interface
(Intellectual Property, ip module) emulation, the AXI bus interface read-write data to IP are relatively that UVM is tested
One of the checking mechanism for demonstrate,proving the most basic most critical of environment, is mainly used for: the smoke test of environment debugging can help verifier's tune
Whether test ring border, verifying circuit elementary path are correct；In a variety of operating process or after operation, for checking whether logarithm
It is impacted according to access；The design defect of bus slave EM equipment module is found out in help；Debugging read-write access is rushed with what other were operated
Prominent mechanism.
The principle that existing read-write data compare is as shown in Figure 1, monitor captures reading and writing data from AXI interface module
It after stream, passes it to reference model and is handled, statistical comparison is finally carried out in scoring board, printing passes through (i.e. total from AXI
The data that line interface is read are correct) or failure (error in data read from AXI bus interface) information.It is lacked with following
Point:
1. reference model and scoring board design are complicated, the development time is long, is not easy fast integration and is applied in platform.
2. needing to define very big static storage, in simulation process, emulator permanently will distribute one piece admittedly for static storage
Fixed memory source causes the significant wastage of memory source.
3. may resequence to read command inside circuit, need to increase and the function to be verified inside reference model
The similar complexity of energy IP circuit, which reorders, handles logic, designs extremely complex.
Summary of the invention
In order to overcome existing read-write data to compare the technical problem of conceptual design complexity, the present invention provides one kind to be based on
The AXI bus interface data read-write comparative approach and UVM verification platform of UVM.
Technical solution of the present invention:
A kind of AXI bus interface read-write data comparing method based on UVM, is characterized in that, comprising steps of
Writing data link:
According to write address, write bit is wide and writes the write gate information in bursty data period and carries out write operation to effectively writing data；
Reading data link:
Reading data link:
Read command identity is obtained according to reading data identity first, it is then corresponding according to read command identity
Read address, read bit it is wide to valid reading according to carry out read operation, finally carry out read data judgement.
Further, data link is being write:
It is described according to write address, write bit is wide and writes the write gate information in bursty data period and carries out writing behaviour to effectively writing data
As:
1.1) in the write order period, write address is pressed into the queue of AXI write address, by the wide mark of the wide indentation AXI write bit of write bit
Queue；
1.2) each in AXI writes the bursty data period, respectively from the queue of AXI write address and the wide mark team of AXI write bit
Corresponding write address is taken out in column and write bit is wide；
1.3) write bit taken out according to step 1.2) is wide, and writes the write gate information in bursty data period, from writing data
It is middle to take out effective write data byte, and calculated according to the write address that step 1.2) is taken out corresponding to effective write data byte
Effective write address；
1.4) using the corresponding effective write data byte of each effective write address as an element, AXI is deposited in
In memory；
Reading data link:
It is described according to read address, read bit is wide and read command identity carries out read operation to valid data are as follows:
2.1) in the read command period, read address is pressed into the queue of AXI read address, by the wide mark of the wide indentation AXI read bit of read bit
Read command identity is pressed into AXI read command identity queue by queue；
2.2) each in AXI reads bursty data period, according to reading data identity from AXI read command identity
First queue index corresponding to read command identity equal thereto is searched in queue, obtains first queue rope
After drawing, deletes first queue and index corresponding element；
2.3) it is indexed according to first queue, corresponding read address information is found out from AXI read address queue, from
The wide information of corresponding read bit is found out in the wide mark queue of AXI read bit, then, the reading ground is deleted from AXI read address queue
Information corresponding element in location deletes the corresponding element of the wide information of the read bit from the wide mark queue of AXI read bit；
2.4) the wide information of the read bit obtained according to step 2.3), from reading to take out valid reading in data according to byte, and according to
The read address information that step 2.3) obtains is calculated with the valid reading according to the corresponding effective read address of byte；
2.5) the effective read address information obtained according to step 2.4) goes in the AXI memory to find out corresponding data；
2.6) judgement of data is read.
Further, the 2.6) judgement for reading data are as follows:
Effectively reading data clock edge, by the data read from the AXI bus interface of tested design and step 2.5) from
The data found out in the AXI memory are compared, and the equal data for then indicating to read from AXI bus interface of the two are correct,
Otherwise the error in data read from AXI bus interface is indicated.
Further, in the step 2.2), the lookup is to look at the top of AXI read command identity queue to bottom
It looks for.
Further, the write address, read address, write bit is wide, read bit is wide, read command identity
When being pressed into queue: being pressed into from queue bottom；When taking-up: popping up at the top of from queue or taken out according to index.
Further, the described data bit width and byte bit wide phase write, read the storage of AXI memory used in data link
Together.
Further, first queue index is integer type.
Further, in step 1.4), one element of every storage in the AXI memory, emulator can dynamically be its point
With one piece of memory headroom.
Further, the AXI memory is Associate array.
Further, the queue of AXI write address, the wide mark queue of AXI write bit, the queue of AXI read address, the wide mark of AXI read bit
Queue, AXI read command identity queue and Associate array utilize object-oriented high-level language to realize.
The present invention also provides a kind of UVM verification platforms, including AXI main equipment environment；The AXI main equipment environment includes
Monitor, driver and sequencer；It, which is characterized in that in the monitor, is integrated with computer program, the meter
AXI bus interface when calculation machine program is run by processor for realizing above-mentioned based on UVM reads and writes data comparing method.
Beneficial effects of the present invention:
1. the present invention solves circuit to the rearrangement bring of order using the powerful index of queue, element function of search
Comparison mechanism obstacle greatly reduces the complexity of comparison mechanism design.
2. the present invention carries out the storage and reading of data, design letter using the queue of object-oriented high-level language and Associate array
It is clean, efficiently, it is convenient for fast integration and application.
3. the present invention is due to introducing Associate array, in simulation process, emulator is that Associate array carries out the non-company of dynamic
Continuous address space allocation, thus greatly reduce the consumption in simulation process to memory source.
4. AXI read-write comparative approach of the invention is placed in monitor, environment components (reference model and score is omitted
Plate) exploitation, to reduce the workload designed and developed, and it is managed convenient for UVM top layer.
Detailed description of the invention
Fig. 1 is the schematic illustration that existing AXI bus interface reads and writes that data compare scheme.
Fig. 2 is the schematic illustration of AXI bus interface data writing operation of the present invention.
Fig. 3 is that AXI bus interface of the present invention reads data manipulation and reads and writes the schematic illustration that data compare.
Fig. 4 is the Integrated Solution figure that AXI bus interface of the present invention reads and writes data comparing method.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
AXI bus interface provided by the present invention based on UVM reads and writes data comparing method, including writes data link and reading
Data link.
Referring to fig. 2, the treatment process of data link is write are as follows:
Write address is pressed into the queue of AXI write address in the write order period by step 1.1), and the wide indentation AXI write bit of write bit is wide
Indicate queue.
Step 1.2): each in AXI writes the bursty data period, respectively from the queue of AXI write address and the wide mark of AXI write bit
Corresponding write address is taken out in will queue and write bit is wide.
Step 1.3) is wide according to the write bit that step 1.2) is taken out, and writes the write gate information in bursty data period, from writing
Effective write data byte is taken out in data, and is calculated and effective write data byte according to the write address that step 1.2) is taken out
Corresponding effective write address.
Step 1.4) is deposited in using the corresponding effective write data byte of each effective write address as an element
In Associate array；One element of every storage in Associate array, emulator can dynamically be that it distributes one piece of memory headroom.
Referring to Fig. 3, the treatment process of data link is read are as follows:
Step 2.1): in the read command period, being pressed into the queue of AXI read address for read address, and the wide indentation AXI read bit of read bit is wide
Indicate queue, read command identity is pressed into AXI read command identity queue.
Step 2.2): each in AXI reads bursty data period, according to reading data identity from AXI read command body
First queue corresponding to the read command identity equal with data identity is read is searched in part mark queue to index, and is obtained
To after this queue index, the corresponding element of the index is deleted.It is at the top of AXI read command identity queue in search procedure
It is searched to bottom, when finding first read command identity equal with data identity is read, corresponding index
As first index.
Step 2.3): indexing according to first queue, and corresponding read address letter is found out from AXI read address queue
Then breath is deleted element corresponding to this read address in the queue of AXI read address, is found out from the wide mark queue of AXI read bit
The wide information of corresponding read bit, then deletes the corresponding element of read bit width in the wide mark queue of AXI read bit.
Step 2.4): the wide information of read bit obtained according to step 2.3), from reading to take out valid reading in data according to byte, and
The read address information obtained according to step 2.3) is calculated with the valid reading according to the corresponding effective read address of byte.
Step 2.5): the effective read address obtained according to step 2.4) goes in the Associate array to find out corresponding data.
Step 2.6): effectively reading data clock edge, the number that will be read from the AXI bus interface of tested design (DUT)
It is compared according to the data found out from the Associate array with step 2.5), the two is equal then to be indicated from tested design (DUT)
The data that read of AXI bus interface it is correct, the data for otherwise indicating that the AXI bus interface from tested design (DUT) is read are wrong
Accidentally.
" effective write data byte " and " valid reading is according to byte " involved in above-mentioned steps have in AXI protocol clear bright
True regulation, specifically in AXI clock signal aclk level hopping edge, and interface signal rvalid and rready from low to high
When being all high, reading data are effective, and when interface signal wvalid and wready are high, it is effective to write data.
In above-mentioned steps: write address, read address, write bit is wide, read bit is wide, and read command identity is all when being pressed into queue
It is pressed into from queue bottom, is popped up when taking out or at the top of queue or is taken out according to index, that is, can be according to elder generation
It is taken out into the first taking-up of queue, or according to index.Writing, reading Associate array used in data link is the same Associate array,
The data bit width of Associate array storage is identical as byte bit wide (8bit), and first queue index is int type (integer type).
As shown in figure 4, since monitor is connected with AXI interface module, and monitor is the member of the tree-like tissue of UVM,
Therefore AXI read-write comparative approach (AXI_RD_WR_CHECKER) of the invention can be integrated into monitor in the form of plug-in unit,
To which the component in AXI main equipment environment be omitted, that is, reference model and scoring board is omitted, while also facilitating UVM verifying flat
Management of the platform top layer to AXI read-write comparative approach.
Claims (10)
1. a kind of AXI bus interface based on UVM reads and writes data comparing method, which is characterized in that comprising steps of
Writing data link:
According to write address, write bit is wide and writes the write gate information in bursty data period and carries out write operation to effectively writing data；
Reading data link:
First according to data identity acquisition read command identity is read, then according to the corresponding reading ground of read command identity
Location, read bit it is wide to valid reading according to read operation is carried out, finally carry out the judgement for reading data.
2. the AXI bus interface according to claim 1 based on UVM reads and writes data comparing method, which is characterized in that
Writing data link:
It is described according to write address, write bit is wide and writes the write gate information in bursty data period and carries out write operation to effectively writing data
Are as follows:
1.1) in the write order period, write address is pressed into the queue of AXI write address, by the wide wide mark queue of indentation AXI write bit of write bit；
1.2) each in AXI writes the bursty data period, respectively from the queue of AXI write address and the wide mark queue of AXI write bit
It takes out corresponding write address and write bit is wide；
1.3) write bit taken out according to step 1.2) is wide, and writes the write gate information in bursty data period, takes from writing in data
Effective write data byte out, and calculated and corresponding with effective write data byte have according to the write address that step 1.2) is taken out
Imitate write address；
1.4) using the corresponding effective write data byte of each effective write address as an element, AXI storage is deposited in
In device；
Reading data link:
It is described according to read address, read bit is wide and read command identity carries out read operation to valid data are as follows:
2.1) in the read command period, read address is pressed into the queue of AXI read address, by the wide wide mark queue of indentation AXI read bit of read bit,
Read command identity is pressed into AXI read command identity queue；
2.2) each in AXI reads bursty data period, according to reading data identity from AXI read command identity queue
It is middle to search first queue index corresponding to read command identity equal thereto, obtain first queue index
Afterwards, it deletes first queue and indexes corresponding element；
2.3) it is indexed according to first queue, corresponding read address information is found out from AXI read address queue, from AXI
The wide information of corresponding read bit is found out in the wide mark queue of read bit, then, the read address letter is deleted from AXI read address queue
Corresponding element is ceased, the corresponding element of the wide information of the read bit is deleted from the wide mark queue of AXI read bit；
2.4) the wide information of the read bit obtained according to step 2.3), from reading to take out valid reading in data according to byte, and according to step
2.3) the read address information obtained is calculated with the valid reading according to the corresponding effective read address of byte；
2.5) the effective read address information obtained according to step 2.4) goes in the AXI memory to find out corresponding data；
2.6) judgement of data is read.
3. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that:
The judgement for reading data are as follows:
2.6) effectively reading data clock edge, by the data read from the AXI bus interface of tested design and step 2.5) from
The data found out in the AXI memory are compared, and the equal data for then indicating to read from AXI bus interface of the two are correct,
Otherwise the error in data read from AXI bus interface is indicated.
4. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that:
In the step 2.2), the lookup is to search at the top of AXI read command identity queue to bottom.
5. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that:
The write address, read address, write bit is wide, read bit is wide, read command identity
When being pressed into queue: being pressed into from queue bottom；
When taking-up: popping up at the top of from queue or taken out according to index.
6. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that:
The data bit width write, read the storage of AXI memory used in data link is identical as byte bit wide.
7. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that:
First queue index is integer type.
8. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that: step
1.4) in, one element of every storage in the AXI memory, emulator can dynamically be that it distributes one piece of memory headroom.
9. the AXI bus interface according to claim 2 based on UVM reads and writes data comparing method, it is characterised in that: described
AXI memory is Associate array.
10. a kind of UVM verification platform, including AXI main equipment environment；The AXI main equipment environment include monitor, driver and
Sequencer；It is characterized by: being integrated with computer program in the monitor, the computer program is run by processor
When for realizing any AXI bus interface based on UVM of claim 1-9 read and write data comparing method.
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| CN112286746A (en) * | 2020-10-31 | 2021-01-29 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN112527705A (en) * | 2020-11-05 | 2021-03-19 | 山东云海国创云计算装备产业创新中心有限公司 | PCIe DMA data path verification method, device and equipment |
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| CN114546900A (en) * | 2022-01-21 | 2022-05-27 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for verifying MCTP controller |
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| CN112286746B (en) * | 2020-10-31 | 2023-01-24 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN112527705A (en) * | 2020-11-05 | 2021-03-19 | 山东云海国创云计算装备产业创新中心有限公司 | PCIe DMA data path verification method, device and equipment |
| CN112527705B (en) * | 2020-11-05 | 2023-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | PCIe DMA data path verification method, device and equipment |
| CN113434544A (en) * | 2021-06-02 | 2021-09-24 | 中科驭数（北京）科技有限公司 | Database data reading method, database data writing method and device |
| CN113434544B (en) * | 2021-06-02 | 2022-11-18 | 中科驭数（北京）科技有限公司 | Database data reading method, database data writing method and device |
| CN114546900A (en) * | 2022-01-21 | 2022-05-27 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for verifying MCTP controller |
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