CN110308992B - GPU (graphics processing Unit) access management method facing multiple partitions - Google Patents
GPU (graphics processing Unit) access management method facing multiple partitions Download PDFInfo
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- CN110308992B CN110308992B CN201910549642.XA CN201910549642A CN110308992B CN 110308992 B CN110308992 B CN 110308992B CN 201910549642 A CN201910549642 A CN 201910549642A CN 110308992 B CN110308992 B CN 110308992B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/504—Resource capping
Abstract
The invention discloses a GPU access management method facing multiple partitions, which comprises the following steps: the GPU creates a GPU access control semaphore and sets a time threshold value for granting access; the partition CPU applies for a GPU access control semaphore to be controlled when the GPU needs to be accessed; the GPU judges whether the residual time on the time slice of the partition is larger than a time threshold value or not, then judges whether the GPU access control semaphore is idle or not, and if the residual time on the time slice of the partition is larger than the time threshold value, the GPU access control semaphore is granted access authority to a partition CPU; and the GPU checks whether the memory space required by the partition CPU for operating the GPU is sufficient, if so, the partition CPU completes GPU access and operation, and the GPU withdraws the GPU access permission of the partition CPU. The invention eliminates the risk of GPU access blockage caused by partition switching in the traditional multi-partition access GPU, and can meet the deterministic requirement and the forensic requirement of safety critical equipment or a system which uses multi-partitions for graphic processing.
Description
Technical Field
The invention relates to the field of graphic driving software and avionics, in particular to a GPU (graphics processing Unit) access management method of the graphic driving software capable of supporting a multi-partition operating system.
Background
A Graphics Processing Unit (GPU) is widely used in various fields requiring graphics generation and display, such as industry, medical treatment, consumer electronics, and the like, and the most common application scenario is that a Central Processing Unit (CPU) accesses the GPU through a PCI or PCIE bus, submits instructions and data for graphics processing to the GPU, and the GPU finishes graphics drawing and outputting.
The ARINC653 embedded partition real-time operating system commonly used in the avionics system can provide partition functions, and partitions are isolated from each other. In an avionics system, an ARINC653 embedded partition real-time operating system is often used to address the challenges of system certainty and security requirements, partitions are scheduled in a time slice round robin fashion, and when a partition runs out of time slices, the next partition is switched to execute an application on the next partition. In some application scenarios, graphics processing applications need to be run on multiple partitions, and a GPU needs to be shared for graphics processing. In such application scenarios, a management mechanism supporting multi-partition access to the GPU is required to ensure correctness of instructions and data submitted by the GPU for graphics processing. The traditional management technology for accessing the GPU by multiple partitions adopts a mutual exclusion lock mode, before each partition accesses the GPU, the GPU access authority needs to be obtained by applying for semaphores, if the partition is idle, the semaphore is granted to the GPU access authority of the current partition, and the partition has the GPU access authority after the semaphore is obtained. And after the partition acquires the access authority, starting the access operation on the GPU, and after the access operation is finished, releasing the GPU access authority through the release semaphore. If the partition is performing GPU access, the GPU access is not ready to be completed and the semaphore is released, the partition time slice is used up, the ARINC653 partition embedded real-time operating system can be directly switched to the next partition in the scheduling table to be executed, in this case, the graphics processing application in each subsequent partition can be blocked because the GPU access right cannot be acquired, and the partition occupying the GPU access right can execute the release access right again. That is, the conventional management technology for multi-partition access GPU has a risk of blocking GPU access due to partition switching.
This situation not only significantly increases graphics processing latency, but also severely undermines isolation between partitions and graphics application execution time determinism, which is unacceptable for security critical systems. The use of multiple partitions for graphics processing in an avionics system necessitates addressing the effects of such.
Disclosure of Invention
The invention aims to provide a multi-partition-oriented GPU access management method, which can eliminate the risk of GPU access blockage caused by partition switching in the traditional multi-partition GPU access management technology and can meet the deterministic requirements and the forensic requirements of safety critical equipment or systems which use multi-partitions for graphics processing.
The invention aims to be realized by the following technical scheme:
a GPU access management method facing multiple partitions comprises the following steps:
step 1: initiating an initialization request to a GPU (graphics processing Unit) by a partition CPU (Central processing Unit), creating a GPU access control semaphore by the GPU, setting a time threshold value for granting access, and turning to the step 2;
step 2: the partition CPU continuously performs graphic processing, and the step 3 is carried out when the GPU needs to be accessed;
and 3, step 3: the partition CPU applies for controlling GPU access control semaphore to the GPU, and the step 4 is carried out;
and 4, step 4: the GPU judges whether the residual time on the time slice of the partition is larger than a time threshold value, if so, the step 5 is carried out, otherwise, the step 3 is carried out;
and 5: the GPU judges whether the GPU access control semaphore is idle, if so, the GPU access control semaphore is granted access authority to the CPU of the partition, the state of the GPU access control semaphore is changed into busy, and the step 6 is carried out, otherwise, the step 3 is carried out;
step 6: the GPU checks whether the memory space required by the partition CPU for operating the GPU is sufficient, if so, the step 10 is carried out, otherwise, the step 7 is carried out;
and 7: the GPU applies for the memory space required by the operation of the GPU, and the step 8 is carried out;
and 8: the GPU judges whether the memory space application is successful, if so, the step 10 is carried out, otherwise, the step 9 is carried out;
and step 9: the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access permission of the CPU of the partition, and then the step 3 is carried out;
step 10: the partition CPU completes GPU access and operation, and then the step 11 is carried out;
step 11: and (3) the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access authority of the partition CPU, and shifts to the step 2.
The multi-partition-oriented GPU access management method is very suitable for multiple partitions to share and use the GPU for graphics processing, and can meet the certainty requirement and evidence obtaining requirement of safety key systems such as airborne display and the like. The invention does not depend on a specific hardware platform, has good adaptability and flexibility, and can be used for other safety critical equipment or systems.
The method is simple to implement, easy to use, suitable for implementing multi-partition-oriented graphic driving software, strong in popularization, widely applied to the avionics market, especially the civil avionics market, and remarkable in economic benefit.
Drawings
Fig. 1 is a flowchart illustrating a multi-partition-oriented GPU access management method.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, a method for managing access to a GPU facing multiple partitions in this embodiment includes the following steps:
step 1: and (3) initiating an initialization request to a GPU (graphics processing Unit) by the partition CPU, establishing a GPU access control semaphore by the GPU, setting a time threshold value for granting access, and turning to the step 2.
Each partition should initiate an initialization request before applying for accessing the GPU, and if the GPU has responded that other partitions have executed initialization first, the GPU will directly return success to the partition requesting initialization without repeatedly executing initialization work. The time threshold for granting authorized access is the time threshold used for the discrimination in step 4, which is the time to ensure that the CPU can complete a set of GPU access operations, typically in the order of 100 us. By using the time threshold, applications that the partition remaining time is not enough to complete a group of GPU access operations can be identified, the applications are prevented from being authorized, and the partition switching is prevented from preventing subsequent partitions from accessing the GPU. After the initialization step is completed, step 2 may be performed.
And 2, step: and (4) continuously performing graphic processing by the partition CPU, and switching to the step 3 when the GPU needs to be accessed.
In the step, the partition CPU continuously performs the graphic processing, when the command and data buffer area of the graphic drive management reaches the command and data needing to submit the graphic processing to the GPU, the GPU is required to be accessed to continue the graphic processing, and at the moment, the step 3 is shifted to apply for GPU access authority.
And step 3: and (4) the partition CPU applies for controlling GPU access control semaphore to the GPU, and the step is shifted to step 4.
The method comprises the steps of applying for GPU access authority in a mode of applying for controlling GPU access authority semaphore, wherein the semaphore for controlling GPU access is successfully obtained to indicate that access authority is obtained, and if the obtaining fails, the access authority is not obtained.
And 4, step 4: and (4) judging whether the residual time on the time slices of the partitions is greater than a time threshold value by the GPU, if so, turning to a step 5, otherwise, turning to a step 3.
In the step, the GPU obtains the residual time value of the partition time slice, when the residual time of the partition is larger than the time threshold value set in the initialization stage, the residual time of the partition is enough to finish a group of GPU access operations, if the GPU is authorized to be operated by partition access, the GPU operation can be finished before partition switching is confirmed, GPU access permission is released, and the step 5 is carried out. And if the remaining time of the partition is less than the time threshold, indicating that the risk that the GPU access operation cannot be completed before partition switching exists, refusing the permission application, and returning to the step 3 to reapply the GPU access permission.
And 5: and the GPU judges whether the GPU access control semaphore is idle, if so, the access authority is granted to the CPU of the partition, the state of the GPU access control semaphore is changed into busy, the step 6 is carried out, and otherwise, the step 3 is carried out.
Judging whether the GPU access control semaphore is idle, if so, indicating that the GPU access authority is not authorized to any partition currently, granting the access authority to the partition CPU, converting the state of the GPU access control semaphore into busy, and turning to step 6. If the semaphore is busy, the fact that the GPU access right is granted to a certain partition currently is indicated, the partition is refused to apply for GPU access, and the step 3 is carried out to reapply the GPU access right.
And 6: and (4) the GPU checks whether the memory space required by the partition CPU for operating the GPU is sufficient, if so, the step 10 is carried out, and if not, the step 7 is carried out.
This step indicates that the partition has obtained access to the GPU, and before starting to operate the GPU, a check is made as to whether the memory space required for the operation is sufficient to complete the set of operations. If the required storage space is sufficient, it indicates that the conditions required for completing a set of GPU operations are met, and the process directly proceeds to step 10 to perform the GPU access operation. If the required memory space is not sufficient, step 7 is executed to apply for the required memory space so as to achieve the conditions required for completing a group of GPU operations.
And 7: and 8, applying for the memory space required by the GPU for operation by the GPU, and turning to the step 8.
In order to guarantee time certainty, the storage space applied in the step is not allowed to be used for waiting directly, or the application is returned immediately after success, or the application is returned immediately after failure, and blocking is not allowed to wait for successful application in the step. After the step is finished, the step 8 is carried out.
And step 8: and the GPU judges whether the memory space application is successful, if so, the step 10 is carried out, and if not, the step 9 is carried out.
Judging the application result of the step 7, if the application result is successful, indicating that the step 7 applies for enough memory space required by the GPU operation, and achieving the condition of completing a group of GPU operations, and then turning to a step 10. And if the application is not successful, indicating that the GPU operation condition is not met, and turning to step 9.
And step 9: and (3) the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access permission of the partition CPU, and then shifts to the step 3.
Entering this step indicates that the partition has acquired the GPU access right, but does not have the condition to complete the GPU operation at present, and releases the semaphore and the GPU access right. And (4) turning to the step (3) to reapply the GPU access authority.
Step 10: and the partition CPU completes GPU access and operation and then proceeds to step 11.
Entering this step indicates that the partition has acquired the GPU access right and has the condition to complete the GPU operation, and submitting the instruction and data for graphics processing to the GPU to complete the GPU operation, and then the process proceeds to step 11.
Step 11: and (3) the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access authority of the partition CPU, and shifts to the step 2.
Entering the step shows that the partition successfully completes the GPU access and operation, and the step is carried out after the semaphore and the GPU access authority are released.
Claims (1)
1. A GPU access management method facing multiple partitions comprises the following steps:
step 1: initiating an initialization request to a GPU (graphics processing Unit) by a partition CPU, establishing a GPU access control semaphore by the GPU, setting a time threshold value for granting access, and turning to step 2;
step 2: the partition CPU continuously performs graphic processing, and the step 3 is carried out when the GPU needs to be accessed;
and 3, step 3: the partition CPU applies for controlling GPU access control semaphore to the GPU, and the step 4 is carried out;
and 4, step 4: the GPU judges whether the residual time on the time slices of the partitions is greater than a time threshold value, if so, the step 5 is carried out, otherwise, the step 3 is carried out;
and 5: the GPU judges whether the GPU access control semaphore is idle, if so, the GPU access control semaphore is granted access authority to the CPU of the partition, the state of the GPU access control semaphore is changed into busy, and the step 6 is carried out, otherwise, the step 3 is carried out;
step 6: the GPU checks whether the memory space required by the partition CPU for operating the GPU is sufficient, if so, the step 10 is carried out, otherwise, the step 7 is carried out;
and 7: the GPU applies for the memory space required by the operation of the GPU, and the step 8 is carried out;
and step 8: the GPU judges whether the memory space application is successful, if so, the step 10 is carried out, otherwise, the step 9 is carried out;
and step 9: the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access permission of the CPU of the partition, and then the step 3 is carried out;
step 10: the partition CPU completes GPU access and operation, and the step 11 is carried out;
step 11: and (3) the GPU changes the state of the GPU access control semaphore into idle, recovers the GPU access authority of the partition CPU, and shifts to the step 2.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103793206A (en) * | 2012-10-26 | 2014-05-14 | 辉达公司 | Work-queue-based graphics processing unit work creation |
| CN105830026A (en) * | 2013-11-27 | 2016-08-03 | 英特尔公司 | Apparatus and method for scheduling graphics processing unit workloads from virtual machines |
| CN108984264A (en) * | 2017-06-02 | 2018-12-11 | 阿里巴巴集团控股有限公司 | The implementation method of virtual GPU, apparatus and system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2003208477A1 (en) * | 2002-03-01 | 2003-09-16 | T5 Labs Ltd | Centralised interactive graphical application server |
| US7752620B2 (en) * | 2005-06-06 | 2010-07-06 | International Business Machines Corporation | Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions |
| US8068114B2 (en) * | 2007-04-30 | 2011-11-29 | Advanced Micro Devices, Inc. | Mechanism for granting controlled access to a shared resource |
| US8082426B2 (en) * | 2008-11-06 | 2011-12-20 | Via Technologies, Inc. | Support of a plurality of graphic processing units |
| US9891949B2 (en) * | 2013-03-06 | 2018-02-13 | Nvidia Corporation | System and method for runtime scheduling of GPU tasks |
| US9836418B2 (en) * | 2013-03-13 | 2017-12-05 | Dornerworks, Ltd. | System and method for deterministic time partitioning of asynchronous tasks in a computing environment |
| EP3161628B1 (en) * | 2014-06-26 | 2021-03-31 | Intel Corporation | Intelligent gpu scheduling in a virtualization environment |
-
2019
- 2019-06-24 CN CN201910549642.XA patent/CN110308992B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103793206A (en) * | 2012-10-26 | 2014-05-14 | 辉达公司 | Work-queue-based graphics processing unit work creation |
| CN105830026A (en) * | 2013-11-27 | 2016-08-03 | 英特尔公司 | Apparatus and method for scheduling graphics processing unit workloads from virtual machines |
| CN108984264A (en) * | 2017-06-02 | 2018-12-11 | 阿里巴巴集团控股有限公司 | The implementation method of virtual GPU, apparatus and system |
Non-Patent Citations (4)
| Title |
|---|
| 《Global hybrid multi-core-GPUs-resources platform (GHRP) in hard real time system》;Furkan Rabee et al.;《2014 7th International Conference on Biomedical Engineering and Informatics》;20150108;全文 * |
| 多核分区管理方法的设计与实现;郝继锋等;《计算机工程与设计》;20180216(第02期);全文 * |
| 微内核结构嵌入式实时操作系统的研究与设计;邓昀等;《微电子学与计算机》;20121005(第10期);全文 * |
| 面向航空电子的分区操作系统;李健等;《计算机工程》;20080923;全文 * |
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