CN110308598B - Array substrate, manufacturing method of array substrate and display panel - Google Patents
Array substrate, manufacturing method of array substrate and display panel Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 144
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- 239000002184 metal Substances 0.000 claims abstract description 124
- 125000006850 spacer group Chemical group 0.000 claims abstract description 45
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- 238000000034 method Methods 0.000 claims description 31
- 239000004973 liquid crystal related substance Substances 0.000 claims description 18
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- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
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- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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Abstract
The application discloses an array substrate, a manufacturing method of the array substrate and a display panel, wherein the array substrate comprises a grid metal layer and a source drain metal layer, the color resistance layer comprises a plurality of color resistances, and each color resistance is located in an area defined by two adjacent scanning lines and two adjacent data lines and extends to cover the adjacent scanning lines; the color resistor is provided with a spacer block protruding from the same side, the spacer block is positioned adjacent to one of the color resistor, the data line and the scanning line are staggered, the other side of the color resistor is sunken to form an avoiding position, and the avoiding position avoids the spacer block of the adjacent color resistor. The technical scheme of the application aims at reducing the parasitic capacitance on the data line and the scanning line, reducing the load of the data line and the scanning line, improving the charging rate of the pixels, further improving the display contrast of the product and improving the image quality grade of the product.
Description
Technical Field
The present disclosure relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a manufacturing method of the array substrate, and a display panel.
Background
Currently, a pixel structure of a VA (Vertical Alignment) display mode is divided into a pixel structure on a TFT (Thin Film Transistor) side and a pixel structure on a CF (Color Filter) side. The pixel structure on the TFT side mainly realizes the electrical function of a TFT-LCD (thin film transistor-liquid crystal display), which is a main factor determining a pixel capacitance effect, an alignment retardation effect, a gray scale voltage writing characteristic, and a retention characteristic; the CF side pixel structure mainly realizes the optical function of the TFT-LCD and is a main factor for determining the contrast and color gamut of the TFT-LCD.
However, in the conventional VA display mode pixel structure, parasitic capacitances are generated on the data lines and the scan lines, and the parasitic capacitances increase the load on the data lines and the scan lines, and reduce the charging rate of the pixels, thereby lowering the display contrast of the product and affecting the quality of the image quality of the product.
The above is only for the purpose of assisting understanding of the technical solutions of the present application, and does not represent an admission that the above is prior art.
Content of application
The main objective of this application is to provide an array substrate, aim at reducing the parasitic capacitance on the data line and on the scanning line, reduce the load of data line and scanning line, improve the charge rate of pixel, and then promote the display contrast of product, promote the image quality grade of product.
In order to achieve the above purpose, the array substrate provided by the present application includes a gate metal layer and a source drain metal layer disposed above the gate metal layer, the gate metal layer includes a plurality of scan lines disposed in parallel, the source drain metal layer includes a plurality of data lines disposed in parallel, each scan line is disposed in a staggered manner with each data line, the array substrate further includes a color resistance layer, the color resistance layer includes a plurality of color resistances, each color resistance is located in an area defined by two adjacent scan lines and two adjacent data lines, and extends to cover an adjacent portion of the scan lines;
the color resistor is provided with a spacer block protruding from the same side, the spacer block is positioned adjacent to one of the color resistor, the data line and the scanning line are staggered, the other side of the color resistor is sunken to form an avoiding position, and the avoiding position avoids the spacer block of the adjacent color resistor.
Optionally, the array substrate further includes a gate insulating layer, and the gate insulating layer is disposed between the gate metal layer and the color resistance layer;
or the grid electrode insulating layer is arranged between the color resistance layer and the source drain electrode metal layer.
Optionally, the array substrate further includes an active layer, when the color resistor is located above the active layer, the color resistor is provided with a yielding port, and the active layer is exposed from the yielding port, so that the source/drain metal layer contacts the active layer through the yielding port.
Optionally, the array substrate further includes a black matrix layer, the black matrix layer is disposed between the gate metal layer and the source and drain metal layers, and a portion of the black matrix layer is located in a crossing region of the scan line and the data line.
Optionally, the black matrix layer is disposed above the color resistance layer, and the array substrate further includes a gate insulating layer disposed between the gate metal layer and the color resistance layer;
or the grid insulating layer is arranged between the color resistance layer and the black matrix layer;
or, the grid insulation layer is arranged between the black matrix layer and the source drain metal layer.
Optionally, the color resistance layer is disposed above the black matrix layer, and the array substrate further includes a gate insulating layer disposed between the gate metal layer and the black matrix layer;
or, the grid insulating layer is arranged between the black matrix layer and the color resistance layer;
or the grid electrode insulating layer is arranged between the color resistance layer and the source drain electrode metal layer.
Optionally, the array substrate further comprises an active layer, the active layer is located between the gate metal layer and the source drain metal layer, when the black matrix layer is located above the active layer of the array substrate, an avoiding port is formed in the black matrix layer, and the active layer is exposed through the avoiding port, so that the source drain metal layer passes through the avoiding port and contacts with the active layer.
Optionally, the plurality of color resistors are a plurality of first color resistors, a plurality of second color resistors and a plurality of third color resistors, one of the first color resistors, one of the second color resistors and one of the third color resistors are sequentially arranged to form a color unit, and the plurality of color units are sequentially arranged along the extending direction of the scanning line;
or, it is a plurality of the colour hinders and divide into a plurality of first colour and hinder, a plurality of second colour and hinder, a plurality of third colour and hinder and a plurality of fourth colour and hinder, one first colour hinders, one the second colour hinders, one the third colour hinders with one the fourth colour hinders and arranges in proper order and constitutes a color unit, and is a plurality of the color unit is followed the extending direction of scanning line arranges in proper order.
The application also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate, and arranging a grid metal layer on the substrate;
arranging a grid insulating layer on the grid metal layer and the substrate base plate;
an active layer is disposed on the gate insulating layer;
arranging source and drain metal layers on the gate insulating layer and the active layer;
arranging protective layers on the source drain metal layer and the active layer; and
arranging a transparent conductive layer on the protective layer;
the method is characterized in that a colored resistance layer is further arranged after the grid metal layer is arranged on the substrate base plate and before the source drain metal layer is arranged on the substrate base plate.
The present application further provides a display panel, comprising:
a first substrate;
the second substrate is arranged opposite to the first substrate;
the liquid crystal layer is clamped between the first substrate and the second substrate;
wherein the second substrate is the array substrate of any one of claims to;
the array substrate comprises a grid metal layer and a source drain metal layer arranged above the grid metal layer, wherein the grid metal layer comprises a plurality of scanning lines arranged in parallel, the source drain metal layer comprises a plurality of data lines arranged in parallel, each scanning line and each data line are arranged in a staggered manner, the array substrate further comprises a color resistance layer, the color resistance layer comprises a plurality of color resistors, and each color resistor is positioned in an area limited by two adjacent scanning lines and two adjacent data lines and extends to cover the adjacent scanning lines;
the color resistor is provided with a spacer block protruding from the same side, the spacer block is positioned adjacent to one of the color resistor, the data line and the scanning line are staggered, the other side of the color resistor is sunken to form an avoiding position, and the avoiding position avoids the spacer block of the adjacent color resistor.
In the technical scheme of the application, in the process of manufacturing the array substrate, the process of the color resistance layer is arranged between the process of the grid metal layer and the process of the source drain metal layer, a spacer block protruding towards the same side is arranged on each color resistance, and the spacer block is located in the staggered area of the data line and the scanning line adjacent to the color resistance. Namely, in each staggered area, the spacing blocks are arranged above the scanning lines and below the data lines, so that the distance between the staggered areas of the scanning lines and the data lines is increased, the parasitic capacitance on the data lines and the parasitic capacitance on the scanning lines are reduced, the load of the data lines and the load of the scanning lines are reduced, the charging rate of pixels is improved, the display contrast of products is improved, and the image quality of the products is improved.
In order to ensure the filtering effect of the color resistors, the gap between two adjacent color resistors is small. Because the spacer block is arranged on one side of the color resistor, in order to avoid the spacer block of the adjacent color resistor, a corresponding avoidance position needs to be arranged on the other side of the color resistor.
Each color resistor in the technical scheme of the application has the separation cushion block and the avoidance position, so that the structure of each color resistor is consistent, the corresponding mask is conveniently machined and formed in the process of forming the color resistor layer, and the cost is lower.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a display panel to which a conventional array substrate is applied, along scan lines where data lines and the scan lines overlap in front;
FIG. 2 is a cross-sectional view of an embodiment of a display panel of the present application along scan lines where data lines and scan lines overlap;
FIG. 3 is a partial top view of the array substrate of FIG. 2;
FIG. 4 is a partial top view of the color resist layer of FIG. 2;
FIG. 5 is a partial top view of a color resist layer in another embodiment;
FIG. 6 is a cross-sectional view of another embodiment of a display panel of the present application along scan lines where the data lines overlap the scan lines at the front;
FIG. 7 is a partial top view of a black matrix layer according to an embodiment of the present application.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 1000 | |
813 | |
| 100 | |
8131 | |
| 10 | |
8133 | |
| 20 | |
8135 | Let a mouthful |
| 21 | |
83 | The |
| 30 | |
85 | |
| 40 | |
87 | |
| 50 | Source |
89 | |
| 51 | |
90 | |
| 53 | Source electrode | 91 | A first |
| 55 | |
911 | |
| 60 | Protective layer | 93 | The second |
| 70 | Transparent |
931 | Dodging |
| 80 | |
200 | |
| 81 | |
210 | |
| 811 | Light filter part |
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that all the directional indications (such as up, down, left, right, front, and rear … …) in the embodiment of the present application are only used to explain the relative position relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indication is changed accordingly.
In addition, the descriptions referred to as "first", "second", etc. in this application are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
With reference to fig. 2, 3 and 4, the present application provides an array substrate 100 applied to a display panel 1000, where the display panel 1000 may be a liquid crystal display panel, the liquid crystal display panel includes the array substrate 100 and a color filter substrate 200, the color filter substrate 200 is disposed opposite to the array substrate 100, and a liquid crystal layer is disposed between the color filter substrate 200 and the array substrate 100. According to the technical scheme, the position of the color resistance layer 80 and the structure of the color resistance 81 on the color resistance layer 80 are improved, so that the parasitic capacitance generated by the data line 51 and the scanning line 21 on the array substrate 100 is reduced, the load of the data line 51 and the scanning line 21 is reduced, the charging rate of pixels is improved, the display contrast of a product is improved, and the image quality grade of the product is improved.
In the embodiment of the present application, the array substrate 100 includes a gate metal layer 20 and a source drain metal layer 50 disposed above the gate metal layer 20, the gate metal layer 20 includes a plurality of scan lines 21 disposed in parallel, the source drain metal layer 50 includes a plurality of data lines 51 disposed in parallel, each scan line 21 is disposed in a staggered manner with each data line 51, the array substrate 100 further includes a color resistance layer 80, the color resistance layer 80 includes a plurality of color resistors 81, and each color resistor 81 is located in an area defined by two adjacent scan lines 21 and two adjacent data lines 51 and extends to cover an adjacent portion of the scan line 21;
the color resistor 81 has a spacer block 8131 protruding from the same side of the color resistor 81, the spacer block 8131 is located in a crossing region of one data line 51 and one scanning line 21 adjacent to the color resistor 81, an avoiding position 8133 is concavely disposed on the other side of the plurality of color resistors 81, and the avoiding position 8133 avoids the spacer block 8131 of the adjacent color resistor.
In this embodiment, the array substrate 100 further includes a substrate 10, a gate insulating layer 30, an active layer 40, a protective layer 60, and a transparent conductive layer 70. The substrate 10, the gate metal layer 20, the gate insulating layer 30, the active layer 40, the source-drain metal layer 50, the protective layer 60, and the transparent conductive layer 70 are sequentially disposed. The concrete structure is as follows: the gate metal layer 20 is arranged on the substrate 10; the gate insulating layer 30 is arranged on the gate metal layer 20 and the substrate base plate 10 and covers the gate metal layer 20 and the substrate base plate 10; the active layer 40 is arranged on the gate insulating layer 30 and is positioned above the gate metal layer 20; the source and drain metal layer 50 is disposed on the gate insulating layer 30 and the active layer 40, and contacts the active layer 40; the protective layer 60 is arranged on the gate insulating layer 30, the active layer 40 and the source/drain metal layer 50, and covers the gate insulating layer 30, the active layer 40 and the source/drain metal layer 50; the transparent conductive layer 70 is disposed on the protective layer 60 and is in contact with the source/drain metal layer 50 (specifically, the transparent conductive layer 70 may be in contact with the source/drain metal layer 50 through a through hole on the protective layer 60). At this time, the scan line 21 in the gate metal layer 20 and the data line 51 in the source-drain metal layer 50 are overlapped, that is, there is a region overlapping with the front of the data line 51 on the scan line 21, and there is a region overlapping with the front of the scan line 21 on the data line 51. The area between the area of the scan line 21 overlapped with the front of the data line 51 and the area of the data line 51 overlapped with the front of the area is the crossing area of the scan line 21 and the data line 51. It should be noted that the array substrate 100 includes a plurality of data lines 51 and a plurality of scan lines 21, and each data line 51 is disposed to overlap each scan line 21, that is, there are a plurality of such interlaced regions on the array substrate 100.
It is understood that each scan line 21 and each data line 51 are defined herein as being staggered, and specifically, each scan line 21 and each data line 51 intersect with each other in a projection onto the substrate 10 and are perpendicular to each other.
In the technical scheme of the present application, in the process of manufacturing the array substrate 100, the process of the color resistor layer 80 is set between the process of the gate metal layer 20 and the process of the source/drain metal layer 50, and a spacer 8131 protruding toward the same side is disposed on each color resistor 81, and the spacer 8131 is located in the staggered area of one data line 51 and one scan line 21 adjacent to the color resistor 81. That is, in each interleaving region, the spacer block 8131 is disposed above the scan line 21 and below the data line 51, so that the distance between the interleaving regions of the scan line 21 and the data line 51 is increased, the parasitic capacitance on the data line 51 and the scan line 21 is reduced, the load on the data line 51 and the scan line 21 is reduced, the charging rate of the pixel is improved, the display contrast of the product is improved, and the image quality of the product is improved.
In order to ensure the filtering effect of the color resistors 81, the gap between two adjacent color resistors 81 is small. Since the spacer 8131 is disposed on one side of the color resistor 81, in order to avoid the spacer 8131 of the adjacent color resistor 81, a corresponding avoidance position 8133 needs to be disposed on the other side of the color resistor 81.
Optionally, each color resistor in the technical scheme of the application has a spacer block and an avoidance position, so that the structure of each color resistor is consistent, the corresponding mask is conveniently machined and formed in the process of forming the color resistor layer, and the cost is low.
In the practical application process of the array substrate 100 according to the technical scheme of the application, not only parasitic capacitance is generated between the data line 51 and the scan line 21, but also parasitic capacitance is generated between the data line 51 and the scan line 21 and the conductive thin film 210 on the color filter substrate 200, and the conductive thin film 210 is disposed on the surface of the color filter substrate 200 facing the array substrate 100.
The parasitic capacitance generated on the data line 51 is defined as CdThe parasitic capacitance generated on the data line 51 mainly includes the following two parts:
1) parasitic capacitance, denoted as C, generated by the overlap of the data line 51 and the scan line 21d1；
2) A parasitic capacitance C generated by the overlap of the data line 51 and the front surface of the conductive film 210 on the color filter substrate 200 is recordedd2；
The parasitic capacitance generated on the scan line 21 is defined as CgThe parasitic capacitance generated on the scanning line 21 mainly includes the following two components:
3) parasitic capacitance, denoted as C, generated by the overlap of the scan line 21 and the data line 51g1；
4) A parasitic capacitance C generated by the overlap of the scan line 21 and the front surface of the conductive film 210 on the color filter substrate 200 is recordedg2。
The following mainly illustrates the parasitic capacitance on the data line 51, and the specific principle is as follows:
the dielectric constant of the liquid crystal layer (not shown) is defined as α, the dielectric constant of the protective layer 60 is defined as β, the dielectric constant of the gate insulating layer 30 is defined as γ, and the dielectric constant of the color resist layer 80 is defined as δ.
The capacitance is calculated as:
(where ξ is the dielectric constant, S is the overlap area, k is the electrostatic force constant, and d is the relative distance).
The series equation for the capacitance is:
the parallel equation of the capacitors is:
C3＝C1+C2；
fig. 1 shows a modified scheme, where the overlapping area of the data line 51 and the scan line 21 is S, and the overlapping area of the data line 51 and the conductive film 210 is also S; the relative distance between the data line 51 and the scan line 21 is d3(ii) a In the crossing region of the conductive film 210 and the data line 51, the distance between the conductive film 210 and the passivation layer 60 is d1(ii) a In the crossing region of the conductive film 210 and the data line 51, the distance between the conductive protection layer 60 and the data line 51 is d2. The specific calculation method is as follows:
(1) the parasitic capacitance generated by the overlap of the data line 51 and the scan line 21 is Cd11：
(2) The parasitic capacitance generated by the overlap of the data line 51 and the front surface of the conductive film 210 on the color filter substrate 200 side is: cd21
Referring to fig. 2, in an embodiment after the modification of the present application, when the process of the color resist layer 80 is disposed between the process of the gate metal layer 20 and the process of the source/drain 55 technology layer, the spacer 8131 is located in the crossing region of the data line 51 and the scan line 21. The overlapping area of the data line 51 and the scanning line 21 is S, in accordance with before the improvement. Since the overall thickness of the display panel 1000 is constant, the distance between the conductive film 210 and the passivation layer 60 is d in FIG. 21-d5In FIG. 2, the relative distance between the data line 51 and the scan line 21 is d3+d5The matrix calculation method is as follows:
(1) the data line 51 and the scan line 21 overlapParasitic capacitance of Cd12：
(2) The parasitic capacitance generated by the overlap of the data line 51 and the front surface of the conductive thin film 210 on the color filter substrate 200 side is Cd22：
The parasitic capacitances between the data line 51 and the scan line 21 before and after the improvement are differentiated to obtain Δ 1:
the parasitic capacitance between the data line 51 and the conductive film 210 on the color filter substrate 200 side before and after the improvement is differentiated to obtain Δ 2:
in summary, after the improvement, the parasitic capacitance between the data line 51 and the scan line 21 is reduced, and the parasitic capacitance between the data line 51 and the conductive thin film 210 on the film substrate 200 side is increased.
Alternatively, now using general parameters, the actual scaling of Δ 1 and Δ 2 is performed as follows:
(1) the dielectric constants of the protective layer 60 and the gate insulating layer 30 are generally about 6.75, that is, β ═ γ ═ 6.75;
(2) the dielectric constant of the liquid crystal layer is generally between 3.5 and 7, namely alpha is 3.5 to 7;
(3) the dielectric constant of the color resist layer 80 is generally about 3.6, i.e., δ is 3.6.
(4)d1Generally about 4.25 μm, and d1＝4.25；
(5)d2Typically around 1.9 μm (of which,PV1 of about 0.2 μm and PV2 of about 1.7 μm), let d2 be 1.9;
(6)d3generally about 0.4 μm, and d3＝0.4；
(7)d5Generally about 2.5 μm, and d5＝2.5。
Easy calculation:
that is to say that the first and second electrodes,
therefore, no matter what the dielectric constant of the liquid crystal layer is (3.5-7), the absolute value of Δ 1 is much larger than that of Δ 2; that is, the amount of reduction of the parasitic capacitance caused by the overlap of the improved data line 51 and the front surface of the scan line 21 is much larger than the amount of increase of the parasitic capacitance caused by the overlap of the improved data line 51 and the front surface of the conductive film 210 on the color filter substrate 200 side.
That is, the technical solution of this embodiment can greatly reduce the parasitic capacitance on the data line 51, and reduce the load of the data line 51.
Similarly, a similar analysis can be performed for the parasitic capacitance on the scan line 21, and the following can be obtained: the technical scheme of the embodiment can greatly reduce the parasitic capacitance on the scanning line 21 and reduce the load of the scanning line 21.
In summary, the parasitic capacitance on the scan line 21 and the data line 51 is reduced, the load on the scan line 21 and the data line 51 is reduced, the charging rate of the pixel is improved, the display contrast of the product is improved, and the quality of the image of the product is improved.
In the embodiment of the present application, the color filter 81 includes a light filter portion 811 and a spacer portion 813 connected to the light filter portion 811, the light filter portion 811 and the spacer portion 813 are arranged along the extending direction of the data line 51, the spacer portion 813 covers the adjacent portion of the scan line 21, the spacer block 8131 is formed by extending the spacer portion 813 along the extending direction of the scan line 21, and the avoiding portion 8133 is formed by recessing the spacer portion 813 along the extending direction of the scan line 21.
In this embodiment, the filter portions 811 and the spacer portions 813 of the color resists 81 are sequentially arranged at intervals along one extending direction of the data lines 51. The filter portion 811 of each color resistor 81 is used for filtering white light emitted from the backlight source, so as to transmit light of different colors; the filter 811 of each color filter 81 is not only used to prevent light leakage, but also used to cover a portion of the scan line 21, so that the parasitic capacitance between the scan line 21 and the data line 51 is reduced.
Referring to fig. 4, in an embodiment, the color resistors 81 include a plurality of first color resistors 83, a plurality of second color resistors 85, and a plurality of third color resistors 87, one of the first color resistors 83, one of the second color resistors 85, and one of the third color resistors 87 are sequentially arranged to form a color unit, and the color units are sequentially arranged along the extending direction of the scan line 21.
The color unit is a color resistor 81 corresponding to each pixel unit, i.e., each pixel unit in the embodiment includes a first color resistor 83, a second color resistor 85 and a third color resistor 87.
In this embodiment, each color unit is composed of a first color resistor 83, a second color resistor 85 and a third color resistor 87 arranged in sequence, and the first color resistor 83, the second color resistor 85 and the third color resistor 87 can respectively filter one of red light, green light and blue light.
Referring to fig. 5, in an embodiment, the color resistors 81 are divided into a plurality of first color resistors 83, a plurality of second color resistors 85, a plurality of third color resistors 87, and a plurality of fourth color resistors 89, one of the first color resistors 83, one of the second color resistors 85, one of the third color resistors 87, and one of the fourth color resistors 89 are sequentially arranged to form a color unit, and the plurality of color units are sequentially arranged along the extending direction of the scan line 21. In this embodiment, each pixel unit includes a first color resistor 83, a second color resistor 85, a third color resistor 87 and a fourth color resistor 89.
In this embodiment, each color unit is composed of a first color resistor 83, a second color resistor 85, a third color resistor 87 and a fourth color resistor 89, which are sequentially arranged, and the first color resistor 83, the second color resistor 85, the third color resistor 87 and the fourth color resistor 89 can respectively filter and obtain one of red light, green light, blue light and white light.
Therefore, the color resistance layer 80 is convenient to form, the array substrate 100 is convenient to manufacture, and the reliability and the stability of the array substrate 100 are improved; meanwhile, the technical scheme of the present application can also be applied to the array substrate 100 in which a color unit is formed by R, G, B, W four colors, so that the applicability of the technical scheme of the present application is enhanced.
In the embodiment of the present application, the array substrate 100 further includes a gate insulating layer 30, where the gate insulating layer 30 is disposed between the gate metal layer 20 and the color resistance layer 80, or the gate insulating layer 30 is disposed between the color resistance layer 80 and the source drain metal layer 50. Both embodiments are within the scope of the present application.
In an embodiment, the array substrate 100 further includes an active layer 40, the active layer 40 is located between the gate metal layer 20 and the source/drain metal layer 50, when the color resistor 81 is located above the active layer 40, the color resistor 81 is provided with a relief port 8135, and the active layer 40 is exposed from the relief port 8135, so that the source/drain metal layer 50 contacts the active layer 40 through the relief port 8135. Specifically, the spacer portion 813 of the color resistor 81 is provided with a yielding hole 8135.
In this embodiment, when the process of the color resist layer 80 is between the process of the active layer 40 and the process of the source/drain metal layer 50, the space portion 813 of the color resist layer 80 is opened with the recess 8135, the active layer 40 is exposed from the recess 8135, and the source 53 and the drain 55 of the source/drain metal layer 50 can pass through the recess 8135 and contact the active layer 40. Therefore, the connection between the active layer 40 and the source/drain metal layer 50 is simpler, more convenient and more reliable, and the performance of the array substrate 100 is more stable.
In an embodiment of the array substrate 100 of the present application, a projection of the active layer 40 on the color resistance layer 80 is located within the range of the offset 8135. That is, the active layer 40 is entirely within the coverage of the relief port 8135. In this way, the exposed area of the active layer 40 is increased, and the connection between the source and drain electrodes 53 and 55 and the active layer 40 in the source and drain metal layer 50 is further facilitated.
In an embodiment of the array substrate 100 of the present application, the peripheral edge of the position-letting hole 8135 is disposed adjacent to the peripheral edge of the active layer 40. Therefore, the distance between the source electrode 53 and the drain electrode 55 outside the edge of the active layer 40 and the gate metal layer 20 can be further increased, and the parasitic capacitance on the source electrode 53, the drain electrode 55 and the gate metal layer 20 can be reduced, so that the parasitic capacitance on the scanning line 21 and the data line 51 can be further reduced, the load of the scanning line 21 and the data line 51 can be reduced, the charging rate of the pixel can be improved, and the display contrast of the product and the image quality of the product can be finally improved.
In an embodiment of the array substrate 100 of the present application, the array substrate 100 further includes a black matrix layer 90, and a portion of the black matrix layer 90 is located in an intersection region of the scan line 21 and the data line 51.
In this embodiment, the process of the black matrix layer 90 is between the process of the gate metal layer 20 and the process of the source/drain metal layer 50, so that the black matrix layer 90 can be partially located in the crossing region of the scan line 21 and the data line 51.
Similar to the technical solution of the foregoing embodiment in which the color resist layer 80 is disposed between the gate metal layer 20 and the source/drain metal layer 50, in the technical solution of this embodiment, the black matrix layer 90 is further disposed between the gate metal layer 20 and the source/drain metal layer 50.
Similar to the demonstration of "the parasitic capacitance on the data line 51 and the scan line 21 is reduced" in the previous embodiment, the arrangement of the black matrix layer 90 in this embodiment can also increase the distance between the scan line 21 and the data line 51 at the crossing region. At this time, since the distance between the scanning line 21 and the data line 51 in the interlaced region is increased, the parasitic capacitance on the data line 51 and the scanning line 21 is reduced, so that the load of the data line 51 and the scanning line 21 is reduced, the charging rate of the pixel is improved, the display contrast of the product is improved, and the image quality of the product is improved.
The specific principle is as follows:
the dielectric constant of the liquid crystal layer is defined as α, the dielectric constant of the protective layer 60 is defined as β, the dielectric constant of the gate insulating layer 30 is defined as γ, the dielectric constant of the color resist layer 80 is defined as δ, and the dielectric constant of the black matrix layer 90 is defined as η.
According to the calculation formula of the capacitance
(where ξ is the dielectric constant, S is the overlap area, k is the constant of the electrostatic force, and d is the relative distance), and a parallel equation C of the capacitance3＝C1+C2And series connection formula of capacitors
Fig. 1 shows the scheme before modification, in order to calculate the following conclusions in the above example:
(1) the parasitic capacitance generated by the overlap of the data line 51 and the scan line 21 is Cd11：
(2) The parasitic capacitance generated by the overlap of the data line 51 and the front surface of the conductive film 210 on the side of the color filter substrate 200 is Cd21：
Referring to fig. 6, in an improved embodiment of the present invention, the process of the color-resist layer 80 and the process of the black matrix layer 90 are both disposed on the gate metal layer20 and the source drain 55 technology layer. The overlapping area of the data line 51 and the scanning line 21 is S, in accordance with before the improvement. Since the overall thickness of the display panel 1000 is constant, the distance between the conductive film 210 and the passivation layer 60 is d in FIG. 51-d5In FIG. 5, the relative distance between the data line 51 and the scan line 21 is d3+d6+d5The matrix calculation method is as follows:
(1) the parasitic capacitance generated by the overlap of the data line 51 and the scan line 21 is Cd13：
Because of this, it is possible to reduce the number of the,
therefore, the first and second electrodes are formed on the substrate,
(2) the parasitic capacitance generated by the overlap of the data line 51 and the front surface of the conductive film 210 on the side of the color filter substrate 200 is Cd23：
The parasitic capacitances between the data line 51 and the scan line 21 before and after the improvement are differentiated to obtain Δ 3:
thus, compared before and after the improvement, it is possible to obtain:
the parasitic capacitance between the data line 51 and the conductive film 210 on the color filter substrate 200 side before and after the improvement is differentiated to obtain Δ 4:
in summary, after the improvement, the parasitic capacitance generated by the overlap of the data line 51 and the scan line 21 is reduced, and then the parasitic capacitance generated by the overlap of the data line 51 and the front surface of the conductive thin film 210 on the color filter substrate 200 side is increased.
Alternatively, now using general parameters, the actual scaling of Δ 3 and Δ 4 as described above is performed as follows:
(1) the dielectric constants of the protective layer 60 and the gate insulating layer 30 are generally about 6.75, that is, β ═ γ ═ 6.75;
(2) the dielectric constant of the liquid crystal layer is generally between 3.5 and 7, namely alpha is 3.5 to 7;
(3) the dielectric constants of the color resist layer 80 and the black matrix layer 90 are generally about 3.6, that is, δ η 3.6.
(4) d1 is generally about 4.25 μm, where d1 is 4.25;
(5) d2 is generally around 1.9 μm (of which PV1 is around 0.2 μm and PV2 is around 1.7 μm), and the notation d2 is 1.9;
(6) d3 is generally about 0.4 μm, and d3 is 0.4;
(7) d5 is generally about 2.5 μm, and d5 is 2.5;
(8) d6 is generally about 1 μm, and d6 is 1.
Easy calculation:
that is to say that the first and second electrodes,
therefore, no matter what the dielectric constant of the liquid crystal layer is (3.5-7), the absolute value of delta 3 is far larger than that of delta 4; that is, the amount of reduction of the parasitic capacitance caused by the overlap of the improved data line 51 and the front surface of the scan line 21 is much larger than the amount of increase of the parasitic capacitance caused by the overlap of the improved data line 51 and the front surface of the conductive film 210 on the color filter substrate 200 side.
That is, the technical solution of this embodiment can greatly reduce the parasitic capacitance on the data line 51, and reduce the load of the data line 51.
Similarly, a similar analysis can be performed for the parasitic capacitance on the scan line 21, and the following can be obtained: the technical scheme of the embodiment can greatly reduce the parasitic capacitance on the data line 51 and reduce the load of the data line 51.
In summary, the technical solution of the present embodiment can reduce the parasitic capacitance on the scan line 21 and the data line 51, so as to reduce the load on the scan line 21 and the data line 51, and improve the charging rate of the pixel, thereby improving the display contrast of the product and improving the quality of the image quality of the product.
In the embodiment of the present application, the black matrix layer 90 is disposed above the color resistance layer, the array substrate 100 further includes a gate insulating layer 30, and the gate insulating layer 30 is disposed between the gate metal layer 20 and the color resistance layer 80;
alternatively, the gate insulating layer 30 is disposed between the color resist layer 80 and the black matrix layer 90;
alternatively, the gate insulating layer 30 is disposed between the black matrix layer 90 and the source/drain metal layer 50.
In the embodiment of the present invention, the color resistance layer 80 is disposed above the black matrix layer 90, the array substrate 100 further includes a gate insulating layer 30, and the gate insulating layer 30 is disposed between the gate metal layer 20 and the black matrix layer 90;
alternatively, the gate insulating layer 30 is disposed between the black matrix layer 90 and the color resist layer 80;
alternatively, the gate insulating layer 30 is disposed between the color resist layer 80 and the source/drain metal layer 50.
In summary, when the color resist layer 80 and the black matrix layer 90 are located between the gate metal layer 20 and the source/drain metal layer 50, the embodiments of different combinations that can be obtained are all within the scope of the present application.
The color-resist layer 80 and the black matrix layer 90 are defined as being located between the gate metal layer 20 and the source/drain metal layer 50, which means that the process of the color-resist layer 80 and the process of the black matrix layer 90 are performed after the process of the gate metal layer 20 and before the process of the source/drain metal layer 50.
In an embodiment of the array substrate 100 of the present application, the black matrix layer 90 includes a plurality of first light-shielding portions 91 arranged corresponding to the plurality of data lines 51, and a plurality of second light-shielding portions 93 arranged corresponding to the scan lines 21, the projection of the data lines 51 on the black matrix layer 90 falls into the range of the first light-shielding portions 91, the projection of the scan lines 21 on the black matrix layer 90 falls into the range of the second light-shielding portions, and a plurality of light-transmitting regions 911 are enclosed by the plurality of first light-shielding portions 91 and the plurality of second light-shielding portions 93.
Each color resistor 81 on the color resistor layer 80 is disposed corresponding to each light transmission region 911, and the light shielding part on each color resistor 81 at least covers the corresponding light transmission region 911. The first light-shielding portion 91 and the second light-shielding portion 93 can not only shield the circuit on the array substrate 100, but also prevent color mixing between adjacent color resists 81. The second light shielding portion 93 further ensures the increase of the distance between the scanning line 21 and the data line 51 at the intersection region, i.e. the increase of the distance between the scanning line 21 and the data line 51 at the overlapping position, and has the advantages of simple structure, convenience for molding and manufacturing, and excellent stability and reliability.
Referring to fig. 7, in an embodiment of the array substrate 100 of the present application, when the black matrix layer 90 is located above the active layer 40 of the array substrate 100, the black matrix layer 90 is provided with an avoiding opening 931 for the active layer 40 to contact with the source/drain metal layer 50. Specifically, the second light-shielding portion 93 of the black matrix layer 90 is provided with an avoiding opening 931
That is, when the process of the black matrix layer 90 is between the process of the active layer 40 and the process of the source/drain metal layer 50, the surface of the second light shielding portion 93 of the black matrix layer 90 corresponding to the active layer 40 is provided with an avoiding opening 931. At this time, if the color resist layer 80 is also located above the active layer 40, the relief opening 931 also penetrates the color resist layer 80, so that the active layer 40 is exposed from the relief opening 931. At this time, the source electrode 53 and the drain electrode 55 of the source-drain metal layer 50 may contact the active layer 40 through the black matrix layer 90 and the color resistance layer 80. If the color resist layer 80 is not located above the active layer 40, the recess 931 does not need to penetrate through the color resist layer 80, and the active layer 40 can be directly exposed by the recess 931, and the source 53 and the drain 55 in the source/drain metal layer 50 can directly penetrate through the recess 931 to contact the active layer 40.
Therefore, the connection between the active layer 40 and the source/drain metal layer 50 is simpler, more convenient and more reliable, and the performance of the array substrate 100 is more stable.
In an embodiment of the array substrate 100 of the present application, the projection of the gate metal layer 20 on the black matrix layer 90 covers the range of the avoiding opening 931. That is, the coverage of the relief opening 931 on the substrate base plate 10 falls within the coverage of the gate metal layer 20 on the substrate base plate 10. Therefore, the light shielding at the avoiding opening 931 can be completed by the gate metal layer 20, which can block light from penetrating through the avoiding opening 931, thereby preventing light leakage and ensuring the display performance of the array substrate and the display panel 1000.
The present application further provides a manufacturing method of the array substrate 100, which includes the following steps:
providing a substrate 10, and arranging a gate metal layer 20 on the substrate 10;
a gate insulating layer 30 is arranged on the gate metal layer 20 and the substrate base plate 10;
an active layer 40 is disposed on the gate insulating layer 30;
a source drain metal layer 50 is arranged on the gate insulating layer 30 and the active layer 40;
a protective layer 60 is arranged on the source drain metal layer 50 and the active layer 40; and
providing a transparent conductive layer 70 on the protective layer 60;
after the gate metal layer 20 is disposed on the substrate 10 and before the source/drain metal layer 50 is disposed on the substrate 10, a color resist layer 80 is further disposed.
The color resist layer 80 may be disposed above the gate insulating layer 30, or may be disposed below the gate insulating layer 30.
Optionally, after the gate metal layer 20 is disposed on the substrate 10 and before the source-drain metal layer 50 is disposed on the substrate 10, a black matrix layer 90 is further disposed on the corresponding structural layer.
The color resist layer 80 and the black matrix layer 90 may be disposed above the gate insulating layer 30, below the gate insulating layer 30, or above and below the gate insulating layer 30, respectively. Between the color resist layer 80 and the black matrix layer 90, the color resist layer 80 may be disposed above the black matrix layer 90, or the black matrix layer 90 may be disposed above the color resist layer 80
The present application further proposes a display panel 1000, comprising:
a first substrate;
the second substrate is arranged opposite to the first substrate;
a liquid crystal layer (not shown) interposed between the first substrate and the second substrate;
the second substrate is the array substrate 100 as described above, and the specific structure of the array substrate 100 refers to the above embodiments, and since the display panel 1000 adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by all the technical solutions of all the above embodiments are achieved, and are not repeated herein. The first substrate is a color filter substrate 200, and a conductive film 210 is disposed on a surface of the first substrate facing the second substrate (the array substrate 100).
Alternatively, the display panel 1000 of the present application may be applied to a display device, and the display device may be a display, a television, a mobile phone, a tablet computer, or other display devices.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that can be directly or indirectly applied to other related fields without departing from the spirit of the present application are intended to be included in the scope of the present application.
Claims (10)
1. An array substrate comprises a grid metal layer and a source drain metal layer arranged above the grid metal layer, wherein the grid metal layer comprises a plurality of scanning lines arranged in parallel, the source drain metal layer comprises a plurality of data lines arranged in parallel, each scanning line and each data line are arranged in a staggered mode, the array substrate is characterized by further comprising a color resistance layer, each color resistance layer comprises a plurality of color resistances, and each color resistance is located in an area defined by two adjacent scanning lines and two adjacent data lines and extends to cover the adjacent scanning lines;
the other sides of the color resistors are concavely provided with avoidance positions, and the avoidance positions avoid the spacing blocks of the adjacent color resistors;
the color resistance comprises a light filtering part and a spacer part connected with the light filtering part, the light filtering part and the spacer part are arranged along the extending direction of the data line, the spacer part covers the adjacent part of the scanning line, the spacer block is arranged along the spacer part along the extending direction of the scanning line, and the avoiding position is formed by the spacer part along the extending direction of the scanning line in a concave mode.
2. The array substrate of claim 1, further comprising a gate insulating layer disposed between the gate metal layer and the color resist layer;
or the grid electrode insulating layer is arranged between the color resistance layer and the source drain electrode metal layer.
3. The array substrate of claim 1, further comprising an active layer, wherein when the color resistor is located above the active layer, the color resistor is provided with a relief opening, and the active layer is exposed from the relief opening, so that the source/drain metal layer contacts the active layer through the relief opening.
4. The array substrate of claim 1, further comprising a black matrix layer disposed between the gate metal layer and the source drain metal layer, wherein a portion of the black matrix layer is located in a crossing region of the scan line and the data line.
5. The array substrate of claim 4, wherein the black matrix layer is disposed over the color resist layer, the array substrate further comprising a gate insulating layer disposed between the gate metal layer and the color resist layer;
or the grid insulating layer is arranged between the color resistance layer and the black matrix layer;
or, the grid insulation layer is arranged between the black matrix layer and the source drain metal layer.
6. The array substrate of claim 4, wherein the color resistance layer is disposed above the black matrix layer, the array substrate further comprising a gate insulating layer disposed between the gate metal layer and the black matrix layer;
or, the grid insulating layer is arranged between the black matrix layer and the color resistance layer;
or the grid electrode insulating layer is arranged between the color resistance layer and the source drain electrode metal layer.
7. The array substrate of claim 4, further comprising an active layer, wherein the active layer is located between the gate metal layer and the source/drain metal layer, and when the black matrix layer is located above the active layer of the array substrate, an avoiding opening is formed in the black matrix layer, and the active layer is exposed from the avoiding opening, so that the source/drain metal layer is in contact with the active layer through the avoiding opening.
8. The array substrate of any of claims 1 to 7, wherein the plurality of color resistors are a plurality of first color resistors, a plurality of second color resistors and a plurality of third color resistors, one of the first color resistors, one of the second color resistors and one of the third color resistors are sequentially arranged to form a color unit, and the plurality of color units are sequentially arranged along the extending direction of the scan line;
or, it is a plurality of the colour hinders and divide into a plurality of first colour and hinder, a plurality of second colour and hinder, a plurality of third colour and hinder and a plurality of fourth colour and hinder, one first colour hinders, one the second colour hinders, one the third colour hinders with one the fourth colour hinders and arranges in proper order and constitutes a color unit, and is a plurality of the color unit is followed the extending direction of scanning line arranges in proper order.
9. The manufacturing method of the array substrate is characterized by comprising the following steps:
providing a substrate, and arranging a grid metal layer on the substrate;
arranging a grid insulating layer on the grid metal layer and the substrate base plate;
an active layer is disposed on the gate insulating layer;
arranging source and drain metal layers on the gate insulating layer and the active layer;
arranging protective layers on the source drain metal layer and the active layer; and
arranging a transparent conductive layer on the protective layer;
the grid metal layer comprises a plurality of scanning lines arranged in parallel, the source and drain metal layer comprises a plurality of data lines arranged in parallel, and each scanning line and each data line are arranged in a staggered mode;
the method is characterized in that a colored resistance layer is further arranged after the grid metal layer is arranged on the substrate base plate and before the source drain metal layer is arranged on the substrate base plate; the color resistance layer comprises a plurality of color resistances, and each color resistance is positioned in an area defined by two adjacent scanning lines and two adjacent data lines and extends to cover the adjacent scanning lines;
the other sides of the color resistors are concavely provided with avoidance positions, and the avoidance positions avoid the spacing blocks of the adjacent color resistors;
the color resistance comprises a light filtering part and a spacer part connected with the light filtering part, the light filtering part and the spacer part are arranged along the extending direction of the data line, the spacer part covers the adjacent part of the scanning line, the spacer block is arranged along the spacer part along the extending direction of the scanning line, and the avoiding position is formed by the spacer part along the extending direction of the scanning line in a concave mode.
10. A display panel, comprising:
a first substrate;
the second substrate is arranged opposite to the first substrate;
the liquid crystal layer is clamped between the first substrate and the second substrate;
wherein the second substrate is the array substrate of any one of claims 1 to 8.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105607368A (en) * | 2016-01-04 | 2016-05-25 | 重庆京东方光电科技有限公司 | Array substrate, preparing method thereof and display device |
| CN106353944A (en) * | 2016-11-04 | 2017-01-25 | 京东方科技集团股份有限公司 | Array base plate, manufacturing method of array base plate, display panel and display device |
| CN107942595A (en) * | 2017-12-21 | 2018-04-20 | 惠科股份有限公司 | Array substrate and manufacturing method thereof, liquid crystal display panel and manufacturing method thereof |
| CN207742427U (en) * | 2017-12-21 | 2018-08-17 | 惠科股份有限公司 | Array substrate and liquid crystal display panel |
| CN108983518A (en) * | 2018-07-23 | 2018-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105607368A (en) * | 2016-01-04 | 2016-05-25 | 重庆京东方光电科技有限公司 | Array substrate, preparing method thereof and display device |
| CN106353944A (en) * | 2016-11-04 | 2017-01-25 | 京东方科技集团股份有限公司 | Array base plate, manufacturing method of array base plate, display panel and display device |
| CN107942595A (en) * | 2017-12-21 | 2018-04-20 | 惠科股份有限公司 | Array substrate and manufacturing method thereof, liquid crystal display panel and manufacturing method thereof |
| CN207742427U (en) * | 2017-12-21 | 2018-08-17 | 惠科股份有限公司 | Array substrate and liquid crystal display panel |
| CN108983518A (en) * | 2018-07-23 | 2018-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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