CN110308387B

CN110308387B - Testing and automatic correcting method for verifying emptiness of assertion in form, storage medium and terminal

Info

Publication number: CN110308387B
Application number: CN201910585118.8A
Authority: CN
Inventors: 袁军
Original assignee: Chengdu Arcas Microelectronics Technology Co ltd
Current assignee: Chengdu Arcas Microelectronics Technology Co ltd
Priority date: 2019-07-01
Filing date: 2019-07-01
Publication date: 2021-03-23
Anticipated expiration: 2039-07-01
Also published as: CN113049948B; CN113075537B; CN113075537A; CN110308387A; CN113049948A

Abstract

The invention relates to a testing and automatic correcting method for verifying the emptiness of an assertion in a form, a storage medium and a terminal, wherein the method comprises the following steps: and setting each sub-expression of the assertion to be 0 and 1 respectively, then carrying out integrated and automaton minimization processing, and if the two obtained results are the same, determining that the assertion has space-time property. The invention is based on the most extensive space-general definition, and the integrity of the test is increased; meanwhile, due to the comprehensive process and the minimum determinability, the two results only need to be compared in structure, and the efficiency is high.

Description

Testing and automatic correcting method for verifying emptiness of assertion in form, storage medium and terminal

Technical Field

The invention relates to a testing and automatic correcting method for verifying the emptiness of an assertion in a form, a storage medium and a terminal.

Background

Formal verification is a chip functional verification technology based on logic modeling and mathematical reasoning proof, is a supplement to traditional simulation verification and is replacing simulation in many scenarios. Due to the uniqueness of formal verification techniques, there are many obstacles to their application in chip design verification processes, the first is how to generate correct and accurate assertions. Assertions are divided into constraints and attributes. The former defines the input environment of the design under test and the latter is a formal verification object-i.e. whether these properties hold under all the operating states and operating paths of the design allowed by the input constraints.

Due to the complexity and high expressive power of assertion languages, and the interaction between assertions and the design under test, assertions often hide semantics that some developers are unaware of, the most common of which is spaciousness. Assertions with emptiness tend to either surface that the assertions themselves are not accurate enough or that the interaction between the assertions and the design presents problems. The current commercial formal verification tools only test for one type of space-time, namely causal space-time. In the A-B form of assertions, if A does not hold, there is no relationship between the hold of the whole assertion and the hold of B. The failure of A is not expected from the assertion itself, and the test for whether B is true is not performed because A is not. Existing tools perform two verifications for a causal form of an assertion, one is the reachability of a, i.e., a can be established. Second is whether the entire assertion holds. The assertion in the case where a is unreachable is referred to as the assertion of the null. This approach has two problems. First it addresses only causal null-flooding, lacking integrity. The second is that it will be validated twice per assertion, reducing efficiency.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a test and automatic correction method for verifying the emptiness of an assertion in a formal mode, a storage medium and a terminal.

The purpose of the invention is realized by the following technical scheme:

the invention provides a testing and automatic correcting method for verifying the emptiness of an assertion in a form, which comprises the following steps:

and setting each sub-expression of the assertion to be 0 and 1 respectively, then carrying out integrated and automaton minimization processing, and if the two obtained results are the same, determining that the assertion has space-time property.

Further, the method further comprises:

adding the logic circuit into the assertion to form a new assertion;

and setting each sub-expression of the new assertion as 0 and 1 respectively, then carrying out integrated and automaton minimization processing, and if the two obtained results are the same, determining that the assertion has space-time property.

Further, the adding the logic circuit to the assertion to form a new assertion comprises:

the logic circuit is stepped up to form a new assertion.

Further, the step-up logic circuit is premised on the absence of emptiness.

Further, the step-up logic circuit is to increase the depth of the logic circuit and/or the depth of the design block.

Further, the incremental logic circuit determines the number of incremental logic and the final test degree according to the computing resources set by the user, including setting the maximum computing time and the maximum available memory.

Further, the method further comprises:

the assertion is corrected to have either a 0 or a 1 for the sub-expression that makes the assertion spacious.

Further, prior to the correcting the assertion, further comprising:

receiving the redundant sub-expressions is not an erroneous acknowledgement.

In a second aspect of the invention, a storage medium having stored thereon computer instructions which, when executed, perform the steps of a method of testing and automatically correcting for autonomy in the form of a proof of assertion.

In a third aspect of the present invention, there is provided a terminal comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, the processor executing the steps of the method for testing and automatically correcting for a formal verification of assertion imminence when executing the computer instructions.

Different from the prior art, the invention has the beneficial effects that:

(1) the invention is based on the most extensive space-general definition, and the integrity of the test is increased; meanwhile, due to the comprehensive process and the minimum determinability, the two results only need to be compared in structure, and the efficiency is high.

(3) In the preferred embodiment of the invention, an additional logic circuit is added for carrying out the null-flooding test, so that the null-flooding can be found to exist in the expression. This result indicates that an error occurred in the externally added logic resulting in an assertion flush.

(4) And performing complexity controllable test by using a progressive mode, performing iterative space-flooding test, and gradually adding the designed logic circuit from the strongest space-flooding property, namely assertion, wherein the method has the advantages of using the calculation resources as little as possible and finding the space-flooding expression as early as possible so as to be beneficial to analyzing and correcting the added logic circuit.

Drawings

FIG. 1 is a flow chart of a test and correction method of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

First, it should be noted that the most general definition of space-flooding will be adopted in the following exemplary embodiments, that is, for each sub-expression in an assertion, if its establishment and failure have no influence on the establishment or failure of the whole assertion, then the sub-expression is redundant, and the assertion is space-flooding.

Referring to fig. 1, fig. 1 is a flow chart of a test and automatic correction method for verifying the emptiness of an assertion in a formal manner, comprising the steps of:

Specifically, in the assertion synthesis process, two synthesis results are generated for each sub-expression, one assuming that the expression is 0 and the other is 1, and the results are subjected to automaton minimization processing.

Theoretically, two logically equivalent automata guarantee automata graph equivalence only after minimization. Minimization is necessary because we can only rely on graphical equivalence to judge functional equivalence.

For tests that assert itself (the strongest nullifying), all that is needed is to compare whether the two results are the same. Due to the determinability of the integrated process and the minimization method used in the exemplary embodiment (determinability, i.e., uniqueness, of the optimized result, which is a basic theory of automaton optimization), the two results only need to be compared structurally, so that the efficiency is high.

In addition, the degree of the empty property is classified into strong and weak. For example, some blanks are self-asserted and are independent of the design to be verified, and the unconditional blanks have the maximum strength; and some incompleteness is caused by logic circuit relation in design, such as the failure of A in the background art, and is not the problem of asserting itself. The more logic circuits involved in the universe, the greater the association with the design and the lower the strength. With respect to such an observation, it is proposed in the exemplary embodiment to perform an iterative space-flooding test, which gradually adds to the designed logic circuit, starting with the strongest space-flooding, i.e., the assertion itself. Wherein the intensity indicates the degree change of the space-flooding from spontaneous to caused by the logic circuit, and provides a quantization index for the reason of the space-flooding.

Specifically, in an exemplary embodiment, the method further comprises:

adding the logic circuit into the assertion to form a new assertion;

And, the adding the logic circuit to the assertion to form a new assertion comprises:

without the nullifying property, the logic circuit is stepped up to form a new assertion.

I.e. in each iteration, the logic circuit is increased stepwise.

Wherein, in yet another exemplary embodiment, the step-up logic is to increase the depth of the logic and/or the depth of the design block.

In yet another exemplary embodiment, the step-up logic circuit is premised on the absence of emptiness.

In yet another exemplary embodiment, the incremental logic circuitry determines the amount of incremental logic and the extent of the final test based on user-defined computational resources, including the maximum computational time and maximum available memory.

Meanwhile, in a further exemplary embodiment, the method further includes:

I.e. finding the redundant sub-expressions at last, after the user confirms that the redundant sub-expressions are not wrong (the preferred scheme), we can optimize the assertion, i.e. delete the redundant sub-expressions and substitute 0 or 1 to minimize the assertion.

Especially in cases where the spaciousness is a result of the introduced design logic circuitry, the user needs to confirm whether to modify the circuitry or assert. In the latter case, an automatic assertion fix is made.

Through testing of the latest OVL standard assertion library, we find out that the self-contained space-time property of the assertion at 3 and the space-time property of the assertion at 6 are added after an OVL module (containing no design logic) where the assertion is located is added. The tests of these two intensities for-40 OVL library assertions took only a few seconds of CPU time.

Based on such understanding, the technical solutions of the present embodiments may be essentially implemented or make a contribution to the prior art, or may be implemented in the form of a software product stored in a storage medium and including several instructions for causing an apparatus to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A test and automatic correction method for verifying the emptiness of an assertion in a form is characterized in that: the method comprises the following steps:

2. The method of claim 1 for testing and automatically correcting for formal verification of assertion imminence, wherein: the method further comprises the following steps:

adding the logic circuit into the assertion to form a new assertion;

3. The method for testing and automatically correcting the emptiness of formal verification assertions according to claim 2, characterized in that: the adding the logic circuit to the assertion to form a new assertion comprises:

the logic circuit is stepped up to form a new assertion.

4. The method of claim 3 for testing and automatically correcting for formal verification of assertion imminence, wherein: the step-up logic circuit is premised on the absence of nullifying properties.

5. The method of claim 3 for testing and automatically correcting for formal verification of assertion imminence, wherein: the step-up logic circuit is to increase the depth of the logic circuit and/or the depth of the design block.

6. The method of claim 3 for testing and automatically correcting for formal verification of assertion imminence, wherein: the step-by-step logic circuit determines the number of logic to be added and the final test degree according to the computing resources set by the user, including setting the maximum computing time and the maximum available memory.

7. The method of claim 1 for testing and automatically correcting for formal verification of assertion imminence, wherein: the method further comprises the following steps:

8. The method of claim 7 for testing and automatically correcting for formal verification of assertion imminence, wherein: prior to the correcting assertion, further comprising:

receiving the redundant sub-expressions is not an erroneous acknowledgement.

9. A storage medium having stored thereon computer instructions, characterized in that: the computer instructions when executed perform the steps of a method for testing and automatically correcting for a formal verification of assertion imminence as claimed in any one of claims 1 to 8.

10. A terminal comprising a memory and a processor, said memory having stored thereon computer instructions executable on said processor, wherein said processor when executing said computer instructions performs the steps of a method of testing and automatically correcting for a formal verification of assertion imminence as claimed in any one of claims 1 to 8.