CN110289040B

CN110289040B - Memory detection method combining BIST and ECC in system chip

Info

Publication number: CN110289040B
Application number: CN201910555383.1A
Authority: CN
Inventors: 黄凯; 郑昌立; 余慜; 修思文
Original assignee: Zhejiang University ZJU; Research Institute of Southern Power Grid Co Ltd
Current assignee: Zhejiang University ZJU; Research Institute of Southern Power Grid Co Ltd
Priority date: 2019-06-25
Filing date: 2019-06-25
Publication date: 2021-05-11
Anticipated expiration: 2039-06-25
Also published as: CN110289040A

Abstract

The invention discloses a memory detection method combining BIST and ECC in a system chip, belonging to the field of built-in self-test of memories. The system comprises a BIST module, an ECC module and a memory, and the specific method comprises the following steps: when the ECC module detects that the data written into the memory is inconsistent with the data read out of the memory and only one bit of error data exists, an ECC correction algorithm is called to correct the error one bit, and then the BIST module is returned, and the BIST module gives out a correct result; when the ECC module does not detect an error, the result signal at BIST will give a correct result; if there are two or more bits of error, the ECC is not corrected and when it is returned to BIST, erroneous data is detected and BIST gives feedback of the result of the error. The invention improves the detected yield of the memory, and the memory is still considered to be correct when one bit error occurs in one memory space.

Description

Memory detection method combining BIST and ECC in system chip

Technical Field

The invention relates to the field of memory BIST detection, in particular to a memory detection method combining BIST and ECC in a system chip.

Background

High complexity system-on-chip products are facing increasingly more severe challenges from quality, time-to-market, reliability, etc. Today, most semiconductor manufacturers focus on the leaders in memory array technology in terms of capacity, process technology, quality, and the like. Meanwhile, the performance index and reliability of the embedded memory, which is an important component in the soc (system on chip), directly determine the performance of the soc. The stability of embedded memories is becoming increasingly important in the field of design and testing. In microprocessors and asics, large-scale SRAM (Static Random-Access Memory) arrays, which are widely used as cache memories, account for a large proportion of the die-to-die area. In the integrated circuit industry chain, circuit testing runs through all processes from circuit design to product. The test method comprises prototype verification test during circuit design, test in a probe test board during wafer production, performance test after chip packaging, comprehensive user test in final products according to different requirements and the like. The purpose is to detect as many and as early as possible chip failures and to detect them. At this stage, the testing problem faced by the integrated circuit industry is very severe. The proportion of memory in a chip is increasing, the chip size is continuously reduced and the transistor manufacturing cost is continuously reduced in order to make the memory more cost-effective, and the test expenditure and the test time spent by each chip are directly related but cannot be increased significantly. The number of bits per chip continues to grow exponentially and the sensitivity to faults increases with the faults becoming more complex.

The test methods for the embedded memory in the chip generally include direct access to the memory, embedded cpu (central Processing unit) test, and memory built-in self-test. The direct memory Test is based on the Test in ATE (auto Test Equipment) Test equipment, and the specific operation is to directly access memory pins, so that various algorithms can be easily realized. However, as the algorithm is more and more complex to implement, the testing cost is more and more expensive, the working frequency of the memory is higher and higher, the requirement on ATE equipment is high, and the testing cost is correspondingly increased. The relevant test algorithm of the embedded CPU test can be modified in the microprocessor by software, is flexible and changeable, and does not need to modify the hardware of the tested memory. However, when the testing algorithm is modified, the software program of the microprocessor needs to be modified, which is labor-consuming, and it is difficult to effectively test the memory for storing the CPU-related program, which has some limitations.

The main idea of the MBIST (Memory built-In Self-Test) technology is to add a BIST circuit inside the Memory chip and outside the Memory circuit for automatically generating Test stimulus signals to the Memory chip and automatically processing and feeding back the Test results. The area of the memory chip is larger than the original area, but the proportion of the circuit is smaller and smaller with the increase of the memory capacity, and the advantages are more and more obvious. Firstly, the BIST can realize an automatic test process, wherein the used algorithm is automatically executed, so that the dependence on high-cost ATE is reduced, and therefore, a system clock can be utilized for full-speed test, so that the test time is reduced, and the defect coverage rate of a chip is increased; finally, the BIST can automatically generate vectors under relevant control to achieve the functions of automatic testing and automatic repair, so that the method is called a mainstream testing method for memory testing.

The architecture of a typical built-in self test consists of four parts: a BIST controller, a vector generator, a response analyzer and a circuit under test. The vector generator is mainly used for generating test vectors and receiving control signals from the controller. Under the action of different algorithms, the generated test vectors are completely different, and the test vectors are generally generated by using a vector generator automatic generation technology. The N-bit test vectors are generated and then sequentially input to the input end of the brushed circuit under the action of a system clock. After the test is finished, the test result can be checked at the output port of the response analyzer and compared with the correct response to obtain the test result. The test vector of the method is automatically generated, and a large amount of input test data is not needed, so that the method is high in speed, high in efficiency and high in fault coverage rate. The main considerations for the generation of test vectors are: higher fault coverage, test vector length, hardware consumption level. The test method of the MBIST is to compare the memory response under normal condition with the memory response when acting on the test vector, analyze the response signal of the tested circuit, and output a signal whether the test vector is correct or not, and feed back the signal whether the function of the tested circuit of the BIST controller is correct or not.

ECC (error Checking and correction) is an error detection and correction algorithm. If there is no problem in operation timing and circuit stability, the memory error will not cause the whole block or page to be unable to read or all error, but only one or several error in the whole page. ECC can correct 1 bit error and detect 2 bit errors, and the calculation speed is fast, but it cannot correct more than one bit of errors and cannot guarantee detection of more than two bits of errors. It is an extra thing on the data to store a code encrypted with the data. When data is written into the memory, the corresponding ECC code is also saved. When the data just stored is read back again, the stored ECC code is compared with the ECC code generated when the data was read. If the two codes are not the same, they are decoded to determine which bit in the data is incorrect. The erroneous bit is discarded and the memory controller releases the correct data. Corrected data is less likely to be placed back into memory. If the same error data is read out again, the correction process is performed again. Rewriting the data increases the overhead of the processing process, which results in a significant reduction in system performance. If the error is generated by a random event rather than a defect in the memory, the error data at the memory address is replaced by other data to be written again.

ECC can be divided into linear block code and convolutional code according to the processing method of the source, and the linear code is commonly used for memory consolidation, and the convolutional code is mostly used in a communication system. The ECC code adopts a redundant check bit form to reinforce the original information, thereby realizing the purposes of error correction and error detection. It is common for ECC checks to operate on 256 bytes of data at a time, including column checks and row checks. The exclusive or of each bit to be checked is solved, if the result is 0, an even number of 1 s is indicated; if the result is 1, it indicates that an odd number of 1 s is contained. The column check rules are shown in table 1. The 256 bytes of data form a matrix of 256 rows and 8 columns, each element of the matrix representing one bit.

Under the prior art, the ECC can detect one bit error and correct and detect two bit errors, and the single BIST detection can give an error signal when detecting one bit error, so that the memory in the area with the error cannot be used as long as the error occurs.

Disclosure of Invention

Aiming at the existing memory detection technology, the invention provides a method for an ECC (error correction code) check module of a BIST multiplexing system chip, under the condition that the BIST detects that only one bit error occurs, the error of the one bit is corrected through the ECC, and the corrected result is still considered to be correct. When errors of two or more bits are detected, the corresponding address is recorded so that the error area can be avoided subsequently and the utilization rate is improved. Compared with the detection only by BIST, the method provided by the invention can not give error feedback when only one bit of error exists, and the yield of the memory is improved.

In circuitry, DFT (design for test) is commonly used to detect combinational logic errors and flip-flop errors. There is a need in the BIST multiplexed ECC detection method to ensure that the ECC itself circuitry is usable without errors at DFT detection. When problems arise with the ECC module itself, it cannot be multiplexed by the BIST system, in which case BIST should be the same as conventional built-in self-test. Thus, the choice of whether to multiplex an ECC module can be made in the BIST system, and when an ECC module is not available, the ECC is not multiplexed. The BIST can multiplex the ECC module only if the ECC itself does not detect a problem. When the ECC module does not detect the problem, the ECC module can be multiplexed by the BIST detection system to improve the yield of the memory.

A memory detection method combining BIST and ECC in a system chip comprises a BIST module, an ECC module and a memory, and the specific method comprises the following steps:

when the ECC module detects that the data written into the memory is inconsistent with the data read out of the memory and only has error data of one bit, calling an ECC correction algorithm to correct the error data of one bit, and returning to the BIST module, wherein the BIST module gives out a correct result;

when the ECC module does not detect errors, the BIST module gives a correct result;

when two or more bits of errors exist, the ECC module does not correct the errors, and when the errors are returned to the BIST module, the BIST module detects the wrong data, and the BIST module feeds back the wrong result.

Furthermore, the BIST module gives out an enabling control operation to generate an address and data, a write operation is initiated to a certain area of the memory, the data is subjected to ECC coding to obtain coded data, and the original data is stored in the memory; the BIST enables the control signal, initiates the read operation of the same address of the memory, and the read data is processed by ECC coding and compared with the coding data during writing.

Furthermore, two or more bits of errors exist, and the address of the memory cell with the errors is recorded after the ECC module checks.

Further, the BIST module multiplexes the ECC module when the ECC module is normal, and does not multiplex the ECC module when the ECC module is unavailable.

Furthermore, the detection function of the BIST and the correction function of the ECC are combined to improve the yield of the memory. When the data written into the memory is the same as the read data, the checksum of the input data is consistent with the checksum of the read data, the ECC cannot detect an error, the read data is returned to the BIST for detection, the obtained data is consistent with the written original data, and the system gives a correct signal.

Further, for the case of an error with one bit, a certain bit of the written data is modified abnormally and is inconsistent with the original data, when the ECC module checks, the checksum of the read data is different from the checksum of the written data, the ECC module starts the correction function and corrects the data in the data error position in a flip manner, and then the data is transmitted back to the BIST module for BIST check, at this time, since the data in the error position is corrected, the data is consistent with the original written data, the result detected by the BIST module is correct, the memory in the area is still considered to be not bad, and the system still gives correct result feedback. I.e. despite a one bit error, this area is considered usable, i.e. tolerant to one bit errors.

Further, when two or more bits of data have errors, the checksum of the read data is inconsistent with the checksum of the written data when the ECC module detects the errors, but the ECC module can only detect the errors, in this case, the errors cannot be corrected, the data returned to the BIST is still the wrong data, the BIST detects the errors, and the system gives feedback of the errors.

The invention provides a method for detecting a memory by combining BIST and ECC, which can correct errors through an ECC module and return the errors to the BIST module under the condition of one bit error, wherein the result received by the BIST module is the same as the original data, and the corresponding area of the memory is still considered to be usable, so that error result feedback is not given, and correct feedback is given. When errors of two or more bits are detected, the corresponding address is recorded so that the error area can be avoided subsequently and the utilization rate is improved. The method provided by the invention improves the yield of BIST detection.

Drawings

FIG. 1 is a diagram of a classical BIST detection framework;

FIG. 2 is a diagram of a classic ECC check framework;

FIG. 3 is a diagram of a detection framework of the present invention.

Detailed Description

The technical scheme of the invention is further described below by combining the attached drawings of the specification.

The invention provides a detection method for improving the yield of a memory by multiplexing ECC (error correction code) check in a system chip in an MBIST (multi-byte synchronous multi-input multi-output) method. When the ECC module does not detect an error, it can be selected for BIST detection. If the ECC module is detected to have errors, the BIST module can not multiplex the ECC module, and when the ECC module is detected to have errors, the BIST module can not multiplex the ECC module, has no correction function, is consistent with the traditional BIST technology, and otherwise is difficult to judge whether the detected errors are errors caused by ECC or the memory. At this time, the BIST is consistent with the traditional method, only the detection technology related to the BIST is used, and the ECC module is not multiplexed. The method is characterized in that: when a region in the memory has a bit of error, the BIST will not detect the error condition through ECC correction, and give correct feedback to consider the region still usable. When two or more bits of error occur in a certain area, the ECC cannot correct, and then the BIST detects the error, considers that the memory block of the area is unusable, and gives feedback of the error. When two bits or more of errors exist, the memory unit is indicated to be unusable, the corresponding address in the memory for storing the check code is recorded, and if the error exists, the memory unit is not used. When no error occurs, the added ECC module does not affect the result, returns the original value to the BIST, does not detect the error, and gives correct feedback.

The pure BIST detection is as shown in figure 1, a starting signal is generated by a controller and sent to a vector generator, the vector generator automatically generates address and data signals according to different algorithms, then a tested circuit receives a test vector, the internal algorithm is used for checking whether the reading and writing are normal, if the reading and writing are wrong, an error feedback is given to the outside, and if the reading and writing are normal, a correct feedback is given to the outside. Pure ECC check-checking as shown in fig. 2, input original data of every 256 bytes is ECC encoded to obtain a check sum of encoded data, which is called original ECC check sum, and the original check sum and the original data are stored in the memory respectively, and when data is read from the memory, the read data is also ECC encoded every 256 bytes to obtain a piece of check sum encoded data. During checking, carrying out bitwise XOR on ECC encoding data of original data and new encoding data, if the result is 0, indicating that no error exists, and if 11 bit bits exist in the XOR result of 3 bytes are 1, indicating that one bit error exists and the error can be corrected; if only 1 bit is 1 in the exclusive OR result of 3 bytes, the error of the detected storage area is indicated; other cases all indicate that an uncorrectable error has occurred.

The method multiplexes the test frame diagram of the ECC module in the system chip during the BIST detection as shown in FIG. 3, and combines the detection function of the BIST and the correction function of the ECC to improve the yield of the memory. When the data written into the memory is the same as the read data, the checksum of the input data is consistent with the checksum of the read data, the ECC module does not detect an error, the read data is returned to the BIST for detection, the obtained data is consistent with the written original data, and the system gives a correct signal.

For the case that one bit of error exists, a certain bit of written data is abnormally modified and is inconsistent with the original data, the checksum of read data is different from the checksum of the written data during ECC check, the ECC correction function is started and the data at the position of the data error is reversed and corrected, and then the data is transmitted back to the BIST module for BIST check, at this time, because the data at the position of the error is corrected, the data is consistent with the original written data, the result detected by the BIST module is correct, the memory in the area is still considered to be not bad, the system can still give correct result feedback.

When two or more bits of data have errors, the checksum of the read data is inconsistent with the checksum of the written data when the ECC module detects the errors, but the ECC can only detect the errors, in this case, the errors cannot be corrected, the data returned to the BIST is still wrong, the BIST detects the errors, and the system gives feedback of the errors.

From the above analysis, the method provided by the present invention adds an ECC check and correction module on the basis of BIST detection, so that even if a bit of error occurs during memory detection, the system still considers that the storage of the slice area is available by using the correction function of ECC to correct the erroneous data, thereby improving the yield of the memory.

Claims

1. A memory detection method combining BIST and ECC in a system chip is characterized by comprising a BIST module, an ECC module and a memory, and the specific method comprises the following steps:

when the ECC module detects that the data written into the memory is inconsistent with the data read out of the memory and one bit of error data exists, an ECC correction algorithm is called to correct the error one bit, and then the BIST module is returned, and the BIST module gives out a correct result;

when the error of two bits or more exists, the ECC module does not correct and returns to the BIST module, the error data is detected, and the BIST module feeds back the error result.

2. The method as claimed in claim 1, wherein the BIST module is configured to provide an enable control operation, generate an address and data, initiate a write operation to a certain area of the memory, perform ECC encoding on the data to obtain encoded data, and store the original data in the memory; the BIST module enables the control signal to initiate a read operation on the same address of the memory, and the read data is subjected to ECC encoding and compared with the encoded data during writing.

3. The method of claim 1, wherein there are more than two bits of errors, and the ECC is verified to record the address of the memory cell with the error.

4. The method of claim 1, wherein the BIST module multiplexes the ECC module when the ECC module is normal, and does not multiplex the ECC module when the ECC module is not available.

5. A method as claimed in claim 1, wherein when the data written into the memory is the same as the data read out, the checksum of the input data is the same as the checksum of the data read out, the ECC module does not detect an error, the data read out is returned to the BIST module for detection, the obtained data is the same as the original data written in, and the system gives a correct signal.

6. A method as claimed in claim 2, wherein for a bit error, the written data has a bit which is abnormally modified and is inconsistent with the original data, the checksum of the read data is different from the checksum of the written data when the ECC module checks, the ECC correction function is started and the data at the data error position is reversed and corrected, and then the data at the error position is corrected and is consistent with the original written data, the result detected by the BIST module is correct, the BIST module considers that the memory in the area is not bad, and the system still gives correct result feedback.

7. A method as claimed in claim 1, wherein when two or more bits of data have errors, the ECC module checks that the checksum of the read data is inconsistent with the checksum of the written data, but the ECC module can only detect the errors and cannot correct the errors, the data returned to the BIST module is still the erroneous data, the BIST module detects the errors, and the system gives feedback of the errors.