CN110275774A

CN110275774A - The mechanism of physical storage device resource is dynamically distributed in virtualized environment

Info

Publication number: CN110275774A
Application number: CN201910159331.2A
Authority: CN
Inventors: O.P.平托
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-03-13
Filing date: 2019-03-04
Publication date: 2019-09-24
Also published as: KR20190108038A

Abstract

Disclose a kind of storage equipment.Storage equipment may include at least one input/output (I/O) queue of the request for the storage device of data and at least one virtual machine (VM) on host equipment.Storage equipment can support I/O queue, IOQ creation order, be that VM distributes I/O queue, IOQ with request.I/O queue, IOQ creation order may include will logical block address (LBA) associated with I/O queue, IOQ range LBA range attribute.The range of LBA can be mapped to the range of the physical block address (PBA) in storage device by storage equipment.

Description

The mechanism of physical storage device resource is dynamically distributed in virtualized environment

Related application data

This application claims the power for the U.S. Provisional Patent Application Serial No. 62/642,596 submitted on March 13rd, 2018 Benefit, this application are incorporated herein by reference for all purposes.

The application on April 20th, 2018 is submitting, is now in U.S. Patent Application Serial Number 15/959 pending state, 108 is related, and this application is incorporated herein by reference herein for all purposes.

Technical field

Present inventive concept relates generally to store equipment, more particularly, to the virtual machine pair supported by that may be isolated from each other Store the access of equipment.

Background technique

Single input/output virtualizes (Single Root Input/Output Virtualization, SR-IOV) A kind of interface mechanism that specification is supported, the mechanism allow single physical peripheral component interconnection quickly (Peripheral Component Interconnect Express, PCIe) equipment is rendered as (separate) the physics PCIe of multiple separation and sets It is standby.For performance and manageability reason, SR-IOV facilitates shared and PCIe resource is isolated, while promoting interoperability.

SR-IOV has existed for 10 years for network adapter.Recently, SR-IOV has begun including storage device (storage).Resource isolation has been provided in central processing unit (Central Processing Unit, CPU) processing, this Facilitate through management program (hypervisor) as main equipment and virtual machine (Virtual Machine, VM) as auxiliary The fast virtualization of equipment uses.Using SR-IOV, network and storage equipment can expose physics function device (Physical Function, PF) and virtual functions equipment (Virtual Function, VF).These jointly provide equipment blocking, it is sufficient to will Physical server is changed into multiple virtual servers, so all using can it is each it is comfortable themselves isolation space in Operation.

Although calculation processing, network and storage device constitute three virtualization pillars, storage equipment and storage equipment Supplier still lags in terms of meeting SR-IOV.The fact that may be because, it is different from networking (networking), deposit Storage device defines empty by the data address of a certain range of logical block address (Logical Block Address, LBA) reference Between.This LBA range can only be subdivided into the unit of limited quantity.In addition, storage equipment needs physical hardware door to support volume Outer VF because VF be directly exposed to VM peripheral component interconnection (Peripheral Component Interconnect, PCI) the hardware capability in space.SR-IOV, which is added to storage/network equipment, will increase its quantity and chip size, and consume More power.

SR-IOV solves the problems, such as hardware isolated, while providing bare machine (bare-metal) performance, because with super virtual It is different to change (para-virtualized) equipment, I/O is without going through management program.Quick (the Non- of nonvolatile memory Volatile Memory Express, NVMe) storage equipment be newest using SR-IOV.It, may but for storage device There are also other mechanism to provide the access of isolation for multiple VM.

There is still a need for a kind of methods to provide function provided by similar SR-IOV, but the hardware forced without SR-IOV is wanted Summation limitation.

Summary of the invention

The one side of the disclosure provides a kind of for dynamically distributing depositing for physical storage device resource in virtualized environment Store up equipment, comprising: the storage device for data；And at least one input/output (I/O) queue, for being set from host The request of standby at least one upper virtual machine (VM), wherein the storage equipment supports I/O queue, IOQ creation order, to request as institute The VM for stating at least one VM distributes the I/O queue, IOQ of at least one I/O queue, IOQ, and the I/O queue, IOQ creation order includes will be with The LBA range attribute of the range of the associated logical block address of I/O queue, IOQ (LBA), also, wherein the storage equipment will The range of LBA is mapped to the range of the physical block address (PBA) in the storage device for data.

Another aspect of the present disclosure provides a kind of for dynamically distributing physical storage device resource in virtualized environment Field programmable gate array (FPGA), comprising: at least one virtual input/output (I/O) queue, for coming from host equipment At least one virtual machine (VM) request；And mapping logic, for by the virtual I/ of at least one virtual i/o queue O queue is mapped to the I/O queue, IOQ in storage equipment, so that the received I/O of slave VM in the virtual i/o queue is requested via institute State I/O queue, IOQ and be passed to the storage equipment, and in the I/O queue, IOQ from storage the received result of equipment via described Virtual i/o queue is passed to the VM, wherein FPGA support virtual i/o queue creation order, to request for described in extremely The VM of a few VM distributes the virtual i/o queue of at least one virtual i/o queue, the virtual i/o queue creation order Including will logical block address (LBA) associated with the virtual i/o queue range LBA range attribute, also, wherein with The range of the LBA is mapped to the object in the storage equipment by the storage equipment that the FPGA is separated but connected to the FPGA Manage the range of block address (PBA).

The another aspect of the disclosure provides a kind of for dynamically distributing physical storage device resource in virtualized environment Article including non-transitory storage medium is stored with instruction on the non-transitory storage medium, when described instruction is by machine When execution, so that: the first request is received from the virtual machine (VM) on host equipment, storage equipment is gone in first request；It catches Obtaining first request prevents it from reaching the storage equipment；The second request, institute are sent to field programmable gate array (FPGA) State the second request simulation first request；The result of second request is received from the FPGA；And it is sent to the VM The result of second request.

Detailed description of the invention

Fig. 1 shows setting for virtual machine (VM) the access storage equipment of the support isolation for the embodiment conceived according to the present invention It is standby.

Fig. 2 shows the additional details of the equipment of Fig. 1.

Fig. 3 shows the communication path between the storage equipment of the VM and Fig. 1 of Fig. 1, and wherein the storage equipment of Fig. 1 only exposes One physical function.

Fig. 4 shows the communication path between the storage equipment of the VM and Fig. 1 of Fig. 1, and wherein the storage equipment of Fig. 1 exposes Multiple physical functions.

Fig. 5 shows the details of the storage equipment of Fig. 1.

Fig. 6 shows the expansion I/O queue creation order of the storage equipment for Fig. 1.

Fig. 7 shows the physical storage device for being divided into the storage equipment of Fig. 1 of multiple NameSpaces.

Fig. 8 shows the memory mapping of the doorbell in the storage equipment of Fig. 1, to support VM to be isolated.

Fig. 9 show for Fig. 3 field programmable gate array (Field Programmable Gate Array, FPGA extension virtual i/o queue) creates order.

Figure 10 shows the FPGA for supporting the Fig. 3 of virtual i/o queue for the I/O queue, IOQ being mapped in the storage equipment of Fig. 1.

The storage equipment for Fig. 1 that Figure 11 shows the embodiment conceived according to the present invention is that VM distributes I/O queue, IOQ The flow chart of instantiation procedure.

The FPGA for Fig. 3 that Figure 12 shows the embodiment conceived according to the present invention is that VM distributes virtual i/o queue The flow chart of instantiation procedure.

The management program for Fig. 3 that Figure 13 shows the embodiment conceived according to the present invention is handled from the virtual of Fig. 3 The flow chart of the instantiation procedure of the control request of machine.

Figure 14 show the embodiment conceived according to the present invention for the storage equipment of Fig. 1 or the FPGA of Fig. 3 by doorbell Storage address be mapped to the different operating system page with support VM be isolated instantiation procedure flow chart.

Specific embodiment

Now with detailed reference to the embodiment of present inventive concept, its example is shown in the drawings.In following detailed description In, numerous specific details are set forth, so as to thoroughly understand present inventive concept.It will be appreciated, however, that ordinary skill Personnel can practice present inventive concept without these specific details.In other cases, public affairs are not described in Method, process, component, circuit and the network known, in order to avoid unnecessarily obscure the aspect of embodiment.

It will be appreciated that though term first, second etc. can be used to describe various elements herein, but these elements are not It should be limited by these terms.These terms are only used to distinguish an element and another element.For example, not departing from this hair In the case where the range of bright design, the first module can be referred to as the second module, and similarly, the second module can be referred to as first Module.

The term used in the description herein to present inventive concept merely for description particular embodiment purpose, and unexpectedly Figure limitation present inventive concept.As used in the description of present inventive concept and appended claims, singular " one ", "one" and "the" are also intended to include plural form, unless context is expressly otherwise indicated.It is also understood that used herein Term "and/or" refers to and covers the associated any and all possible combinations for listing one or more of project.Also It should be appreciated that when used in this manual, term " including (comprise) " and/or " including " specify the feature, Integer, step, operation, the presence of element and/or component, but be not excluded for other one or more features, integer, step, operation, The presence or addition of element, component and/or their group.The component and feature of attached drawing are not drawn necessarily to scale.

Currently, single input/output virtualization (SR-IOV) quickly (NVMe) stores equipment for nonvolatile memory Early purchasers had taken up each physical function of offer (PF) limited quantity virtual functions (VF) and associated life The route of the name space.The distribution of logical address space range is distributed depending on NameSpace, and is directly accessed the bare machine of VM and taken Certainly in the quantity of the VF of support.This embodiment is to supporting the storage equipment of large capacity to create problem, because it must be with Power and naked core (die) size are cost to support additional hardware, to meet the performance requirement for directly supporting multiple VM.Most On lower bound degree, support SR-IOV function that equipment is needed to provide peripheral component interconnection (PCI) configuration space, the I/ of separation for each VF O item (bar), the I/O queue, IOQ for submitting and completing queue, message signal interrupt (Message Signaled Interrupt, MSI-X) and support queue doorbell address.

The deficiency of available fixed allocation method promotes the exploitation of the NVMe committee to eliminate in first SR-IOV storage equipment Another specification of embodiment limitation, is such as changed to dynamic resource allocation and management for fixed resource distribution.It is many current Change that is open and overturing is attempt to solve resource allocation problem.However, the constraint that they are limited by physical equipment, The VF such as supported, which increase the specification complexity inevitably occurred.

Although there is a small number of leading management programs in the market, such as VMWare, Microsoft, Citrix XenServer, KVM, Qemu and Oracle VM, but current seldom management program only in the set just changes in active adaption market. By doing so, they have won most of market shares.Due to the essence of their programmed environment, each management program environment It can be viewed as customized embodiment.Therefore, support that the variation of this embodiment may be critically important.

The embodiment of present inventive concept defines simpler mechanism to be programmed to SR-IOV storage equipment, to provide VM isolation and performance.The embodiment of present inventive concept is by mapping resource by management program, it then follows simpler method. The embodiment of present inventive concept may include that strategy is used for:

1) by providing the direct application access to the I/O queue, IOQ of VM (submit and complete queue to), behavior extension is arrived VM。

2) ability (capability) of I/O queue, IOQ (submitting and complete queue) is directly mapped to VM.

3) controller details is encapsulated in and is used to manage path in management program.

4) physical resource that each isolated VM of dynamic isolation is required.

The embodiment of present inventive concept can be supported effectively to mention as feature by adding new NVMe storage equipment For the function of SR-IOV type.

The embodiment of present inventive concept defines following new feature:

1) NVMe I/O for performance purposes, is submitted queue and I/O to complete queue and (is collectively known as I/O queue, IOQ by one kind It is right) directly it is remapped to the higher management mechanism of VM.

2) for implementing the mechanism of virtualization controller in a kind of management program, which reflects Hardware I/O queue dynamic It is mapped to VM, the set as virtualization controller.

3) a kind of mechanism that logical address space is mapped as to logic unit or NameSpace.

4) a kind of mechanism that not available additional I/O queue, IOQ in storage equipment is mapped in using additional method.

5) a kind of to provide the VM method of specific isolation for shared resource.

The embodiment of present inventive concept provides the following advantages better than traditional technology:

1) class SR-IOV function is provided, without expensive SR-IOV hardware requirement.

2) the additional I/O resource isolation and performance advantage of VM for surmounting equipment code is provided.

3) it provides to be fully virtualized and drives journey to avoid operating system (Operating System, O/S) is built-in The hardware capabilities that sequence changes.

4) channel service quality (Quality of Service, QoS) is created between storage facilities and administration program.

5) simplify the hardware requirement of Storage Virtualization.

The embodiment of present inventive concept provides a kind of mechanism that storage equipment I/O resource is directly remapped to VM. The embodiment of present inventive concept uses the existing resource that remaps for memory and interruption, including for the defeated of x86 framework Enter-output storage administrative unit (Input-Output Memory Management Unit, IOMMU) and additional hardware Resource, to be mapped to a large amount of VM that storage equipment is not supported usually.

In order to realize these advantages, store equipment (may include solid state drive (Solid State Drive, SSD)) Should:

1) expansion I/O queue is supported to create attribute.

2) the simple logic address of I/O queue, IOQ rank is supported to remap.

3) doorbell at O/S page boundary is supported, for VM safety.

4) these extended attributes are announced by one or more fields according to NVMe codes and standards.

5) additional queue priority hierarchical arbitration mechanism is optionally provided, rather than default application QoS.

By NVMe I/O queue, IOQ to mapping directly to VM

I/O, which submits queue and I/O to complete queue, can be collectively known as I/O queue, IOQ pair, because they work together, and When resource-constrained, it will be mapped automatically using 1:1.NVMe driver built in most of (if not all) creates these teams The 1:1 of column maps.The embodiment of present inventive concept is using this usage as target, because these are that the equipment run in VM is driven Dynamic program embodiment.

Support the storage equipment of the embodiment of present inventive concept that can provide the wound of the expansion I/O for submitting and completing queue Build order.Order can be applied by isolated operation code, can be marked as optional (optional) or can be with It is defined as the order of supplier specific (vendor-specific).Explosion command can support the basic of NVMe specification definition NVMe queue create order details, such as queue size, queue identifier, queue priority grade, queue buffer whether object Continuous, interrupt vector and the enabled field of interruption in reason.But in addition to that, explosion command can be empty with the address of holding equipment Interior logical block addressing offset.These mechanism works are as follows:

1) when creating VM, management program NVMe of exposure virtualization in the PCI space of VM stores equipment.Equipment is most It can just be fully virtualized, to use client computer (guest) when accessing its PCI configuration and I/O memory-mapped region It exits.For interrupting, management program can be set specific MSI-X and interrupt, with according to the embodiment of management program, according to need Want direct broken clients machine VM.

2) in I/O memory mapping space, management program can capture any NVMe configuration space and change, and according to need Virtualized access is wanted to request.Management program can expose one of doorbell as I/O memory in O/S page level granularity Point, so that management program can map each doorbell in VM rank.Storage equipment can also support this function.

3) when VM creation I/O submits queue, management program capture requests and uses " to extend creation I/O and submit queue The physics I/O that (Extended Create I/O Submission Queue) " order maps that storage equipment submits team Column.The value of VM offer can be used in management program and storage equipment, and change/add the following contents:

A) queue memory is mapped to its (multiple) physical page, can directly accesses it to store equipment.It is this Mechanism can be provided by the IOMMU on the framework based on Intel x86.

B) it adds queue priority (if supporting), which carries out this queue relative to other VM excellent First grade sequence.

C) the I/O completion queue ID being previously created in the space of VM is tied to this for being directed to storage equipment I/O queue, IOQ Submit queue.

D) a part of physical address space is mapped to the logical block address start and end value of VM by addition.

E) using the appropriate of the minimum or maximum byte transmitted for minimum or maximum I/O operation or granularity per second Qos requirement.

F) in addition, global name space access authority can be provided by storing equipment if VM needs.These global namings Space access permission can specify in the array for listing NameSpace id.

G) in addition, NameSpace access type can be provided by storing equipment if storage equipment provides this support Permission, such as read-only, read-write, exclusive access.

4) management program is also possible to capture I/O completion queue request to create and is changed to (instead):

A) queue memory is mapped to its (multiple) physical page, can directly accesses it to store equipment.In base In on the framework of Intel x86, IOMMU can provide this mechanism.

B) by place for virtualize system architecture mechanism (such as IOMMU) be mapped in physical storage devices to The interrupt vector provided between amount and VM.

5) the VM complexity and management program embodiment of management are depended on, the embodiment of present inventive concept can will be multiple I/O request to create is mapped to single physical queue.If implemented, FPGA can dispose I/O complete queue, and can in It is disconnected to return to VM client computer.The mechanism can solve dynamic queue's distribution mechanism.

6) in another usage of dynamic queue's distribution mechanism, management program can be based on VM Service Level Agreement (Service Level Agreement, SLA) only exposes required I/O queue, IOQ.

Once establishing, Hardware I/O queue dynamic mapping to VM management program auxiliary mechanism can be provided and SR- The similar necessary isolation and performance advantage of those of IOV offer, but there is lower manufacture, test and debugging cost.Pipe Reason program may also need some changes, but these changes are (self-contained) alone, and are confined to available Management program, to reduce general impacts.If storage equipment is mounted in the system for not supporting virtualization, the storage equipment Conventional NVMe storage equipment be should be used as to run.

The isolation of management address space

NVMe can be by using as small computer system interface (Small Computer Systems Interface, SCSI) NameSpace that equally works of logical unit number (Logical Unit Number, LUN) is single to share A, unique logical address space.Given NameSpace ID, logical address block can be reflected with NameSpace in entire logical address The address of beginning is hit to deviate.

In conventional memory device, physical address space can be patrolled by creation NameSpace and its coordinate to be subdivided into Collect unit.In conventional memory device, this subdivision may need additional NameSpace to support to create multiple NameSpaces. The embodiment of present inventive concept bypasses this requirement by the way that the I/O queue, IOQ of creation is attached directly to logic unit space.Example Such as, extended attribute can be defined as a part in the logical addressable space of I/O queue, IOQ, therefore the NameSpace mapping defaulted To it.This modification will be aligned each I/O queue, IOQ, and VM is allow directly to access space appropriate.In general, VM or request only access Privately owned NameSpace or request access to shared NameSpace.Extended attribute in I/O queue, IOQ creation can specify relative to complete The default namespace beginning and end LBA of office's physical address space.This mechanism solves hardware NameSpace management requirement.Appoint What incoming I/O request has to pass through I/O queue, IOQ.Since I/O queue, IOQ has kept the NameSpace Map Offsets of default, so It directly can convert the address LBA using the offset of this programming.

If necessary to access multiple NameSpaces, then expansion I/O queue creation may have an additional definition to prop up Hold global name space access.For example, I/O queue, IOQ 23: the global name space of access: 3.

The mechanism of not available additional I/O queue, IOQ in mapping storage equipment

This mechanism is related to the additional field programmable gate array using the offer I/O queue, IOQ in isolated space (FPGA) logic.Using the mechanism, the embodiment of present inventive concept can support that the significantly more of VM can be mapped directly to I/O queue, IOQ.The subset that FPGA can support NVMe to standardize or standardize, arbitrates the mechanism by the specification.

Specification is supported completely: in the mechanism, FPGA can imitate NVMe specification completely, and provide complete specification rank Function.FPGA can with O/S page-granular for associated I/O queue, IOQ doorbell provide memory mapping, provide in equipment not The support of available additional I/O queue, IOQ is provided to interrupt the complete MSI-X for the I/O queue, IOQ supported and be supported, and provides every The mapping of the logical address space of one I/O queue, IOQ.In the mechanism, storage equipment does not need support expansion I/O queue function Can, this can be implemented completely in additional programmable hardware.

Partial specification is supportedIf: it can predict quantity of the quantity no more than the I/O queue, IOQ that storage equipment is supported of VM, Part or all of function can be implemented in storage equipment.FPGA may then serve as " straight-through " for the I/O request by VM Equipment, or use virtual i/o queue to the one-to-one mapping of storage equipment I/O queue, IOQ.FPGA, which still can be used for reducing, to be used for Implement the quantity of the hardware of function in storage equipment.

In any case, fpga logic can provide necessary isolation granularity for each VM.In order to provide a large amount of I/O The I/O queue, IOQ of its many exposure can be mapped to single storage equipment I/O queue, IOQ by queue, FPGA.

FPGA can provide the isolation of logical address space mapping structure and associated class NameSpace.FPGA can be with Necessary MSI-X is provided and interrupts mapping ability, so that the equipment works normally completely.

Service quality

When multiple VM execute the I/O operation of the single storage equipment of access, due to mixer effect (blender Effect), they can rejection.When VM rank shared device is without being isolated, storage equipment can not access particular VM.It is right In SR-IOV, isolation is to provide in PF map level, but its advantage is not announced or unknown.The embodiment of present inventive concept can To support I/O queue, IOQ resource being tied to VM, which not only provides nature isolation on resource class, but also is also provided in stream VMI/O request.By configuring I/O queue, IOQ mark, storage equipment has complete VM knowledge.If storing equipment to support additionally Priority level arbitration mechanism (as defined in a part of NVMe specification or supplier's specific command), management program can be with These mechanism are applied to I/O queue, IOQ in creation time.Management program can be selected different using these based on the requirement of VM Priority level is supported.

Based on provided storage functions of the equipments, the embodiment of present inventive concept can also be created in expansion I/O queue is ordered The additional field of exposure in order, the field are provided applied to performance limitation or minimum service needed for storage equipment.Required property It can limit or minimum service can quantify in the byte that read-write I/O is counted or is transmitted.This required performance limitation or minimum Service is also possible to that the settable option of VM is supported and be applied to by management program based on equipment.

The typical usage of the embodiment of present inventive concept may be directly applied to the city, enterprise for largely utilizing virtual machine (VM) Storage Virtualization in field (enterprise segment).

Fig. 1 shows setting for virtual machine (VM) the access storage equipment of the support isolation for the embodiment conceived according to the present invention It is standby.In fig. 1 it is shown that equipment 105, can also be referred to as host computer or host equipment.Equipment 105 may include place Manage device 110.Processor 110 can be any kind of processor: for example, Intel to strong (Xeon), Celeron (Celeron), Anthem (Itanium) or white imperial (Opteron) processor of atom (Atom) processor, AMD, arm processor etc..Although Fig. 1 shows Go out the single processor 110 in equipment 105, but equipment 105 may include any amount of processor, each processor can To be single or multiple core processor, and can be with any desired combined hybrid.Processor 110 can drive journey with running equipment Sequence 115, this can support the access to storage equipment 120: different device drives can support the other assemblies to equipment 105 Access.

Equipment 105 can also include Memory Controller 125, can be used for managing the access to main memory 130.It deposits Reservoir 130 can be any kind of memory, such as flash memory, dynamic random access memory (Dynamic Random Access Memory, DRAM), it is static random access memory (Static Random Access Memory, SRAM), permanent Random access memory, ferroelectric RAM (Ferroelectric Random Access Memory, FRAM) or Such as magnetoresistive RAM (Magnetoresistive Random Access Memory, MRAM) etc. is non-volatile Property random access memory (Non-Volatile Random Access Memory, NVRAM).Memory 130 is also possible to not With any desired combination of type of memory.

Although equipment 105 is portrayed as server (it can be stand alone type or rack-mount server) by Fig. 1, of the invention The embodiment of design may include the equipment 105 of any desired type, without limiting.For example, equipment 105 can with desk-top or Laptop computer or any other equipment of embodiment that can benefit from present inventive concept are replaced.Equipment 105 can be with Equipment, tablet computer, smart phone and other calculating equipment are calculated including special portable formula.

Fig. 2 shows the additional details of the equipment 105 of Fig. 1.In Fig. 2, typically, equipment 105 includes one or more A processor 110, processor 110 may include Memory Controller 125 and clock 205, and clock 205 can be used for coordinating equipment The operation of 105 component.Processor 110 is also coupled to memory 130, memory 130 may include as it is exemplary with Machine access memory (Random Access Memory, RAM), read-only memory (Read-only Memory, ROM) or other State preserving medium.Processor 110 is also coupled to storage equipment 120 and network connector 210, and network connector 210 can To be such as ethernet connector or wireless connector.Processor 110 may be also connected to bus 215, user interface 220 and can It may be attached to bus 215 with the input output interface port and other assemblies that use input/output engine 225 to manage.

Fig. 3 shows the communication path between the storage equipment 120 of the VM and Fig. 1 of Fig. 1, wherein the storage equipment 120 of Fig. 1 Only expose a physical function.In fig. 3 it is shown that three VM 305-1,305-2 and 305-3, they can be in the master of Fig. 1 It is instantiated on machine equipment 105.Although Fig. 3 shows three VM 305-1,305-2 and 305-3, the implementation of present inventive concept Example may include the host equipment 105 for supporting Fig. 1 of any number of VM.

VM 305-1,305-2 and 305-3 can be communicated with management program 310.Management program 310 can create, manage and Run VM 305-1,305-2 and 305-3.Management program 310 is commonly implemented as the processor in the host equipment 105 of Fig. 1 The software run on 110.

In order to realize the interaction with hardware device, especially implement the hardware of single input/output virtualization (SR-IOV), Such hardware device may expose various physical functions.For example, Fig. 3 shows one physical function (PF) 320 of exposure Field programmable gate array (FPGA) 315.

In order to enable VM 305-1,305-2 and 305-3 to interact with hardware device, various virtual functions can also be exposed (VF).VM 305-1,305-2 and 305-3 can be interacted with VF 325-1,325-2 and 325-3, rather than must be straight with hardware Connect interaction.VF 325-1,325-2 and 325-3 provide the virtualization version of PF 320, use different operating system (O/S) VM can effectively interact (for example, using the machine O/S driver) with bottom hardware equipment.Although Fig. 3 shows PF's 320 Three VF, but the embodiment of present inventive concept may include every any number of VF of a PF；And if FPGA 315 (or deposit Store up equipment 120) the more than one PF of exposure, then every PF may have the VF of different number.Exposed each VF may need to come from Some hardware supporteds of underlying device.For example, each VF for the storage exposure of equipment 120 may need additional end trap (endtrap) and doorbell, this needs additional hardware embodiment.

As described above, PF 320 can be exposed by FPGA 315, rather than by the exposure of storage equipment 120, it is to implement PF 320 bottom hardware.FPGA 315 can inquire that storage equipment 120 is exposed with which determining (those) PF by storage equipment 120, Then FPGA 315 oneself exposes comparable (multiple) PF, these PF can be mapped to storage equipment directly across FPGA 315 120 corresponding PF.

Alternatively, PF 320 can be by the directly exposure of storage equipment 120, and VF 325-1,325-2 and 325-3 can be with It is exposed by FPGA 315.The embodiment of the present inventive concept operated using this embodiment can be had to avoid FPGA 315 Implement the hardware PF function of having implemented via storage equipment 120, but be likely larger than storage equipment 120 itself with quantity to provide VF supplement the hardware embodiment.

It either stores equipment 120 or FPGA 315 implements PF 320, FPGA 315 can be inserted in one side Between processor 110 (and management program 310) and storage equipment 120 on the other hand.Management program 310 (thus VM 305- 1,305-2 and 305-3) and storage equipment 120 between any communication all will pass through FPGA 315, so that FPGA315 be allowed to increase The function that strong storage equipment 120 provides is (latent or when storage equipment 120 itself does not provide the embodiment of SR-IOV type It is that storage equipment 120 provides the support of SR-IOV type on ground).

For embodiment, FPGA 315 can be the hardware in storage equipment 120 (that is, storage equipment 120 Can include FPGA 315 in its inside configuration) or FPGA 315 can be storage equipment 120 outside additional hardware, but It is still along the communication path between processor 110 and storage equipment 120.For example, FPGA 315 may be implemented as installing Circuit board in the host equipment 105 of Fig. 1, the circuit board by from FPGA 315 to the connection of storage equipment 120 from periphery Component interconnects quickly (PCIe) bus and receives data.Regardless of FPGA 315 is implemented, FPGA 315 should be in processor Between 110 and storage equipment 120 somewhere, to capture the information of the transmission of management program 310 and execute the function of FPGA 315 Energy.

Management program 310 can capture the request of the control from VM 305-1,305-2 and 305-3, to manage their place Reason.It is set for example, management program 310 can capture the information for being sent to peripheral component interconnection (PCI) configuration space or be sent to storage The request of standby 120 control queue, and processing locality they, redirect requests to FPGA 315, or generate and be similar to The new request of raw requests (although depending on specific request, concrete mode is different).

FPGA 315 is provided better than the advantages of implementing SR-IOV function in equipment 120 is being stored, and wherein FPGA 315 can Programmed at the scene using a part as installation process: storage equipment 120 is usually programmed during manufacture.For example, FPGA 315 can support 100 VF for such as storing equipment, but during installation, client may want to only exposed such as 50 VF (because the host equipment 105 of Fig. 1 may not be able to support so much VM).Then FPGA 315 can be used traditional technology and be compiled Journey leaves not used remaining door (gate) (therefore not consuming power) only to expose 50 VF.For example, FPGA 315 can be with It is programmed with a shell during fabrication, which provides connecing using nonvolatile memory quick (NVMe) order Mouthful.After in the host equipment 105 that FPGA 315 is installed to Fig. 1, these NVMe orders are can be used desirably in client Customize FPGA 315.

FPGA 315 can also be desirably programmed in terms of it can support which parameter.For example, such as below with reference to Fig. 9 It is discussed, there are many different variations in qos requirement.But FPGA 315 can be programmed to only consider bandwidth, and ignore Parameter relevant to the quantity of quantity or byte that the I/O of processing per second is requested.For other of expansion I/O queue creation order Parameter, it is same a possibility that also set up.

Fig. 4 shows the communication path between the storage equipment 120 of the VM and Fig. 1 of Fig. 1, wherein the storage equipment 120 of Fig. 1 Expose multiple physical functions.Fig. 4 is identical as Fig. 3, in addition to not instead of one PF 320 of exposure, three PF of exposure in Fig. 4 320,405 and 410, wherein for each PF one VF 325-1,325-2 of exposure and 325-3.Although Fig. 4 shows FPGA 315 three PF 320,405 and 410 of exposure, but the embodiment of present inventive concept can be supported to expose any number of PF, and And any number of VF 325-1,325-2 and 325-3 can be exposed for each PF.Due to many, it may expose more A PF: for example, the amount of storage that storage equipment 120 provides may be unable to fully support very much greatly for single PF.Each PF is logical Often need some special hardware supporteds.Therefore, the PF to be exposed is more, and more hardware is usually required in underlying device, from And chip size and power consumption are increased, and potentially reduce its performance checked by single VM.Each PF can provide different Function or multiple PF can provide identical function (individual equipment is enable once to provide support to more than one VM).

In Fig. 3-Fig. 4, the institute of the support described herein for providing SR-IOV type is functional can be in FPGA 315 Implement or some (or whole) can implement in the storage 120.For example, in some embodiments of present inventive concept, Storage equipment 120 can be conventional memory device, not provide the built-in support of the function to any SR-IOV type, wherein FPGA 315 are responsible for the function of all SR-IOV types.In the other embodiments of present inventive concept, storage equipment 120 can be provided pair The support (below with reference to Fig. 5-Fig. 6 discussion) of expansion I/O queue creation order, and if storage equipment 120 includes enough I/O queue, IOQ support the VM of anticipated number, then FPGA 315 can only provide VF 325-1,325-2 and 325-3, and will I/O request management from VM is " straight-through " equipment.In the another embodiment of present inventive concept, storage equipment 120 can be mentioned For the support to expansion I/O queue creation order, but will be more than the I/O queue, IOQ of storage equipment 120 because the quantity of VM is expected Quantity, so FPGA 315 still may be created in internal control I/O queue, IOQ: then storage equipment 120 may be considered as passing System storage equipment, although supporting expansion I/O queue creation order.

Fig. 5 shows the details of the storage equipment 120 of Fig. 1.In Fig. 5, storage equipment 120 may include host interface 505, the communication of management and the host equipment 105 of Fig. 1.Store equipment 120 can also include storage device 510, storage by The real data of VM 305-1,305-2 and the 305-3 access of Fig. 3.Memory 510 can take any desired form: example Such as, if storage equipment 120 is solid state drive (SSD), storage device 510 can take the form of flash memory, and if deposited Storing up equipment 120 is hard disk drive, then storage device 510 can take the form of disk.Storing equipment 120 can also include door Bell distributed logic 515, doorbell distributed logic 515 can be distributed doorbell across the internal storage of storage equipment 120, so that each door In the different pages of the internally positioned memory of bell (wherein the size of the page can according to the page-size of the memory 130 of Fig. 1 come It determines).By the way that doorbell to be placed in the different pages, different VM accesses the different pages to access their (multiple) door Bell, (this will be disobeyed a possibility that may needing to access doorbell of the same locked memory pages to access them so as to avoid multiple VM Carry on the back the target of VM isolation).And although Fig. 5 shows a part of doorbell distributed logic 515 as storage equipment 120, this Doorbell distributed logic 515 can also be placed in the FPGA 315 of Fig. 3 by the embodiment of inventive concept.Doorbell distribution will be below It is further discussed with reference to Fig. 8.

It may include other conventional hardwares and/or circuit in the storage 120 that Fig. 5, which is not shown, such as SSD Flash translation layer (FTL) (Flash Translation Layer, FTL) and read/write circuit, or for hard disk drive reading/ Write header (head).It may include additional optional component in the storage 120 that Fig. 5, which is also not shown, and such as high speed is slow It deposits.The embodiment of present inventive concept is expanded to including all such traditional components.

Storage equipment 120 can be used any desired interface to communicate with the host equipment 105 of Fig. 1.For example, storage is set Standby 120 can be used NVMe interface, or serial AT attachment interface can be used in storage equipment 120.Similarly, equipment is stored 120 can be used any desired connection mechanism to be connected to host equipment 105, including such as PCI or PCIe (using 4,8 or The channel PCI of any other quantity), M.2 with SATA and other may.The embodiment of present inventive concept be intended to include connection and All changes on interface.

Storage equipment 120 can also include that can be used for requesting to submit and responding I/O queue, IOQ (the also referred to as I/O team returned Column to): submit queue (submission queue, SQ) can be used to submit I/O request (such as to read by the VM 305-1 of Fig. 3 Or write request), and complete queue (completion queue, CQ) and can be used to return result to by storage equipment 120 The VM 305-1 of Fig. 3.In Fig. 5, storage equipment 120 is shown as including three I/O queue, IOQs 520-1,520-2 and 520-3, divides There is not submit queue 525-1,525-2 and 525-3 and be respectively provided with and complete queue 530-1,530-2 and 530-3.Although figure 5 suggest that each submission queue 520-1,520-2 and 520-3 have corresponding completion queue 525-1,525-2 and 525-3, still The embodiment of present inventive concept can support to include the single completion queue from multiple results for submitting queue.

Storage equipment 120 may include supporting that 535 electricity can be ordered by the I/O queue, IOQ creation that storage equipment 120 provides Road.It is created using I/O queue, IOQ and orders the management program 310 of 535, Fig. 3 or the FPGA 315 of Fig. 3 that can request to establish I/O queue, IOQ For using.But although conventional memory device (such as those storage equipment for supporting NVMe interface) can provide standardization Form I/O queue, IOQ creation order 535, but shown in I/O queue, IOQ creation order 535 represent extension I/O queue, IOQs create life It enables, to provide the additional attribute that traditional I/O queue, IOQ creation order is not provided or do not supported.

Fig. 6 shows the expansion I/O queue creation order 535 of Fig. 5 of the storage equipment 120 for Fig. 1.In Fig. 6, show I/O queue, IOQ creation order 535 is gone out.I/O queue, IOQ creation order 535 may include the I/O team as traditional NVMe specification definition The parameter of a part of column creation order, such as queue size 603 (should be the queue assignment how many space established), queue Identifier 606 (identifier for the submission queue established) completes queue identifier 609 (identifier for completing queue), team Column priority 612 (relative priority for the submission queue established) and (the instruction submission queue and complete of physics continuous mark 615 It is whether physically continuous at queue).But in addition, I/O queue, IOQ creation order 535 may include other attributes.These attributes Including logical block address (LBA) range attribute 618, service quality (QoS) attribute 621 and shared namespace attribute 624.LBA Range attribute 618 can specify the range of LBA associated with VM 305-1.Use LBA range attribute 618, the FPGA of Fig. 3 The storage equipment 120 of 315 or Fig. 1 can be with physical block address (the Physical Block in the storage equipment 120 of distribution diagram 1 Address, PBA) a part for the VM use, without by other VM use (although exception that the rule is discussed below). By the way that the range of LBA and the corresponding range of PBA is isolated, VM isolation can be provided.

How the physical storage device that Fig. 7 shows the storage equipment 120 of Fig. 1 is divided into the example of multiple NameSpaces. In fig. 7 it is shown that the storage device 510 of the 1TB of Fig. 5, although the embodiment of present inventive concept can support to have it is any total The storage equipment of capacity.The storage device 510 of this 1TB of Fig. 5 be illustrated as being divided into three NameSpaces 705-1,705-2 and 705-3, but the storage device 510 of Fig. 5 can be divided into any number of NameSpace by the embodiment of present inventive concept.

Each NameSpace has the associated range of LBA.Therefore, NameSpace 705-1 includes the range 710- of LBA 1, NameSpace 705-2 include that the range 710-2 and NameSpace 705-3 of LBA include the range 710-3 of LBA.Correspond to Each range 710-1,710-2 and 710-3 of LBA, range 715-1,715-2 and 715-3 of PBA can establish depositing in Fig. 5 In storage device 510.Each range 715-1,715-2 and 715-3 of PBA should be at least big as corresponding range with LBA's, so as to Each LBA in given LBA range has corresponding PBA.It is noted that LBA is not necessarily with PBA and to be consistent (coincidental): for example, the range 710-2 of LBA is from LBA0 is started, to LBA 134,217,727 is terminated, (this can be example Such as block address, wherein each piece of data including 4096 bytes: this block address corresponds to byte address 549,755,813,887), And the range 715-2 of PBA from start PBA 67,108,864 (byte address 274,877,906,944) to end PBA 201, 326,591 (byte address 824,633,720,831).

By LBA range be mapped to PBA and by one (or two) one associated with I/O queue, IOQ in these ranges it is excellent Point is that such mapping can be to avoid mixer effect.Mixer effect is the knot how conventional memory device handles I/O request Fruit.When I/O request is still in I/O queue, IOQ, I/O request has some residual contexts.But once I/O request reaches FTL, Any such context can all be lost: all I/O requests seem to be the same at that time.As a result, the storage equipment of Fig. 1 120 will not ensure that the qos requirement of special VM.But if PBA can map (itself is reversible) via LBA-PBA It is coupled (tied) and returns special I/O queue, IOQ, then the qos requirement of the I/O queue, IOQ still can be determined by the storage equipment 120 of Fig. 1 Position and satisfaction.

It is worth noting that, each NameSpace 705-1,705-2 and 705-3 have the NameSpace identifier of their own (ID).In some embodiments of present inventive concept, these NameSpaces ID can correspond to the queue identifier as Fig. 6 606 queue identifiers provided.

Fig. 6 is returned to, LBA range attribute 618 can be indicated with various ways.For example, LBA range attribute 618 may include LBA, which starts 627 and LBA, terminates 630, they provide the LBA's in range 710-1,710-2 and 710-3 of the LBA of Fig. 7 Start and end address.Alternatively, given LBA starts 627 and queue size 603, it is possible to infer that LBA terminates 630, this will Permitting omission LBA terminates 630.The structure of expansion I/O queue creation order 535 can be established to support LBA range attribute 618 On any desired variation, as needed include and/or omit parameter.

QoS attribute 621 can indicate any desired QoS regulation.For example, being established by I/O queue, IOQ creation order 535 Queue can be associated with the VM with Service Level Agreement (SLA), which attempts to ensure that the spy of VM user Other service class.Any desired form can be used to indicate in QoS attribute 621.Some exemplary forms shown in fig. 6 include most It is small guarantee bandwidth 633, it is maximum guarantee bandwidth 636, the minimum number 639 of read requests per second, read requests per second maximum number The minimum of amount 642, the minimum number 645 per second for reading byte, the maximum quantity 648 per second for reading byte, write request per second Quantity 651, the maximum quantity 654 of write request per second, the minimum number 657 of write-in byte per second and write-in byte per second are most Big quantity 660.It is noted that tradition SR-IOV solution depends on the management program 310 of Fig. 3 to manage qos requirement；This hair This management can be transferred to the storage equipment 120 of the FPGA 315 or Fig. 1 of Fig. 3 by the embodiment of bright design, to reduce Fig. 3 Management program 310 on load and host CPU load, and thus improve overall system performance.Expansion I/O queue creation order 535 structure can be established to support any desired variation on QoS attribute 621, include as needed and/or omission is joined Number.

Physics is deposited finally, shared namespace attribute 624 can indicate that the VM for being intended to request creation I/O queue, IOQ is shared The list of the NameSpace of the access of storage device.The concept of shared namespace attribute represents the exception of the concept of VM isolation: such as The shared access to common data sets of fruit virtual machine, then they may not be isolated.But since there may be multiple VM to need The situation of shared information is wanted, and shares the visit for comparing the message data between VM to the access of common data sets for them It asks more effectively, shared namespace attribute 624 provides this solution.Shared namespace attribute 624 can be with any Desired mode is implemented: including shared NameSpace ID array 663, the array column another example is I/O queue, IOQ creation order 535 The NameSpace ID that the VM of share and access is carried out to data set is gone out.

Fig. 8 shows the memory mapping of the doorbell in the storage equipment 120 of Fig. 1, to support VM to be isolated.Using doorbell In the conventional memory device communicated between the host equipment 105 of Fig. 1 and the storage equipment 120 of Fig. 1, there can be multiple doorbells: For example, each of I/O queue, IOQ 520-1,520-2 and 520-3 of Fig. 5 have a doorbell.In order to support VM 305-1, 305-2 and 305-3 accesses these doorbells, and the storage equipment 120 of Fig. 1 can be requested the address space of the host equipment 105 of Fig. 1 A part distribute to storage equipment 120.Then, the address in the address space of the host equipment 105 of Fig. 1, which may map to, deposits Store up the storage address of equipment 105.Then, the management program 310 of Fig. 3 can be mentioned to VM 305-1,305-2 and 305-3 of Fig. 3 For the address of doorbell, enable VM 305-1,305-2 and the 305-3 of Fig. 3 by using the address of the host equipment 105 of Fig. 1 Address in space accesses doorbell.

But in the Conventional implementations of the storage equipment 120 of Fig. 1, these doorbells may reside within the continuous of memory In section: Fig. 8 illustrates this point.In fig. 8 it is shown that memory 805, the storage equipment 120 or Fig. 3 of Fig. 1 are indicated Memory in FPGA 315.Storage address 810-1,810- of the doorbell of I/O queue, IOQ 520-1,520-2 and 520-3 of Fig. 5 2 and 810-3 is shown to occupy the continuous section of memory, and is entirely located in the single page of memory 805.Although Fig. 8 It shows three doorbells and occupies storage address 810-1,810-2 and 810-3, but the embodiment of present inventive concept may include Any amount of doorbell.In the case of the host equipment 105 of Fig. 1 is as individual equipment operation (not virtualizing), this cloth It is good to set work.But in the case where the host equipment of Fig. 1 105 supports the multiple virtual machines for needing to be isolated, make all doorbells Dwelling in the same page of memory 805 means that VM must share the access to the same page of memory, this violation The requirement of VM isolation.

In order to solve this difficulty, the storage equipment 120 of Fig. 1 or the FPGA 315 of Fig. 3, depend on which equipment provides door Bell can position doorbell storage address, as shown in memory 815 in the different pages of the memory 130 of Fig. 1.Fig. 1's How the FPGA 315 for storing equipment 120 or Fig. 3 positions the example of doorbell storage address in September, 2015 in the different pages It is shown in the U.S. Patent Application Serial Number 14/862,145 submitted for 22nd, this application is now arranged in pending state, and this application is Through being incorporated herein by reference as 2016/0306580 disclosure of U.S. Patent Publication No..By using doorbell span value (stride value), doorbell storage address can be shifted such that each doorbell is located at the storage equipment 120 or Fig. 3 of Fig. 1 FPGA 315 the different pages in (in this context, term " the different pages " be intended to description interval so that the host of Fig. 1 Size of the corresponding doorbell address based on the page in O/S memory in the address space of equipment 105 and be located at the different pages In).Then, because doorbell is located in the different pages in the storage equipment 120 of Fig. 1 or the FPGA 315 of Fig. 3, Fig. 1's Corresponding address in the address space of host equipment 105 also is located in the different pages of O/S memory.Thus, for example, storage Device address 810-1 may map to storage address 820-1, and storage address 810-2 may map to storage address 820- 2, storage address 810-3 may map to storage address 820-3, etc..Due to the page 825-1,825-2,825-3 and 825-4 can represent the different pages of memory, and after this mapping, each doorbell may reside within memory 815 not With in the page.As a result, the access of the single page of the not shared memory 130 to Fig. 1 of VM accesses doorbell, thus support VM every From.

In Fig. 5-Fig. 7, description concentrates on providing the storage equipment of Fig. 1 of the expansion I/O queue creation order 535 of Fig. 5 In the storage equipment 120 for Fig. 1 that 120 and realization VM is isolated.Although the storage equipment 120 of Fig. 1 may include that VM is supported to be isolated Necessary hardware, but not each storage equipment must include the hardware.But by systems including the FPGA of Fig. 3 315, even if the embodiment of present inventive concept can also prop up when the storage equipment 120 of Fig. 1 does not include hardware needed for SR-IOV Hold the access of VM isolation and the SR-IOV type to the storage equipment 120 of Fig. 1.In addition, even if working as storage equipment 120 of Fig. 1 When machine supports SR-IOV, the function of the storage equipment 120 of Fig. 1 is also can be enhanced in the FPGA 315 including Fig. 3 in systems.

Firstly, FPGA 315 may include the necessary hardware for supporting VM isolation.Fig. 3 is referred back to, since Fig. 1 will be sent to Each request of storage equipment 120 may pass through the FPGA 315 of Fig. 3, so FPGA 315 can intercept plan by Fig. 1 The received request of storage equipment 120.For example, if the storage equipment 120 of Fig. 1 does not support the expansion I/O queue of Fig. 5 to create life 535 are enabled, then the FPGA 315 of Fig. 3 can intercept any such request, and oneself disposition I/O queue, IOQ creation.The FPGA of Fig. 3 315 can send traditional I/O queue, IOQ creation order, while oneself management VM isolation to the storage equipment 120 of Fig. 1, to provide QoS guarantee, and NameSpace is shared in due course.For this purpose, the FPGA 315 of Fig. 3 may include the storage equipment similar to Fig. 1 The hardware that may otherwise include in 120.The FPGA 315 of Fig. 3 can determine that the request of the special I/O in I/O queue, IOQ is No in the range of 710 LBA associated with the I/O queue, IOQ (or a part of shared NameSpace).The FPGA315 of Fig. 3 can It is requested with the I/O of the storage equipment 120 for the Fig. 1 to be sent to that organizes and sort, in order to provide QoS guarantee.

In order to support I/O queue, IOQ creation and VM isolation, the FPGA315 of Fig. 3 may include virtual i/o queue creation order 903, as shown in Figure 9.Virtual i/o queue creation order 903 is very similar to the I/O queue, IOQ creation order 535 of Fig. 6, and wraps Include similar parameter and attribute.Main difference is that the I/O queue, IOQ creation order 535 in view of Fig. 6 is intended to be set by the storage of Fig. 1 Standby 120 processing (although as described above, the FPGA 315 of Fig. 3 can intercept the I/O queue, IOQ creation order 535 of Fig. 6, and instead Inter-process), and the FPGA315 of Fig. 3 is directed toward in virtual i/o queue creation order 903, without being intended to the storage equipment by Fig. 1 120 processing.

Because virtual i/o queue creation order 903 be intended to realize be similar to I/O queue, IOQ creation order 535 as a result, Virtual i/o queue creation order 903 may include with the similar attribute of properties/parameters of the I/O queue, IOQ of Fig. 9 creation order 535/ Parameter.Therefore, virtual i/o queue creation order may include the parameter as a part of traditional I/O queue, IOQ creation order, all Such as queue size 906 (should be the queue assignment how many space established), (the submission team established of queue identifier 909 The identifier of column), complete queue identifier 912 identifier of queue (complete), (submission established of queue priority 915 The relative priority of queue) and physics continuous mark 918 (whether instruction submits queue and completion queue physically continuous).It is empty Quasi- I/O queue, IOQ creation order 903 can also include extended attribute, such as LBA range attribute 921, QoS attribute 924 and shared life Name space attribute 927.

Just as the I/O queue, IOQ of Fig. 5 creation order 535, LBA range attribute 921 can be indicated with various ways.Example Such as, LBA range attribute 921 may include that LBA starts 930 and LBA and terminates 933, they provide the LBA range 710- in Fig. 7 1, the start and end address of the LBA in 710-2 and 710-3.Alternatively, given LBA starts 930 and queue size 906, has It may infer that LBA terminates 933, this, which will permit omission LBA, terminates 933.The structure for extending virtual i/o queue creation order 903 can Support any desired variation on LBA range attribute 921 to be established, include as needed and/or omit parameter.

Similarly, QoS attribute 924 can indicate any desired QoS regulation.For example, being created by virtual i/o queue The queue that order 903 is established can be associated with the VM with SLA, which attempts to ensure that the special service class of VM user. Any desired form can be used to indicate in QoS attribute 924.Some exemplary forms shown in Fig. 9 include minimum guarantee bandwidth 936, it is maximum guarantee bandwidth 939, the minimum number 942 of read requests per second, read requests per second maximum quantity 945, per second Read minimum number 948, the minimum number 954, every per second for reading the maximum quantity 951 of byte, write request per second of byte The maximum quantity 963 of the maximum quantity 957 of second write request, the minimum number 960 of write-in byte per second and write-in byte per second. The structure of extension virtual i/o queue creation order 903 can be established to support any desired variation on QoS attribute 924, As needed include and/or omit parameter.

Physics is deposited finally, shared namespace attribute 927 can indicate that the VM for being intended to request creation I/O queue, IOQ is shared The list of the NameSpace of the access of storage device.The concept of shared namespace attribute represents the exception of the concept of VM isolation: such as The shared access to common data sets of fruit virtual machine, then they may not be isolated.But since there may be multiple VM to need The situation of shared information is wanted, and shares the visit for comparing the message data between VM to the access of common data sets for them It asks more effectively, shared namespace attribute 927 provides this solution.Shared namespace attribute 927 can be with any Desired mode is implemented: including shared NameSpace ID array 966, the battle array another example is virtual i/o queue creation order 903 List the NameSpace ID that the VM of share and access is carried out to data set.

It is noted that the storage equipment 120 of Fig. 1 may include the I/O of Fig. 6 in some embodiments of present inventive concept Queue creation order 535, and therefore can support creation I/O queue, IOQ and assign them to VM 305-1,305-2 and 305-3. In such embodiment of present inventive concept, the FPGA 315 of Fig. 3 can simply accept (take) virtual i/o queue creation Order 903, and the 535 storage equipment 120 for being sent to Fig. 1 are ordered as the creation of the I/O queue, IOQ of Fig. 5, rather than Fig. 3's Virtual i/o queue creation order 903 is handled in FPGA 315 to create virtual i/o queue.

But what the FPGA 315 of Fig. 3 can do is not only operation that SR-IOV type is supported in unloading (offload) Hardware (FPGA 315 for permitting Fig. 3 does not include that the storage equipment of hardware of SR-IOV type is used together with itself).Fig. 3's FPGA 315 can also extend the quantity of the I/O queue, IOQ by the storage equipment 120 " offer " of Fig. 1.Because of the host equipment of Fig. 7 Each VM on 105 needs access of the their own to the storage equipment 120 of Fig. 1, so each of on the host equipment 105 of Fig. 1 VM needs to access VF and I/O queue, IOQ of the their own in the storage equipment 120 of Fig. 1.But what the storage equipment 120 of Fig. 1 was supported The quantity of VF and I/O queue, IOQ can indicate the upper of the quantity of the VM of the storage equipment 120 of accessible Fig. 1 at any point in time Boundary.The quantity for the VM that the management program 310 (and processor 110 of Fig. 1) that this upper bound is probably well below Fig. 3 can be supported, This means that or VM the resource of the host equipment 105 of the storage equipment 120 or Fig. 1 that cannot access Fig. 1 will be idle.

The FPGA 315 of Fig. 3 can solve this problem by providing additional virtual i/o queue, the virtual i/o team The quantity of column may be significantly larger than the quantity of the I/O queue, IOQ (and PF/VF) directly provided by the storage equipment 120 of Fig. 1.Figure 10 Show such case.

In FIG. 10, it is assumed that I/O queue, IOQ 520-1,520-2 and 520-3 expression are provided only by the storage equipment 120 of Fig. 1 (in fact, the quantity of I/O queue, IOQ is greater than three, but the host equipment 105 generally still less than Fig. 1 can prop up one I/O queue, IOQ simultaneously The quantity of the VM held).If the host equipment 105 of Fig. 1 is currently running more than three VM, if that the storage equipment 120 of Fig. 1 It is the sole source of I/O queue, IOQ, then one or more VM will be without available I/O queue, IOQ.But virtual i/o is supported in FPGA 315 In the case where queue, the storage equipment 120 of the still accessible Fig. 1 of these additional VM.

When the management program 310 of Fig. 3 issues virtual i/o queue creation order 903 provided by FPGA 315, FPGA 315 can establish new virtual i/o queue.Figure 10 show five virtual i/o queue 1005-1,1005-2,1005-3, 1005-4 and 1005-5, but FPGA 315 can support any number of virtual i/o queue (to limit by the door in FPGA 315 Quantity define).Each virtual i/o queue includes the submission queue and completion queue of oneself.Therefore, virtual i/o queue 1005-1,1005-2,1005-3,1005-4 and 1005-5 respectively include submitting queue 1010-1,1010-2,1010-3,1010- 4 and 1010-5, and respectively include completing queue 1015-1,1015-2,1015-3,1015-4 and 1015-5.

Each virtual i/o queue then can be associated with (hardware) I/O queue, IOQ of storage equipment 120 of Fig. 1.FPGA 315 can be used mapping logic 1020, and any desired method can be used by virtual i/o queue 1005-1 to 1005-5 group It is made into group, and maps them into (hardware) I/O queue, IOQ 520-1,520-2 and 520-3.For example, in Figure 10, mapping logic 1020 can choose virtual i/o queue 1005-1 and 1005-2 to form associated with I/O queue, IOQ 520-1 group of 1025-1, select Virtual i/o queue 1005-3 (itself) is selected to form associated with I/O queue, IOQ 520-2 group of 1025-2, and selection virtual i/o Queue 1005-4 and 1005-5 is to form associated with I/O queue, IOQ 520-3 group of 1025-3.Therefore, VM of the FPGA 315 from Fig. 3 The received any I/O request of 305-1,305-2 and 305-3 can be " positioned " in virtual submission queue appropriate, then by Correct (hardware) for being transmitted to the storage equipment 120 of Fig. 1 submits queue.Similarly, the received response of queue is completed from (hardware) It can be " positioned " in correctly virtual completion queue, and " return " arrives VM appropriate.

Mapping logic 1020 can be used any desired method and be organized into virtual i/o queue 1005-1 to 1005-5 Group, wherein each group associated with special (hardware) I/O queue, IOQ.For example, mapping logic 1020 can by virtual i/o queue with Machine distributes to group.Alternatively, mapping logic 1020 can in a manner of circulation (round-robin) by virtual i/o queue assignment to group: First virtual i/o queue assignment give first group, the second virtual i/o queue assignment give second group, and so on, until all groups all There is a virtual i/o queue, hereafter, and since first group, by virtual i/o queue assignment to group.Alternatively, mapping logic 1020 Can VM 305-1,305-2 and 305-3 based on Fig. 3 expection I/O load by virtual i/o queue assignment to group, it is flat to attempt I/O load between weighing apparatus group.Alternatively, mapping logic 1020 can be based upon the phase that VM 305-1,305-2 and 305-3 of Fig. 3 are specified To priority by virtual i/o queue assignment to group (it is noted that the queue priority 612 of Fig. 6 is traditional NVMe specification definition A part of I/O queue, IOQ creation order and the queue priority 915 of Fig. 9 are the virtual i/o queue creation orders 903 of Fig. 9 A part).Alternatively, mapping logic 1020 can the QoS attribute 924 based on Fig. 9 by virtual i/o queue assignment to group, to attempt Meet the qos requirement of VM 305-1,305-2 and 305-3.The embodiment of present inventive concept can also be determined using other methods Which virtual i/o queue assignment given to which group.

Since FPGA 315 knows which LBA is associated with each virtual i/o queue (via the LBA range attribute of Fig. 9 The shared namespace attribute 927 of 921 and/or Fig. 9), so FPGA 315 can be not suitable for the virtual i/o queue by refusal I/O request to force VM to be isolated.Similarly, because FPGA 315 knows the qos requirement of VM (via the QoS attribute of Fig. 9 924), thus FPGA 315 can in a manner of meeting the qos requirement of each VM by I/O request be forwarded to I/O queue, IOQ 520-1, 520-2 and 520-3.Thus, for example, if VM has been set up the qos requirement of at least ten I/O request per second (assuming that may I/O request is etc. (pending) to be processed), then FPGA 315 can be asked in I/O of the forwarding from other virtual i/o queues Priority processing carrys out the I/O request of self-corresponding virtual i/o queue before asking.(some are random for this example, as it implies that not having Other VM are with qos requirement: in the case where multiple VM have qos requirement, FPGA 315 can be wanted with meeting all VM QoS The mode asked manages I/O request).Other qos requirements, such as bandwidth requirement can similarly be disposed via FPGA 315.

Figure 11 shows 305 distribution diagram of VM that the storage equipment 120 of the Fig. 1 for the embodiment conceived according to the present invention is Fig. 3 The flow chart of the instantiation procedure of 5 I/O queue, IOQ 520.In Figure 11, at block 1105, the storage equipment 120 of Fig. 1 can be from Fig. 3 Management program 310 receive Fig. 5 I/O queue, IOQ creation order 535.Alternatively, at block 1110, the storage equipment 120 of Fig. 1 The I/O queue, IOQ creation order 535 of Fig. 5 can be received from the FPGA 315 of Fig. 3.In any case, the I/O queue, IOQ creation of Fig. 5 Order 535 may include the range 710 of the LBA of Fig. 7.Regardless of the source of the I/O queue, IOQ creation order 535 of Fig. 5, in block 1115 Place, the storage equipment 120 of Fig. 1 can establish the I/O queue, IOQ 520 of Fig. 5.At block 1120, the storage equipment 120 of Fig. 1 can be selected Select the range 715 of the PBA of Fig. 7 of the sufficiently large range 710 with the LBA for supporting the Fig. 7 received.At block 1125, Fig. 1's is deposited The range 710 of the LBA of Fig. 7 can be mapped to the range 715 of the PBA of Fig. 7 by storage equipment 120.In this way, working as the storage equipment of Fig. 1 120 receive I/O request when, the range 715 of the PBA of Fig. 7 of the VM 305 corresponding to Fig. 3 can be only accessed, thus by each VM is isolated with other VM.In a similar way, due to reflecting between the range 710 of the LBA of Fig. 7 and the range 715 of the PBA of Fig. 7 It penetrates and is reversible, therefore, give special physical address, can determine the suitable context of I/O request, make it possible to select to fit When completion queue come notify Fig. 3 VM 305I/O request be completed, as Figure 11 block 1130 in proposed by (wherein I/O is asked The success asked may return to the VM 305 of Fig. 3).

It is noted that block 1105 and 1110 suggests the expansion I/O queue creation order 535 using Fig. 5, but regardless of Fig. 5's How is the source of I/O queue, IOQ creation order 535.It is of the invention although a possibility that embodiment of present inventive concept includes such The other embodiments of design may include the storage equipment 120 of Fig. 1, and the expansion I/O queue of Fig. 5 is not supported to create order 535. In these embodiments of present inventive concept, the FPGA 315 of Fig. 3 can support to simulate SR- using the storage equipment 120 of Fig. 1 The institute of IOV is functional, and the storage equipment 120 of Fig. 1 handles I/O in the case where any context that no I/O is requested and asks It asks.In other words, the FPGA 315 of Fig. 3 can support all context managements and VM to be isolated, and make the storage equipment 120 of Fig. 1 It is operated for conventional memory device, any function without implementing present inventive concept.

Figure 12 shows 305 distribution diagram 10 of VM that the FPGA 315 of the Fig. 3 for the embodiment conceived according to the present invention is Fig. 3 Virtual i/o queue 1005 instantiation procedure flow chart.In Figure 12, at block 1205, the FPGA 315 of Fig. 3 can be from figure 3 management program 310 receives the virtual i/o queue creation order 903 of Figure 10.At block 1210, the FPGA 315 of Fig. 3 can be The VM 305 of Fig. 3 establishes the virtual i/o queue 1005 of Figure 10.At block 1215, the FPGA 315 of Fig. 3 can be to the storage of Fig. 1 Equipment 120 sends the I/O queue, IOQ creation order 535 of Fig. 5.It is noted that being sent to if the storage equipment 120 of Fig. 1 is supported The I/O queue, IOQ creation order 535 of Fig. 5 of the storage equipment 120 of Fig. 1 can be the extended version of the order, or if not prop up It holds, then can be traditional I/O queue, IOQ creation order.At block 1220, the FPGA 315 of Fig. 3 can be from the storage equipment 120 of Fig. 1 Receive the result of the I/O queue, IOQ creation order 535 of Fig. 5.

At block 1225, the virtual i/o queue 1005 of Figure 10 can be mapped to by Fig. 1's by the mapping logic 1020 of Figure 10 Store the I/O queue, IOQ 520 for Fig. 5 that equipment 120 is established.At block 1230, the FPGA 315 of Fig. 3 can be by the range of the LBA of Fig. 7 710 is associated with the virtual i/o queue 1005 of Figure 10.Finally, the FPGA 315 of Fig. 3 can be to the management of Fig. 3 at block 1235 Program 310 returns to success indicators.

What several annotations above Figure 12 were ordered into.Although firstly, note that in the block 1105 and 1110 of Figure 11, Fig. 1 Storage equipment 120 may not receive the expansion I/O queue creation order of Fig. 5 and 535 (implement the present invention in the FPGA 315 of Fig. 3 Design functional and Fig. 1 storage equipment 120 be in the embodiment of present inventive concept of conventional memory device), still The FPGA 315 of Fig. 3 is not but in this way.Any order of the storage equipment 120 of Fig. 1 is sent to from the management program 310 of Fig. 3, or Person is sent to any I/O request of the storage equipment 120 of Fig. 1 from the VM 305 of Fig. 3, all passes through the FPGA 315 of Fig. 3.Due to this The order of sample will include I/O queue, IOQ creation order (actual or virtual), it is possible to it is expected that the FPGA 315 of Fig. 3 is received The I/O queue, IOQ of extension creates order.If the I/O queue, IOQ creation order 535 of Fig. 5 can be implemented in the storage equipment 120 of Fig. 1, The FPGA 315 of Fig. 3 does not need to receive the virtual i/o queue creation order 903 of Figure 10 (although the implementation of present inventive concept at all Example may include that the management program 310 of Fig. 3 sends the virtual i/o queue creation order 903 of Figure 10 to the FPGA 315 of Fig. 3, will Its FPGA 315 for leaving Fig. 3 for oneself to execute order or issues the I/O queue, IOQ creation life of Fig. 5 to the storage equipment 120 of Fig. 1 It enables 535).And queue is distributed to VM and context management, the FPGA 315 of Fig. 3 will be wished if the FPGA 315 of Fig. 3 is executed Hope the virtual i/o queue creation order 903 for receiving Fig. 9.

Second, it is noted that, block 1215 and 1220 assumes that the I/O queue, IOQ 520 of Fig. 5 is not yet established in storage equipment 120.Such as Fruit during execution, establish in the storage equipment 120 of Fig. 1 (for example, if the FPGA of Fig. 3 by the I/O queue, IOQ 520 of Fig. 5 315 are being mapped to multiple virtual i/o queues 1005 of Figure 10 the independent I/O queue, IOQ of Fig. 5 in the storage equipment 120 of Fig. 5 520), then block 1215 and 1220 can be omitted, as shown in dotted line 1240.

Third, the FPGA 315 of Fig. 3 may not be needed the contextual information of the virtual i/o queue 1005 of storage Figure 10.Example Such as, if the range 710 of the LBA of Fig. 7 is mapped to the range 715 of the PBA of Fig. 7 by the storage equipment 120 of Fig. 1, and pass is stored In the contextual information of the VM 305 of Fig. 3 of the I/O queue, IOQ 520 of Fig. 5, then block 1230 can be omitted, as shown in dotted line 1245.

The management program 310 that Figure 13 shows the Fig. 3 for the embodiment conceived according to the present invention handles the VM from Fig. 3 The flow chart of the instantiation procedure of the control request of 305-1,305-2 and 305-3.In Figure 13, at block 1305, the management of Fig. 3 Program 310 can receive control request from the VM 305 of Fig. 3.At block 1310, the management program 310 of Fig. 3 can capture this and ask It asks.Then, at block 1315, the management program 310 of Fig. 3 can send different (if similar to the FPGA 315 of Fig. 3 Words) request: second request can simulate raw requests.At block 1320, the management program 310 of Fig. 3 can be from the FPGA of Fig. 3 315 reception results.It is noted that the FPGA 315 of Fig. 3 may be in the request of inter-process second or the FPGA of Fig. 3 The management program 310 for the storage equipment 120: Fig. 3 that the request of their own is forwarded to Fig. 1 may be indifferent to Fig. 3's by 315 How FPGA 315 handles the second request.Finally, the management program 310 of Fig. 3 can return the result to Fig. 3 at block 1325 VM 305.

Figure 14 show the embodiment conceived according to the present invention for the storage equipment 120 of Fig. 1 or the FPGA 315 of Fig. 3 The example mistake that the storage address 810 of Fig. 8 of doorbell is mapped to the different operating system page 825 of Fig. 8 to support VM to be isolated The flow chart of journey.It is noted that no matter instantiation procedure is implemented by the storage equipment 120 of Fig. 1 or the FPGA 315 of Fig. 3, Instantiation procedure is all identical.For descriptive purposes, the FPGA 315 of Fig. 3 will be described as executing instantiation procedure, still The embodiment of present inventive concept expands to the storage equipment 120 for also executing Fig. 1 of instantiation procedure.

In Figure 14, at block 1405, the FPGA 315 of Fig. 3 can identify FPGA's 315 for managing Fig. 3 and Fig. 3 The doorbell of communication between VM 305.At block 1410, the FPGA 315 of Fig. 3 can be based on the figure in the host equipment 105 of Fig. 1 The page-size of 1 memory 130, the storage address 820 of distribution map 8 in different locked memory pages.For example, Fig. 3 The doorbell storage address 820 that doorbell span value to position Fig. 8 in the different pages can be used in FPGA 315.In block 1415 Place, the FPGA 315 of Fig. 3 can be to the 105 request address space of host equipment of Fig. 1.At block 1420, FPGA 315 can be incited somebody to action The storage address 820 of Fig. 8 is mapped to the storage address in requested address space.In this way it is possible to keep VM Isolation, because there are two their the accessible doorbells on the common storage page of VM 305.At block 1425, Fig. 3's FPGA 315 can provide the new storage address 820 of Fig. 8 to the VM 305 of Fig. 3.

At block 1430, the FPGA 315 of Fig. 3 can receive request from the VM 305 of Fig. 3 to access the memory in mapping Doorbell at address.At block 1435, the FPGA 315 of Fig. 3 can be inverted mapping, restore the original memory addresses of Fig. 8 820.At block 1440, the FPGA 315 of Fig. 3 can transmit the request to the original memory addresses 820 of Fig. 8.

In Figure 11-Figure 14, some embodiments of present inventive concept are shown.But those skilled in the art will recognize that It arrives, by the sequence of change block, omission block or by including attached not shown in the figure piece, the other embodiments of present inventive concept It is possible.All these variations of flow chart are considered as the embodiment of present inventive concept, regardless of whether being expressly recited.

The embodiment of present inventive concept provides several technical advantages on the prior art.Firstly, passing through removal Fig. 1's The requirement of the hardware in equipment 120 is stored to support VM to be isolated and use the FPGA 315 of Fig. 3, theoretically any storage equipment is all In the system that can be used for needing the function of SR-IOV type, because the FPGA 315 of Fig. 3 can force VM to be isolated.Second, by It can be programmed during installation in the FPGA 315 of Fig. 3, so can be built during installation by the certain desired function that system provides It is vertical, rather than (this may not provide best solution for all installations) is fixed in the manufacture point of storage equipment 120.The The FPGA 315 of three, Fig. 3 can provide the more VF of storage equipment 120 than Fig. 1, make it possible to greater number of VM System in use Fig. 1 storage equipment 120.4th, although VM isolation is provided by the FPGA 315 of Fig. 3, I/O is asked Ask, each VM still can storage equipment 120 to Fig. 1 carry out " bare machine " access.5th, doorbell storage address can be again Different O/S locked memory pages are mapped to, VM isolation is further enhanced.And the 6th, because the context of I/O request can chase after It traces back to special I/O queue, IOQ, even if the storage equipment 120 of Fig. 1 still can support VM after removing in the I/O queue, IOQ Qos requirement, so as to avoid mixer effect.

It is suitable to the one or more for some aspects that present inventive concept wherein can be implemented that following discussion is intended to provide Machine brief, general description.One or more machines can be at least partly by coming from conventional input device (such as key Disk, mouse etc.) input and the instruction by being received from another machine, with virtual reality (Virtual Reality, VR) interaction, biofeedback of environment or other input signals control.As it is used herein, term " machine " is intended to extensively The system that the machines of individual machine, virtual machine or communicative couplings, virtual machine or the equipment operated together are covered in ground.Example machine Including calculating equipment, such as personal computer, work station, server, portable computer, handheld device, phone, tablet computer Deng and transporting equipment, such as private or public traffic, for example, automobile, train, taxi etc..

One or more machines may include embedded controller, such as programmable or non-programmable logical device or battle array Column, specific integrated circuit (Application Specific Integrated Circuit, ASIC), embedded computer, intelligence Can block etc..One or more machines can use one or more connections of one or more remote machines, such as pass through net Network interface, modem or other communicative couplings.Machine can be interconnected by physical and or logical network, such as intranet, Internet, local area network, wide area network etc..It will be understood by those skilled in the art that network communication can use it is various wiredly and/or wirelessly Short distance or remote carrier and agreement, including radio frequency (Radio Frequency, RF), satellite, microwave, Electrical and Electronic engineer Association (Institute of Electrical and Electronics Engineer, IEEE) 802.11,Light , infrared, cable, laser etc..

The embodiment of present inventive concept can be described by reference to or in conjunction with associated data, associated data packet Include function, process, data structure, application program etc., when associated data are accessed by the machine so that machine performing tasks or Define abstract data type or low level hardware context.Associated data can store such as volatibility and/or it is non-easily In the property lost memory (for example, RAM, ROM etc.) or other storage equipment and its associated storage medium (including hard drive Device, floppy disk, optical storage, tape, flash memory, memory stick, digital video disc, biological memory devices etc.) in.Associated number According to can be in the form of grouping, serial data, parallel data, transmitting signal etc. in the transmission including physical and or logical network Environmentally transmit.And it can be used with compression or encryption format.Associated data can use in distributed environment, and And locally and/or remotely it is being stored for machine access.

The embodiment of present inventive concept may include include the instruction that can be performed by one or more processors it is tangible, The machine readable media of non-transitory, the instruction include the instruction for executing the element of present inventive concept as described herein.

The various operations of the above method can be executed by being able to carry out any suitable device of these operations, such as Various (multiple) hardware and or software components, circuit and/or (multiple) module.The software may include for implementing logic function The ordered list of the executable instruction of energy, and can be embodied in any " processor readable medium ", for instruction execution system System, device or equipment (such as single or multiple core processor or the system comprising processor) are using or with instruction execution system, dress It sets or equipment is used in combination.

The block or step of the method or algorithm and function that describe in conjunction with embodiment disclosed herein can be embodied directly in firmly In part, by the software module of processor execution or in the combination of the two.If implemented in software, then these functions can be with It is stored on tangible, non-transitory computer-readable medium as one or more instruction or code or transmits on it. Software module may reside within random access memory (Random Access Memory, RAM), flash memory, read-only memory (ROM), electrically programmable ROM (Electrically Programmable ROM, EPROM), electrically erasable ROM (Electrically Erasable Programmable ROM, EEPROM), register, hard disk, removable disk, CD ROM or In the storage medium of any other form known in the art.

The principle of present inventive concept has been described and illustrated by reference to the embodiment shown, it should be appreciated that the reality shown Applying example can modify in arrangement and details in the case where not departing from these principles, and can be with any desired side Formula combination.Also, although the discussion of front concentrates in special embodiment, but it is also contemplated that other configurations.Particularly, Even if herein using the expression ways such as " embodiment conceived according to the present invention ", these phrases also imply that referring generally to Embodiment possibility, and do not mean that and present inventive concept is limited to special embodiment configuration.As it is used herein, this A little terms can be with reference to the identical or different embodiment for being combined into other embodiments.

Foregoing illustrative embodiment is not necessarily to be construed as limiting its inventive concept.Although it have been described that some embodiments, But the person skilled in the art will easily understand, can in the case where the novel teachings and advantage that do not depart from the disclosure substantially To carry out many modifications to these embodiments.Therefore, all such modifications are intended to be included within sheet defined in claims In the range of inventive concept.

The embodiment of present inventive concept can extend to following notice, but not limited to this:

The embodiment for stating 1. present inventive concepts includes a kind of storage equipment, comprising:

Storage device for data；And

At least one input/output (I/O) queue, for asking at least one virtual machine (VM) on host equipment It asks,

It wherein stores equipment and supports I/O queue, IOQ creation order, to request to distribute at least one for the VM at least one VM The I/O queue, IOQ of I/O queue, IOQ, the I/O queue, IOQ creation order include will logical block address (LBA) associated with I/O queue, IOQ model The LBA range attribute enclosed, and

Wherein the range of LBA is mapped to the range of the physical block address (PBA) in storage device by storage equipment.

The embodiment for stating 2. present inventive concepts includes the storage equipment according to statement 1, in which:

Storage equipment includes solid state drive (SSD) storage equipment；And

SSD storage equipment uses quick (NVMe) interface of the nonvolatile memory of host equipment.

The embodiment for stating 3. present inventive concepts includes according to the storage equipment of statement 2, and wherein I/O queue, IOQ includes submitting team Column and completion queue.

The embodiment for stating 4. present inventive concepts includes according to the storage equipment of statement 2, wherein storage equipment is set from host Standby upper management program receives I/O queue, IOQ creation order.

The embodiment for stating 5. present inventive concepts includes according to the storage equipment of statement 2, and wherein LBA range attribute includes opening Beginning LBA and end LBA.

The embodiment for stating 6. present inventive concepts includes the storage equipment according to statement 2, in which:

LBA range attribute includes starting LBA；And

I/O queue, IOQ creation order further includes queue size.

The embodiment for stating 7. present inventive concepts includes according to the storage equipment of statement 2, and wherein I/O queue, IOQ creation order is wrapped Include the quality of service attribute of service quality (QoS) parameter for VM.

The embodiment for stating 8. present inventive concepts includes according to the storage equipment of statement 7, and wherein QoS attribute is from including minimum Bandwidth, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, reading byte per second are most Smallest number, it is per second read the maximum quantity of byte, the minimum number of write request per second, write request per second maximum quantity, It is extracted in the set of the minimum number of write-in byte per second and the maximum quantity of write-in byte per second.

The embodiment for stating 9. present inventive concepts includes according to the storage equipment of statement 2, and wherein I/O queue, IOQ creation order is wrapped Shared namespace attribute is included, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 10. present inventive concepts includes according to the storage equipment of statement 2, further includes doorbell distributed logic, For positioning the first doorbell of I/O queue, IOQ in the locked memory pages different from the second doorbell of the second I/O queue, IOQ.

The embodiment for stating 11. present inventive concepts includes according to the storage equipment of statement 2, further includes by multiple virtual i/os Queue is mapped to the field programmable gate array (FPGA) of I/O queue, IOQ, in which:

FPGA supports virtual i/o queue creation order, to request to distribute the first virtual i/o team of multiple virtual i/o queues Column, virtual i/o queue creation order include will logical block address (LBA) associated with the first virtual i/o queue the second model The the second LBA range attribute enclosed, the first virtual i/o queue are associated with I/O queue, IOQ.

The embodiment for stating 12. present inventive concepts includes according to the storage equipment of statement 11, and wherein FPGA includes that mapping is patrolled Volume, the I/O queue, IOQ for being mapped to the first virtual i/o queue in storage equipment, so that the slave VM in the first virtual i/o queue Received I/O request is passed to storage equipment via I/O queue, IOQ, and in I/O queue, IOQ from the storage received result of equipment VM is passed to via the first virtual i/o queue.

The embodiment for stating 13. present inventive concepts includes according to the storage equipment of statement 11, and wherein the second of FPGA is virtual I/O queue, IOQ is associated with I/O queue, IOQ.

The embodiment for stating 14. present inventive concepts includes according to the storage equipment of statement 11, and wherein FPGA is operable to adjust Order is created with the I/O queue, IOQ in storage equipment.

State 15. present inventive concepts embodiment include according to statement 11 storage equipment, wherein FPGA be operable to from Management program on host equipment receives virtual i/o queue creation order.

State 16. present inventive concepts embodiment include according to statement 15 storage equipment, wherein FPGA be operable to from The management program of VM on host equipment receives virtual i/o queue creation order.

The embodiment for stating 17. present inventive concepts includes according to the storage equipment of statement 11, wherein the second LBA range attribute Starting LBA and second including second terminates LBA.

The embodiment for stating 18. present inventive concepts includes the storage equipment according to statement 11, in which:

Second LBA range attribute includes the second beginning LBA；And

Virtual i/o queue creation order further includes second queue size.

The embodiment for stating 19. present inventive concepts includes according to the storage equipment of statement 11, and wherein virtual i/o queue creates Order includes the 2nd QoS attribute of the QoS parameter for VM.

The embodiment for stating 20. present inventive concepts includes according to the storage equipment of statement 19, wherein the 2nd QoS attribute is from packet Include the maximum of the second minimum bandwidth, the second maximum bandwidth, the minimum number of the second read requests per second, the second read requests per second Quantity, second minimum number per second for reading byte, second per second read the maximum quantity of byte, the second write request per second Minimum number, the maximum quantity of the second write request per second, the minimum number of the second write-in byte per second and the second write-in per second It is extracted in the set of the maximum quantity of byte.

The embodiment for stating 21. present inventive concepts includes according to the storage equipment of statement 11, and wherein virtual i/o queue creates Order includes the second shared namespace attribute, which specifies the second of the NameSpace of the access of the shared range to LBA Array.

The embodiment for stating 22. present inventive concepts includes according to the storage equipment of statement 2, and wherein FPGA further includes doorbell point Cloth logic, for positioning the first virtual i/o queue in the locked memory pages different from the second doorbell of the second virtual i/o queue The first virtual doorbell.

The embodiment for stating 23. present inventive concepts includes field programmable gate array (FPGA), comprising:

At least one virtual input/output (I/O) queue, at least one virtual machine (VM) on host equipment Request；And

Mapping logic, the I/O for being mapped to the virtual i/o queue of at least one virtual i/o queue in storage equipment Queue, so that the received I/O of slave VM in virtual i/o queue requests to be passed to storage equipment, and I/O via I/O queue, IOQ It is passed to VM from the storage received result of equipment via virtual i/o queue in queue,

Wherein FPGA supports virtual i/o queue creation order, to request the VM for being at least one VM to distribute at least one void The virtual i/o queue of quasi- I/O queue, IOQ, virtual i/o queue creation order includes will logical block associated with virtual i/o queue The LBA range attribute of the range of address (LBA), and

The range of LBA is mapped to the physics stored in equipment by the storage equipment that FPGA is wherein separated but connected to FPGA The range of block address (PBA).

The embodiment for stating 24. present inventive concepts includes according to the FPGA of statement 23, and wherein virtual i/o queue includes submitting Queue and completion queue.

The embodiment for stating 25. present inventive concepts includes according to the FPGA of statement 23, and wherein FPGA is from host equipment The management program of VM receives virtual i/o queue creation order.

The embodiment for stating 26. present inventive concepts includes according to the FPGA of statement 23, and wherein LBA range attribute includes starting LBA and end LBA.

The embodiment for stating 27. present inventive concepts includes the FPGA according to statement 23, in which:

LBA range attribute includes starting LBA；And

Virtual i/o queue creation order further includes queue size.

The embodiment for stating 28. present inventive concepts includes according to the FPGA of statement 23, wherein virtual i/o queue creation order Quality of service attribute including service quality (QoS) parameter for VM.

The embodiment for stating 29. present inventive concepts includes according to the FPGA of statement 28, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 30. present inventive concepts includes according to the FPGA of statement 23, wherein virtual i/o queue creation order Including sharing namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 31. present inventive concepts includes according to the FPGA of statement 23, and wherein FPGA is by multiple virtual i/o teams Column are mapped to the I/O queue, IOQ in storage equipment.

The embodiment for stating 32. present inventive concepts includes according to the FPGA of statement 31, and wherein FPGA can be operated to call and deposit The I/O queue, IOQ creation order in equipment is stored up to create I/O queue, IOQ.

The embodiment for stating 33. present inventive concepts includes according to the FPGA of statement 32, and wherein I/O queue, IOQ creation order includes Will LBA associated with I/O queue, IOQ the second range the 2nd LBA attribute.

The embodiment for stating 34. present inventive concepts includes further including doorbell distributed logic, being used for according to the FPGA of statement 23 The first virtual doorbell of virtual i/o queue is positioned in the locked memory pages different from the second doorbell of the second virtual i/o queue.

The embodiment for stating 35. present inventive concepts includes a kind of method, comprising:

It is received at storage equipment and creates order, I/O queue, IOQ creation for the I/O queue, IOQ of the first VM on host equipment Order includes at least will be with the LBA range category of the range of the associated logical block address (LBA) of I/O queue, IOQ in storage equipment Property；

I/O queue, IOQ is established on a storage device；

The range of big physical block address at least as the range of LBA (PBA) is selected on a storage device；

The range of LBA is mapped to the range of PBA；And

Return to success indicators,

Wherein therefore the 2nd VM on host equipment is denied access to the range of PBA.

The embodiment for stating 36. present inventive concepts includes the method according to statement 35, in which:

Storage equipment includes solid state drive (SSD) storage equipment；And

The embodiment for stating 37. present inventive concepts includes according to the method for statement 36, and wherein I/O queue, IOQ includes submitting queue With completion queue.

The embodiment for stating 38. present inventive concepts includes wherein the in receiving host equipment according to the method for statement 36 The I/O queue, IOQ creation order of one VM includes that I/O queue, IOQ creation order is received from the management program of the first VM on host equipment.

The embodiment for stating 39. present inventive concepts includes wherein the in receiving host equipment according to the method for statement 36 The I/O queue, IOQ creation order of one VM includes receiving I/O from the field programmable gate array (FPGA) of the first VM on host equipment Queue creation order.

The embodiment for stating 40. present inventive concepts includes according to the method for statement 39, and wherein FPGA is included in storage and sets In standby.

The embodiment for stating 41. present inventive concepts includes according to the method for statement 39, and wherein FPGA is separated with storage equipment But it is connected to storage equipment.

The embodiment for stating 42. present inventive concepts includes according to the method for statement 36, and wherein LBA range attribute includes starting LBA and end LBA.

The embodiment for stating 43. present inventive concepts includes the method according to statement 36, in which:

LBA range attribute includes starting LBA；And

I/O queue, IOQ creation order further includes queue size.

The embodiment for stating 44. present inventive concepts includes according to the method for statement 36, and wherein I/O queue, IOQ creation order includes The quality of service attribute of service quality (QoS) parameter for the first VM.

The embodiment for stating 45. present inventive concepts includes according to the method for statement 44, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 46. present inventive concepts includes according to the method for statement 36, and wherein I/O queue, IOQ creation order includes Shared namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 47. present inventive concepts includes the method according to statement 36, further includes:

Identify multiple doorbells associated with multiple I/O queue, IOQs；

Each of multiple doorbells are distributed to the memory in more than first a storage address in storage equipment Location, a memory address profile is in multiple locked memory pages more than first；

To host device requests address space；

More than second a storage address that more than first a storage address are mapped in address space, more than second storage Device Address d istribution is in multiple locked memory pages；And

The doorbell address of more than second a storage address is at least provided to the first VM.

The embodiment for stating 48. present inventive concepts includes the method according to statement 47, further includes:

Doorbell request is received to access doorbell address；

Doorbell address of cache is gone back into the address in more than first a storage address；And

The address more than first in a storage address is sent by doorbell request.

The embodiment for stating 49. present inventive concepts includes a kind of method, comprising:

Virtual i/o team is received from the management program of the first VM on host equipment at programmable gate array (FPGA) at the scene Column creation order, virtual i/o queue creation order includes at least will logical block associated with the I/O queue, IOQ in storage equipment The LBA range attribute of the range of address (LBA)；

The first virtual i/o queue is established on FPGA；

I/O queue, IOQ creation order is sent to storage equipment, to establish I/O queue, IOQ on a storage device；

From storage equipment reception result；

First virtual i/o queue is mapped to I/O queue, IOQ；

The range of LBA is associated with the first virtual i/o queue；And

Success indicators are returned to management program,

Wherein the range of LBA is mapped to the range of the physical block address (PBA) in storage equipment, and

The embodiment for stating 50. present inventive concepts includes according to the method for statement 49, wherein the first virtual i/o queue includes It submits queue and completes queue.

The embodiment for stating 51. present inventive concepts includes according to the method for statement 49, and wherein FPGA is by the first virtual i/o team Both column and the second virtual i/o queue are mapped to I/O queue, IOQ.

The embodiment for stating 52. present inventive concepts includes according to the method for statement 49, and wherein I/O queue, IOQ creation order includes The LBA range attribute of the range of LBA.

The embodiment for stating 53. present inventive concepts includes according to the method for statement 49, and wherein LBA range attribute includes starting LBA and end LBA.

The embodiment for stating 54. present inventive concepts includes the method according to statement 49, in which:

LBA range attribute includes starting LBA；And

Virtual i/o queue creation order further includes queue size.

The embodiment for stating 55. present inventive concepts includes according to the method for statement 49, wherein virtual i/o queue creation order Quality of service attribute including service quality (QoS) parameter for the first VM.

The embodiment for stating 56. present inventive concepts includes according to the method for statement 55, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 57. present inventive concepts includes according to the method for statement 49, wherein virtual i/o queue creation order Including sharing namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 58. present inventive concepts includes the method according to statement 49, further includes:

Identify multiple doorbells associated with multiple I/O queue, IOQs；

Each of multiple doorbells are distributed into the storage address in more than first a storage address in FPGA, the A memory address profile is in multiple locked memory pages more than one；

To host device requests address space；

The embodiment for stating 59. present inventive concepts includes the method according to statement 58, further includes:

Doorbell request is received to access doorbell address；

The address more than first in a storage address is sent by doorbell request.

The embodiment for stating 60. present inventive concepts includes a kind of method, comprising:

The first request is received from the virtual machine (VM) on host equipment, which goes to storage equipment；

The first request of capture prevents it from reaching storage equipment；

The second request is sent to field programmable gate array (FPGA), the second request first request of simulation；

The result of the second request is received from FPGA；And

The result of the second request is sent to VM.

The embodiment for stating 61. present inventive concepts includes the method according to statement 60, in which:

First request includes the first pci configuration space request of the first pci configuration space of access；And

Second request includes the second pci configuration space request of the second pci configuration space of access.

The embodiment for stating 62. present inventive concepts includes the method according to statement 60, in which:

First request includes the I/O queue, IOQ request to create for storage equipment creation I/O queue, IOQ；And

Second request includes the virtual i/o queue request to create for FPGA creation virtual i/o queue.

The embodiment for stating 63. present inventive concepts includes according to the method for statement 62, wherein the second request further includes will be with Logical block address (LBA) attribute of the range of the associated LBA of virtual i/o queue.

The embodiment for stating 64. present inventive concepts includes according to the method for statement 63, wherein virtual i/o queue request to create Including sharing namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 65. present inventive concepts includes according to the method for statement 62, wherein the second request further includes being used for The quality of service attribute of service quality (QoS) parameter of VM.

The embodiment for stating 66. present inventive concepts includes according to the method for statement 65, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 67. present inventive concepts includes a kind of article including non-transitory storage medium, the nonvolatile It is stored with instruction on property storage medium, when executed by a machine, so that:

I/O queue, IOQ is established on a storage device；

The range of LBA is mapped to the range of PBA；And

Return to success indicators,

The embodiment for stating 68. present inventive concepts includes the article according to statement 67, in which:

Storage equipment includes solid state drive (SSD) storage equipment；And

The embodiment for stating 69. present inventive concepts includes according to the article of statement 68, and wherein I/O queue, IOQ includes submitting queue With completion queue.

The embodiment for stating 70. present inventive concepts includes wherein the in receiving host equipment according to the article of statement 68 The I/O queue, IOQ creation order of one VM includes that I/O queue, IOQ creation order is received from the management program of the first VM on host equipment.

The embodiment for stating 71. present inventive concepts includes wherein the in receiving host equipment according to the article of statement 68 The I/O queue, IOQ creation order of one VM includes receiving I/O from the field programmable gate array (FPGA) of the first VM on host equipment Queue creation order.

The embodiment for stating 72. present inventive concepts includes according to the article of statement 71, and wherein FPGA is included in storage and sets In standby.

The embodiment for stating 73. present inventive concepts includes according to the article of statement 71, and wherein FPGA is separated with storage equipment But it is connected to storage equipment.

The embodiment for stating 74. present inventive concepts includes according to the article of statement 68, and wherein LBA range attribute includes starting LBA and end LBA.

The embodiment for stating 75. present inventive concepts includes the article according to statement 68, in which:

LBA range attribute includes starting LBA；And

I/O queue, IOQ creation order further includes queue size.

The embodiment for stating 76. present inventive concepts includes according to the article of statement 68, and wherein I/O queue, IOQ creation order includes The quality of service attribute of service quality (QoS) parameter for the first VM.

The embodiment for stating 77. present inventive concepts includes according to the article of statement 76, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 78. present inventive concepts includes according to the article of statement 68, and wherein I/O queue, IOQ creation order includes Shared namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 79. present inventive concepts includes the article according to statement 68, further includes:

Identify multiple doorbells associated with multiple I/O queue, IOQs；

To host device requests address space；

The embodiment for stating 80. present inventive concepts includes the article according to statement 79, further includes:

Doorbell request is received to access doorbell address；

The address more than first in a storage address is sent by doorbell request.

The embodiment for stating 81. present inventive concepts includes a kind of article including non-transitory storage medium, the nonvolatile It is stored with instruction on property storage medium, when executed by a machine, so that:

The first virtual i/o queue is established on FPGA；

From storage equipment reception result；

First virtual i/o queue is mapped to I/O queue, IOQ；

The range of LBA is associated with the first virtual i/o queue；And

Success indicators are returned to management program,

The embodiment for stating 82. present inventive concepts includes according to the article of statement 81, wherein the first virtual i/o queue includes It submits queue and completes queue.

The embodiment for stating 83. present inventive concepts includes according to the article of statement 81, and wherein FPGA is by the first virtual i/o team Both column and the second virtual i/o queue are mapped to I/O queue, IOQ.

The embodiment for stating 84. present inventive concepts includes according to the article of statement 81, and wherein I/O queue, IOQ creation order includes The LBA range attribute of the range of LBA.

The embodiment for stating 85. present inventive concepts includes according to the article of statement 81, and wherein LBA range attribute includes starting LBA and end LBA.

The embodiment for stating 86. present inventive concepts includes the article according to statement 81, in which:

LBA range attribute includes starting LBA；And

Virtual i/o queue creation order further includes queue size.

The embodiment for stating 87. present inventive concepts includes according to the article of statement 81, wherein virtual i/o queue creation order Quality of service attribute including service quality (QoS) parameter for the first VM.

The embodiment for stating 88. present inventive concepts includes according to the article of statement 87, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

The embodiment for stating 89. present inventive concepts includes according to the article of statement 81, wherein virtual i/o queue creation order Including sharing namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 90. present inventive concepts includes the article according to statement 81, further includes:

Identify multiple doorbells associated with multiple I/O queue, IOQs；

To host device requests address space；

The embodiment for stating 91. present inventive concepts includes the article according to statement 90, further includes:

Doorbell request is received to access doorbell address；

The address more than first in a storage address is sent by doorbell request.

The embodiment for stating 92. present inventive concepts includes a kind of article, which includes non-transitory storage medium, this is non- Instruction is stored on temporary storage medium, when executed by a machine, so that:

The first request of capture prevents it from reaching storage equipment；

The result of the second request is received from FPGA；And

The result of the second request is sent to VM.

The embodiment for stating 93. present inventive concepts includes the article according to statement 92, in which:

The embodiment for stating 94. present inventive concepts includes the article according to statement 92, in which:

The embodiment for stating 95. present inventive concepts includes according to the article of statement 94, wherein the second request further includes will be with Logical block address (LBA) attribute of the range of the associated LBA of virtual i/o queue.

The embodiment for stating 96. present inventive concepts includes according to the article of statement 95, wherein virtual i/o queue request to create Including sharing namespace attribute, the array of the NameSpace of the access of the specified shared range to LBA of the attribute.

The embodiment for stating 97. present inventive concepts includes according to the article of statement 94, wherein the second request further includes being used for The quality of service attribute of service quality (QoS) parameter of VM.

The embodiment for stating 98. present inventive concepts includes according to the article of statement 97, and wherein QoS attribute is from including most small band Width, maximum bandwidth, the minimum number of read requests per second, the maximum quantity of read requests per second, the minimum per second for reading byte Quantity, the maximum quantity, every per second for reading the maximum quantity of byte, the minimum number of write request per second, write request per second It is extracted in the set of the minimum number of second write-in byte and the maximum quantity of write-in byte per second.

Accordingly, it is considered to embodiment described herein various displacements, the detailed description and institute's enclosure material are only anticipated Scheme illustrative, and is not construed as limiting the scope of the inventive concept.Therefore, claimed as present inventive concept to be All such modifications, these modifications can be fallen into the scope and spirit of the following claims and their equivalents.

Claims

1. a kind of for dynamically distributing the storage equipment of physical storage device resource in virtualized environment, comprising:

Storage device for data；And

At least one input/output I/O queue, IOQ, for the request of at least one virtual machine VM on host equipment,

Wherein the storage equipment supports I/O queue, IOQ creation order, to request the VM distribution for being at least one VM described extremely The I/O queue, IOQ of a few I/O queue, IOQ, the I/O queue, IOQ creation order includes will logical block associated with the I/O queue, IOQ The LBA range attribute of the range of location LBA, and

Wherein the range of LBA is mapped to the physical block address PBA being used in the storage device of data by the storage equipment Range.

2. storage equipment according to claim 1, in which:

The storage equipment includes solid state drive SSD storage equipment；And

The SSD storage equipment uses the quick NVMe interface of the nonvolatile memory of host equipment.

3. storage equipment according to claim 2, wherein the storage equipment is from the management program on the host equipment Receive the I/O queue, IOQ creation order.

4. storage equipment according to claim 2, wherein the LBA range attribute includes starting LBA and end LBA.

5. storage equipment according to claim 2, wherein the I/O queue, IOQ creation order includes the clothes for the VM The quality of service attribute for quality Q oS parameter of being engaged in.

6. storage equipment according to claim 2, wherein the I/O queue, IOQ creation order includes shared NameSpace category Property, the array of the NameSpace of the access of the specified shared range to the LBA of the attribute.

7. storage equipment according to claim 2 further includes that multiple virtual i/o queues are mapped to the I/O queue, IOQ On-site programmable gate array FPGA, in which:

The FPGA supports virtual i/o queue creation order, to request to distribute the first virtual I/ of the multiple virtual i/o queue O queue, the virtual i/o queue creation order includes will logical block address LBA associated with the first virtual i/o queue The second range the second LBA range attribute, the first virtual i/o queue is associated with the I/O queue, IOQ.

8. storage equipment according to claim 2 further includes doorbell distributed logic, in the second I/O queue, IOQ The first doorbell of the I/O queue, IOQ is positioned in the different locked memory pages of two doorbells.

9. a kind of for dynamically distributing the on-site programmable gate array FPGA of physical storage device resource, packet in virtualized environment It includes:

At least one virtual input/output I/O queue, IOQ, the request at least one virtual machine VM on host equipment； And

Mapping logic, the I/O for being mapped to the virtual i/o queue of at least one virtual i/o queue in storage equipment Queue, so that the received I/O of slave VM in the virtual i/o queue requests to be passed to the storage via the I/O queue, IOQ Equipment, and being passed to from the storage received result of equipment via the virtual i/o queue in the I/O queue, IOQ is described VM,

Wherein the FPGA supports virtual i/o queue creation order, to request the VM distribution for being at least one VM described extremely The virtual i/o queue of a few virtual i/o queue, the virtual i/o queue creation order includes will be with the virtual i/o queue The LBA range attribute of the range of associated logical block address LBA, and

The range of the LBA is mapped to the storage by the storage equipment that the FPGA is wherein separated but connected to the FPGA The range of physical block address PBA in equipment.

10. FPGA according to claim 9, wherein the LBA range attribute includes starting LBA and end LBA.

11. FPGA according to claim 9, wherein virtual i/o queue creation order includes the clothes for the VM The quality of service attribute for quality Q oS parameter of being engaged in.

12. FPGA according to claim 9, wherein virtual i/o queue creation order includes shared NameSpace category Property, the array of the NameSpace of the access of the specified shared range to the LBA of the attribute.

13. FPGA according to claim 9, wherein multiple virtual i/o queues are mapped in the storage equipment by the FPGA I/O queue, IOQ.

14. FPGA according to claim 13, wherein the FPGA can be operated to call the I/O team in the storage equipment Column creation order is to create the I/O queue, IOQ.

15. FPGA according to claim 9 further includes doorbell distributed logic, in the second virtual i/o queue The first virtual doorbell of the virtual i/o queue is positioned in the different locked memory pages of two doorbells.

It for dynamically distribute physical storage device resource in virtualized environment include non-transitory storage medium 16. a kind of Article is stored with instruction on the non-transitory storage medium, when described instruction is executable by a machine, so that:

The first request is received from the virtual machine VM on host equipment, storage equipment is gone in first request；

Capturing first request prevents it from reaching the storage equipment；

The second request, the second request simulation first request are sent to on-site programmable gate array FPGA；

The result of second request is received from the FPGA；And

The result of second request is sent to the VM.

17. article according to claim 16, in which:

First request includes the I/O queue, IOQ request to create for the storage equipment creation I/O queue, IOQ；And

18. article according to claim 17, wherein second request further includes related to the virtual i/o queue The logical block address LBA attribute of the range of the LBA of connection.

19. article according to claim 18, wherein the virtual i/o queue request to create includes shared NameSpace category Property, the array of the NameSpace of the access of the specified shared range to the LBA of the attribute.

20. article according to claim 17, wherein second request further includes the service quality QoS for the VM The quality of service attribute of parameter.