CN110266293A - A kind of low delay synchronizing device and method - Google Patents
A kind of low delay synchronizing device and method Download PDFInfo
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- CN110266293A CN110266293A CN201910514768.3A CN201910514768A CN110266293A CN 110266293 A CN110266293 A CN 110266293A CN 201910514768 A CN201910514768 A CN 201910514768A CN 110266293 A CN110266293 A CN 110266293A
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- delay
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- delay unit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
Abstract
A kind of low delay synchronizing device and method, device include: time delay chain (1), are sequentially connected and are formed by one or more delay unit, input signal is successively delayed through delay unit；Flip-flop element (2), is made of one or more trigger, and trigger and delay unit correspond, and when for the clock in sampled signal along arrival, latches to the signal of each delay unit output end；Coding unit (3), for the signal latched in each trigger to be converted to coded data；It selects output unit (4), for selecting corresponding delay unit according to coded data, and exports the signal of the delay unit output end.By carrying out the delay of one kind or more to input signal, and according to the signal after input signal and sampled signal selection output wherein optimal delay, so that output signal keeps stablizing in sampled signal sampling period.
Description
Technical field
This disclosure relates to automation control area, and in particular, to a kind of low delay synchronizing device and method.
Background technique
Automation control area, when needing quickly to transmit signal between the digital display circuit of multiple homologous clock controls,
The signal synchronization mechanism of low delay need to be met, to avoid sample error is generated, currently used synchronization scheme there are following three kinds:
(1) by manually adjusting the transmission cable length between transmitting terminal and receiving end, when so that signal reaching receiving end, receiving end letter
Number with sampling clock establish holding relationship, i.e., sampling clock reach when, the data sampled before sampling clock edge and it
It keeps stablizing in a period of time afterwards, this method simple, intuitive, but when receiving end number or cable number reach tens even
When up to a hundred a, manually adjust more and more difficult；(2) increasing with Lu Shizhong, transmitting terminal issues clock signal while sending data,
This method is simple, but cable number becomes original twice, and enters behind receiving end with road clock and still need to and receiving end sheet
Ground clock synchronizes processing, to establish holding relationship；(3) coding protocol is used, clock is encoded to transmitting terminal and receiving end
Between data in, which solve manually adjusting and the problem of cable doubles, but increase agreement and design complexity got higher,
And protocol-decoding process increases delay, decoded data still need to synchronize processing with local clock.
Summary of the invention
(1) technical problems to be solved
The disclosure in view of the above problems, provides a kind of low delay synchronizing device and method, by carrying out to input signal
A kind of or more delay, setting maximum delay are greater than the sampling period of sampled signal, and select after exporting wherein optimal delay
Signal so that output signal sampling period keep stablize, at least to solve the above technical problem.
(2) technical solution
The disclosure provides a kind of low delay synchronizing device, comprising: time delay chain is successively connected by one or more delay unit
Composition is connect, input signal is successively delayed through the delay unit；Flip-flop element, by one or more trigger group
Corresponded at, the trigger and the delay unit, for the clock in sampled signal along arrive when, described prolong to each
The signal of Shi Danyuan output end is latched；Coding unit, for the signal latched in each trigger to be converted to volume
Code data；Output unit is selected, for selecting the corresponding delay unit according to the coded data, and exports the delay list
The signal of first output end.
Optionally, the selection output unit includes selecting unit and Mux unit, and the selecting unit is used for according to
Coded data selects the corresponding delay unit, and generates a selection result, and the Mux unit is exported according to the selection result
The signal of the delay unit output end.
Optionally, the quantity of the delay unit meets preset condition so that in the time delay chain delay unit delay
The sum of be greater than the sampled signal period.
Optionally, the delay of each delay unit is Δ t, and the period of the sampled signal is T, the preset condition
For greater than T/ Δ t.
Optionally, the data input pin of each trigger is connected to the input terminal of its corresponding delay unit, described
Delay unit input terminal to corresponding trigger data input pin delay it is equal with the delay of the delay unit.
Optionally, the coded data is thermometer code, and the coding unit will be described according to the delay of the delay unit
Thermometer code is converted to time value.
Optionally, the signal of the delay unit output end of the selection output unit selection is adopted in the sampled signal
It is remained unchanged when sample.
Optionally, the clock end of each trigger is connected to the sampled signal.
The disclosure additionally provides a kind of low delay synchronous method, comprising: S1, according to one or more default delay to defeated
Enter signal to be delayed, obtains each default corresponding time delayed signal that is delayed；S2 arrives on the clock edge of sampled signal
When, each time delayed signal is latched；Each time delayed signal is converted to coded data by S3；S4, according to described
The time delayed signal output of coded data selection one, wherein the time delayed signal is kept not when the sampled signal is sampled
Become.
Optionally, one or more default delay forms arithmetic progression, and maximum preset delay is greater than described adopt
The period of sample signal.
(3) beneficial effect
The disclosure provide low delay synchronizing device and method have good scalability, be delayed it is low, precision is high, avoid across
Clock domain is synchronous, and can dynamically adjust output signal, additionally can be convenient and rapidly carries out large-scale integrated, significantly
Improve synchronous flexibility.
Detailed description of the invention
Fig. 1 diagrammatically illustrates the block diagram of the low delay homologous signal synchronization system of embodiment of the present disclosure offer.
Fig. 2 diagrammatically illustrates the structural schematic diagram of the low delay synchronizing device of embodiment of the present disclosure offer.
Fig. 3 diagrammatically illustrates the working sequence schematic diagram in the low delay synchronizing device of embodiment of the present disclosure offer.
Fig. 4 diagrammatically illustrates the flow chart of the low delay synchronous method of embodiment of the present disclosure offer.
Specific embodiment
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
The disclosure is further described in attached drawing.
First embodiment of the present disclosure provides a kind of low delay synchronizing device, referring to Fig.2, in conjunction with Fig. 1 and Fig. 3, to Fig. 2
The structure and working principle of shown device is described in detail.
Low delay synchronizing device is located in the purpose end equipment in Fig. 1, in the system shown in figure 1, a source equipment
With the work of multiple purpose end equipments under homologous clock, source equipment is connected with purpose end equipment by cable.Source equipment hair
Homologous pulse signal is to purpose end equipment out, due to the changeability of length of cable, even if source equipment and purpose end equipment are
It is homologous, but when pulse signal reaches purpose end equipment by cable, the foundation of purpose end equipment sampling clock may be unsatisfactory for
With the requirement of retention time.Therefore, multiple purpose end equipment is when receiving the signal, is prolonged by low in purpose end equipment
When synchronizing device carry out sampling and synchronization process so that treated pulse signal is in sampling clock within neighbouring a period of time
It remains unchanged.
Low delay synchronizing device includes time delay chain 1, flip-flop element 2, coding unit 3 and selection output unit 4, and is prolonged
When chain 1, flip-flop element 2, coding unit 3 and selection output unit 4 be integrated in the field programmable gate array (Field- of monolithic
Programmable Gate Array, FPGA) in chip.
Time delay chain 1 is the signal transmission path for being sequentially connected by one or more delay unit and being formed, generally by more
A delay unit forms, each delay unit on path can draw tap signal, is usually used in split-second precision
Measurement.Input signal is by first delay unit D1Input terminal enter time delay chain, and carried out at delay in each delay unit
Next delay unit is successively transmitted to after reason, until the last one delay unit DnDelay process finishes.It is delayed in time delay chain 1
The quantity n of unit should meet preset condition, so that the maximum delay (the sum of the delays of i.e. all delay units) of time delay chain 1 is greater than
The sampling period of sampled signal, so that the delay of time delay chain 1 can move freely in a sampling period, wherein sampled signal
It is provided by the clock in Fig. 1.The maximum delay that time delay chain 1 is able to achieve is equal to the sum of the delay of this n delay unit, practical application
In, identical delay Δ t often is set by the delay of each delay unit, the sampling period of sampled signal is set as T, then be delayed list
The quantity n > T/ Δ t of member.In time delay chain 1, j-th of delay unit DjDelay between the tap signal and input signal of extraction
For j* Δ t, wherein 1≤j≤n.
Flip-flop element 2 is made of one or more trigger, and trigger and delay unit correspond, i.e. trigger
Quantity be also n.The data input pin of each trigger is connected to the input terminal of its corresponding delay unit, each triggering
The clock end of device is connected to sampled signal, and its enable end is connected to same enable signal enable, and enable signal has
" 0 ", " 1 " two states, when enable signal is " 1 ", the enabled switch of trigger is opened, and trigger works normally.Work as sampling
When the clock of signal arrives along (specially rising edge), if enabled switch is in the open state, each trigger is corresponding to its
The tap signal of delay unit output end latched, i.e., simultaneously latch clock along arriving moment input signal in time delay chain
Transmitting situation.In addition, the delay of data input pin and the prolonging of the delay unit of the delay unit input terminal to corresponding trigger
When be consistent, so as to sampled signal clock along arrive when can accurately by input signal in time delay chain transmittance process
It preserves.
Coding unit 3 is used to the signal latched in each trigger being converted to coded data, which is temperature
Code is spent, which is converted to corresponding binary code by coding unit 3, according to the delay Δ t of delay unit by binary code
Be converted to corresponding time value.In addition, coding unit 3 can also calculate the pass of the time between input signal and sampled signal
System, for example, calculating time difference of the input signal apart from nearest sampled signal rising edge.
It selects output unit 4 to select corresponding delay unit according to coded data, and exports the delay unit output end
Signal, the i.e. tap signal of the delay unit.Wherein, selection output unit 4 includes selecting unit and data selector
(multiplexer, Mux) unit, selecting unit time relationship according to obtained in coding unit 3 and coded data (i.e. time
Value) select an optimal tap signal wherein, which remains unchanged when sampled signal is sampled, and specially exists
Sampled signal sampling clock remains unchanged within neighbouring a period of time, and (i.e. the tap signal is corresponding for one selection result of generation
Delay unit) be sent to Mux unit, Mux unit exports the signal of the delay unit output end according to the selection result.
In the present embodiment, by taking delay unit quantity n=7 as an example, the working sequence of each unit in the present apparatus is illustrated, is joined
Read Fig. 3.In Fig. 3, the sampling period of sampled signal is 10ns, and the delay Δ t of each delay unit is 1.5ns, delay unit
Therefore 7 delay units are arranged, input signal is from nearest sampling clock rising edge in quantity n > 10/1.5 in time delay chain 1
For 9.2ns, flip-flop element 2 latches delay unit tap signal in sampled signal rising edge, and coding unit 3 will latch
Signal is converted into thermometer code, which is 0111111, and being converted to time value is 6*1.5ns=9ns.Refering to Fig. 3, delay is single
First D1-D6The tap signal of output (before arriving comprising rising edge and can rise within a period of time of sampled signal rising edge
After arriving) it remains unchanged, it is contemplated that the accuracy of sampling, this answers the duration for a period of time, and the longer the better, therefore,
Compare D1-D6The tap signal of output, D3The tap signal of output is able to maintain longer before rising edge arrival and after arriving
The stabilization of time, therefore the number of the optimal corresponding delay unit of tap signal is 3, D3The signal of output end is chosen as finally
Signal output.
Second embodiment of the present disclosure provides a kind of low delay synchronous method, and refering to Fig. 4, this method includes following behaviour
Make:
S1 is delayed to input signal according to one or more default delay, and it is corresponding to obtain each default delay
Time delayed signal.
The default delay of said one or more forms one group of arithmetic progression, i.e., the time difference between adjacent default delay is permanent
It is set to Δ t, and maximum preset delay is greater than the sampling period T of sampled signal, so that the delay to input signal can be at one
It is moved freely in sampling period.
It is assumed that the number of default delay is n, the default delay of said one or more is respectively Δ t, 2 Δ t, 3 Δs
t、……nΔt。
S2 latches each time delayed signal when the clock of sampled signal is along arrival.
When the rising edge of sampled signal arrives, each time delayed signal in operation S1 is latched, so as to accurately
Input signal after progress different delayed time is preserved.
Each time delayed signal is converted to coded data by S3.
Obtained time delayed signal will be latched and be converted to thermometer code, and the thermometer code is converted into corresponding binary code, root
Binary code is converted into corresponding time value according to delay Δ t.In addition, also need to calculate between input signal and sampled signal when
Between relationship, for example, calculating time difference of the input signal apart from nearest sampled signal rising edge.
S4 selects time delayed signal output according to coded data, wherein the time delayed signal is when sampled signal is sampled
It remains unchanged.
Optimal time delayed signal is selected to export according to time value obtained in operation S3 and time relationship, it is however generally that,
There may be multiple time delayed signals can remain unchanged when sampled signal is sampled in above-mentioned n time delayed signal, that is, is adopting
In a period of time of sample signal rising edge (before arriving comprising rising edge and after rising edge arrival), it is contemplated that sampling
Accuracy, this answers the duration for a period of time, and the longer the better, and therefore, optimal time delayed signal should arrive in sampled signal rising edge
It is able to maintain the time delayed signal that longest stablizes the time before and after arriving.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail it is bright, it is all it should be understood that be not limited to the disclosure the foregoing is merely the specific embodiment of the disclosure
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of low delay synchronizing device, comprising:
Time delay chain (1), is sequentially connected by one or more delay unit and is formed, input signal successively through the delay unit into
Line delay；
Flip-flop element (2), is made of one or more trigger, and the trigger and the delay unit correspond,
When for the clock in sampled signal along arrival, the signal of each delay unit output end is latched；
Coding unit (3), for the signal latched in each trigger to be converted to coded data；
It selects output unit (4), for selecting the corresponding delay unit according to the coded data, and exports the delay list
The signal of first output end.
2. low delay synchronizing device according to claim 1, wherein the selection output unit (4) includes selecting unit
With Mux unit, the selecting unit is used to select the corresponding delay unit according to the coded data, and generates a selection
As a result, the Mux unit exports the signal of the delay unit output end according to the selection result.
3. low delay synchronizing device according to claim 1, wherein the quantity of the delay unit meets preset condition,
So that the sum of delay of delay unit is greater than the period of the sampled signal in the time delay chain (1).
4. low delay synchronizing device according to claim 3, wherein the delay of each delay unit is △ t, described
The period of sampled signal is T, and the preset condition is greater than T/ △ t.
5. low delay synchronizing device according to claim 1, wherein the data input pin of each trigger is connected to
The input terminal of its corresponding delay unit, the delay of data input pin of the delay unit input terminal to corresponding trigger with should
The delay of delay unit is equal.
6. low delay synchronizing device according to claim 1, wherein the coded data is thermometer code, and the coding is single
The thermometer code is converted to time value according to the delay of the delay unit by first (3).
7. low delay synchronizing device according to claim 1, wherein the delay list of selection output unit (4) selection
The signal of first output end is remained unchanged when the sampled signal is sampled.
8. low delay synchronizing device according to claim 1, wherein the clock end of each trigger is connected to institute
State sampled signal.
9. a kind of low delay synchronous method, comprising:
S1 is delayed to input signal according to one or more default delay, and it is corresponding to obtain each default delay
Time delayed signal；
S2 latches each time delayed signal when the clock of sampled signal is along arrival；
Each time delayed signal is converted to coded data by S3；
S4 is exported according to the time delayed signal of coded data selection one, wherein the time delayed signal the sampled signal into
It is remained unchanged when row sampling.
10. low delay synchronous method according to claim 9, wherein one or more default delay formation etc.
Difference series, and maximum preset delay is greater than the period of the sampled signal.
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Cited By (1)
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| CN111262562A (en) * | 2020-03-02 | 2020-06-09 | 上海交通大学 | Metastable state detection circuit |
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Application publication date: 20190920 |