CN110265515B - Light emitting diode chip and manufacturing method thereof - Google Patents

Light emitting diode chip and manufacturing method thereof Download PDF

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Publication number
CN110265515B
CN110265515B CN201910535164.7A CN201910535164A CN110265515B CN 110265515 B CN110265515 B CN 110265515B CN 201910535164 A CN201910535164 A CN 201910535164A CN 110265515 B CN110265515 B CN 110265515B
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layer
electrode
forming
conductive lead
semiconductor layer
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CN110265515A (en
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吴永军
刘亚柱
唐军
齐胜利
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Ningbo anxinmei Semiconductor Co.,Ltd.
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Hefei Irico Epilight Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention provides a light emitting diode chip and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate; forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer; forming a patterned current blocking layer on the epitaxial structure; forming a current spreading layer on the epitaxial structure, removing part of the current spreading layer and the epitaxial structure, and forming a groove, wherein part of the second semiconductor layer is exposed out of the groove, and the current spreading layer covers the patterned current blocking layer; forming a first electrode on the current spreading layer and a second electrode on the exposed second semiconductor layer; forming a first conductive lead on the first electrode and a second conductive lead on the second electrode, wherein the second conductive lead is also positioned on a cutting path of the light-emitting diode chip; and forming passivation layers on two sides of the first electrode and the second electrode. The manufacturing method has reasonable design and lower cost.

Description

Light emitting diode chip and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a light emitting diode chip and a manufacturing method thereof.
Background
Light Emitting Diodes (LEDs) are undoubtedly the most important light source technology because of their advantages of high color purity, fast response speed, small size, good reliability, long lifetime, environmental protection, etc., and with the development of technology, the requirements for high pixel screens are more prominent, and higher requirements are put forward on chip size. According to the 2018 technological industry development trend published by trends, the micro light emitting diode (Mini LED) technology can be matched with a flexible substrate to achieve a high-curved backlight mode, and the micro LED backlight module is organically applied to various applications such as mobile phones, televisions, vehicle-mounted panels and the like.
Under a specific current, the luminous efficiency of the LED chip is influenced by two factors of brightness and working voltage, the two factors are a pair of spear bodies, the length or the width of the conducting lead is increased to facilitate conduction, namely the working voltage is reduced, but the corresponding light blocking area is increased, namely the brightness is reduced; otherwise, the voltage and the brightness are both increased, and it is difficult to greatly improve the light emitting efficiency. The conductive leads in the prior art typically require sacrificing the light-emitting area of the chip, thus resulting in the light-emitting efficiency of the chip.
Disclosure of Invention
In view of the above-mentioned defects of the prior art, the present invention provides a light emitting diode chip and a manufacturing method thereof, by which a light blocking area of the chip can be reduced and a light emitting efficiency of the chip can be improved.
In order to achieve the above and other objects, the present invention provides a method for manufacturing a light emitting diode chip, including:
providing a substrate;
forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer;
forming a patterned current blocking layer on the epitaxial structure;
forming a current spreading layer on the epitaxial structure, removing part of the current spreading layer and the epitaxial structure, and forming a groove, wherein part of the second semiconductor layer is exposed out of the groove, and the current spreading layer covers the patterned current blocking layer;
forming a first electrode on the current spreading layer and a second electrode on the exposed second semiconductor layer;
forming a first conductive lead on the first electrode and a second conductive lead on the second electrode, wherein the second conductive lead is also positioned on a cutting path of the light-emitting diode chip;
and forming passivation layers on two sides of the first electrode and the second electrode.
In one embodiment, the patterned current blocking layer has a thickness of 80-500 nm.
In one embodiment, the thickness of the current spreading layer is 20-200nm, and the depth of the groove is 1-2 μm.
In one embodiment, the forming a first conductive lead on the first electrode and forming a second conductive lead on the second electrode, the second conductive lead being located on the scribe line of the led chip includes:
forming a patterned photoresist layer on the current spreading layer and the second semiconductor layer;
forming a conductive layer on the patterned photoresist layer;
and removing part of the conductive layer, and reserving the conductive layer on the side wall of the patterned photoresist layer to form a first conductive lead and a second conductive lead.
In one embodiment, the first conductive lead is perpendicular to the first electrode and the second conductive lead is perpendicular to the second electrode.
In one implementation, the first and second conductive leads have a width of 1-2 μm.
In one embodiment, the passivation layer is on the second semiconductor layer and the current spreading layer.
The invention also provides a light emitting diode chip, comprising:
a substrate;
the epitaxial structure is positioned on the substrate and comprises a first semiconductor layer and a second semiconductor layer;
a current blocking layer located on the epitaxial structure;
the current extension layer is positioned on the epitaxial structure and covers the current barrier layer;
a recess on the epitaxial structure, the recess exposing a portion of the second semiconductor layer;
a first electrode on the current spreading layer and a second electrode on the second semiconductor layer in the recess;
the first conductive lead is positioned on the first electrode, and the second conductive lead is positioned on the second electrode and positioned on a cutting path of the light-emitting diode chip;
and the passivation layer is positioned on the current expansion layer and the second semiconductor layer.
In one embodiment, the first conductive lead is perpendicular to the first electrode and the second conductive lead is perpendicular to the second electrode.
The invention provides a light-emitting diode chip and a manufacturing method thereof, the manufacturing method optimizes the chip structure design again, and designs a second conducting lead on a cutting path of the light-emitting diode chip, so that the second conducting lead does not occupy the light-emitting area of the light-emitting diode chip independently, the light-emitting distribution is optimized by increasing the number of the first conducting leads, the conductivity is increased, the shielding area of the chip is reduced, and the light-emitting efficiency of the light-emitting diode chip is effectively improved. The manufacturing method adopts a brand new process and can manufacture the conductive lead with a larger height-width ratio on a low-precision exposure system.
Drawings
FIG. 1: the method for manufacturing a light emitting diode chip according to the present embodiment is a flowchart.
FIG. 2A: the cross-sectional views of steps S1-S2.
FIG. 2B: top views of steps S1-S2.
FIG. 3A: a cross-sectional view of step S3.
FIG. 3B: top view of step S3.
FIG. 4A: a cross-sectional view of step S4.
FIG. 4B: top view of step S4.
FIG. 5A: a cross-sectional view of step S5.
FIG. 5B: top view of step S5.
FIGS. 6A-6B: a cross-sectional view of step S6.
FIG. 6C: top view of step S6.
FIG. 7A: a cross-sectional view of step S7.
FIG. 7B: top view of step S7.
FIG. 8: the light emitting diode chip of the present embodiment is shown in a cross-sectional view.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be complicated.
Referring to fig. 1, the present embodiment provides a method for manufacturing a light emitting diode chip, including:
s1: providing a substrate;
s2: forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer;
s3: forming a patterned current blocking layer on the epitaxial structure;
s4: forming a current extension layer on the epitaxial structure, removing part of the current extension layer and the epitaxial structure, and forming a groove;
s5: forming a first electrode on the current spreading layer, and forming a second electrode on the exposed second semiconductor layer
S6: forming a first conductive lead on the first electrode and a second conductive lead on the second electrode, wherein the second conductive lead is positioned on a cutting path of the light-emitting diode chip;
s7: and forming passivation layers on two sides of the first electrode and the second electrode.
Referring to fig. 2A-2B, in steps S1-S2, the substrate 110 includes a sapphire patterned substrate, a sapphire substrate, a silicon carbide substrate, and a composite substrate, and in the present embodiment, the substrate 110 is an alumina substrate. The epitaxial structure 120 includes a first semiconductor layer 122, a second semiconductor layer 121, the second semiconductor layer 121 is located on the substrate 110, the first semiconductor layer 122 is located on the second semiconductor layer 121, in this embodiment, for example, a metal organic compound chemical vapor deposition technique is adopted to sequentially deposit the second semiconductor layer 121 and the first semiconductor layer 122 on the substrate 110, the first semiconductor layer 122 is, for example, a P-type semiconductor layer, and the second semiconductor layer 121 is, for example, an N-type semiconductor layer. In the steps S1-S2, the method may further include forming a buffer layer on the substrate 110, and then growing the epitaxial structure 120 on the buffer layer, wherein the buffer layer formed between the substrate 110 and the second semiconductor layer 121 facilitates the growth of the epitaxial structure 120, and improves the quality of the flip-chip light emitting diode.
Referring to fig. 3A-3B, in step S3, a current blocking layer 130 is formed on the epitaxial structure 120 by using a plasma enhanced chemical vapor deposition method, a sputtering process or an evaporation process, a patterned photoresist layer is formed on the current blocking layer 130, the current blocking layer 130 is etched and cleaned, the patterned current blocking layer 130 is obtained, and then the photoresist layer is removed and cleaned. In the present embodiment, the material of the current blocking layer 130 includes at least one of silicon oxide, silicon nitride, aluminum oxide, and magnesium fluoride, and in the present embodiment, the material of the current blocking layer 3 is, for example, silicon oxide, which has a simple manufacturing process and a low cost; the thickness of the current blocking layer 130 is between 80-500nm, for example 300 nm. It should be noted that, the current blocking layer 130 is located between the first semiconductor layer 122 and the current spreading layer 140, so that a current can be prevented from directly entering the first semiconductor layer 122, and the light emitting brightness of the semiconductor chip is improved, and the size of the current blocking layer 130 is smaller than that of the first semiconductor layer 122.
Referring to fig. 4A-4B, in step S4, a current spreading layer 140 is first formed on the current blocking layer 130 by using electron beam evaporation and/or magnetron sputtering, the thickness of the current spreading layer 140 is 20-200nm, for example, 100nm, then a patterned photoresist layer is formed on the current spreading layer 140, then a portion of the current spreading layer 140 is removed by an inductively coupled plasma etching process to form a patterned current spreading layer 140, and a portion of the epitaxial structure 120 is removed to form at least one groove 150 from the current spreading layer 140 to the second semiconductor layer 121, the depth of the groove 150 is 1-2 μm, for example, 1.5 μm, and then cleaning is performed. In this embodiment, the material of the current spreading layer 140 includes at least one of Indium Tin Oxide (ITO), fluorine-doped tin oxide, and graphene; optionally, the material of the current spreading layer 140 is Indium Tin Oxide (ITO), which is widely used and low in cost.
Referring to fig. 5A-5B, in step S5, a patterned photoresist layer is first formed on the current spreading layer 140 and the groove 150, the patterned photoresist layer includes a first opening and a second opening, the first opening is located on the current spreading layer 140, the second opening is located in the groove 150, the first electrode 161 is grown in the first opening, the second electrode 162 is grown in the second opening, then electrodes are deposited on the patterned photoresist layer, the first opening and the second opening by evaporation and/or sputtering techniques, then the metal on the patterned photoresist layer is stripped and the patterned photoresist layer on the chip surface is removed, so as to obtain the first electrode 161 and the second electrode 162, and the materials of the first electrode 161 and the second electrode 162 include gold, aluminum, chromium, nickel, titanium, and chromium, At least one of platinum; the first electrode 161 is electrically connected to the current spreading layer 140, and the second electrode 162 is electrically connected to the second semiconductor layer 121.
Referring to fig. 6A-6C, in step S6, a patterned photoresist layer PR is formed on the current spreading layer 140 and the exposed second semiconductor layer 121, the patterned photoresist layer PR includes a third opening on the first electrode 161, the patterned photoresist layer PR also covers a portion of the second electrode 162, a conductive layer is deposited on the patterned photoresist layer PR by evaporation and/or sputtering, the conductive layer covers a top surface and sidewalls of the patterned photoresist layer PR, the conductive layer is also located in the third opening on the first electrode 161, the conductive layer on the top surface of the patterned photoresist layer PR is removed by dry etching (e.g., an inductively coupled plasma etching process), and the conductive layer on the sidewalls of the patterned photoresist layer PR is remained after removing the conductive layer in the third opening, the first conductive wiring 171 and the second conductive wiring 172 are formed, and then the patterned photoresist layer PR is removed and cleaned. In this embodiment, the first conductive lead 171 is located on the first electrode 161, the first conductive lead 171 is perpendicular to the first electrode 161, the second conductive lead 172 is located on the second electrode 162, and the second conductive lead 172 is perpendicular to the second electrode 162, in this embodiment, the widths of the first conductive lead 171 and the second conductive lead 172 are 1-2 μm, for example, 1.5 μm. In this embodiment, the second conductive lead 172 is further located on a cutting street (not shown) of the led chip, and the cutting street is located outside the led chip, so that the second conductive lead 172 does not exclusively use the light emitting area of the led chip. In this embodiment, the led chip includes two first conductive leads 171, the led chip includes one second conductive lead 172, the first conductive lead 171 is, for example, a P-electrode lead, and the second conductive lead 172 is, for example, an N-electrode lead. In this embodiment, when the conductive layer is deposited on the patterned photoresist layer PR, the width of the conductive layer on the sidewall of the patterned photoresist layer PR can be controlled by adjusting the operating conditions of the apparatus, so that the width of the conductive lead can be controlled, the aspect ratio of the conductive lead is effectively improved, and the area of the conductive lead for shielding the chip to emit light is reduced. In other embodiments, the first conductive lead 171 is angled at 85 ° -115 °, such as 90 ° or 100 °, with respect to the first electrode 161, and the second conductive lead 172 is angled at 85 ° -115 °, such as 95 ° or 105 °, with respect to the second electrode 162.
Referring to fig. 7A-7B, in step S7, a passivation layer 180 is first formed on the current spreading layer 140 and the second semiconductor layer 121, a patterned photoresist layer is then formed on the passivation layer 180, the passivation layer 180 is then etched according to the patterned photoresist layer to form a patterned passivation layer, and then the patterned photoresist layer is removed and cleaned. In this embodiment, the passivation layer 180 is also located at two ends of the first electrode 161 and the second electrode 162. In this embodiment, the passivation layer 180 is made of silicon oxide or aluminum oxide, and protects the semiconductor chip, thereby avoiding problems such as reverse leakage and improving reliability of the chip, optionally, the passivation layer 180 is made of silicon oxide, which facilitates etching of the opening, and in this embodiment, the passivation layer 180 is etched by buffering silicon oxide etching liquid or dry etching.
Referring to fig. 8, the present embodiment further provides a light emitting diode chip 100, including a substrate 110, a second semiconductor layer 121 disposed on the substrate 110, a first semiconductor layer 122 disposed on the second semiconductor layer 121, an epitaxial structure formed by the first semiconductor layer 122 and the second semiconductor layer 121, a current blocking layer 130 disposed on the first semiconductor layer 122, a current spreading layer 140 disposed on the first semiconductor layer 122, the current spreading layer 140 covering the current blocking layer 130, a groove 150 disposed on the epitaxial structure, the groove 150 exposing a portion of the second semiconductor layer 121, a first electrode 161 disposed on the current spreading layer 140, a second electrode 162 disposed on the second semiconductor layer 121 in the groove 150, a first conductive lead 171 disposed on the first electrode 161, and a second conductive lead 172 disposed on the second electrode 162, the first conductive lead 171 is perpendicular to the first electrode 161, the second conductive lead 172 is perpendicular to the second electrode 162, and a passivation layer 180 is disposed on the current spreading layer 140 and the second semiconductor layer 121, wherein the passivation layer 180 is disposed on two sides of the first electrode 161 and the second electrode 162. In this embodiment, the second conductive leads 172 are located in the cutting channels of the led chip, so as to reduce the light emitting area of the led chip.
The led chip and the method for manufacturing the same are suitable for manufacturing various led chips, such as rgb chips, and also such as forward/flip/vertical/high voltage led chips.
In summary, the present embodiment provides a light emitting diode chip and a manufacturing method thereof, in which the structural design of the light emitting diode chip is re-optimized by the method, and the second conductive leads are disposed on the scribe lines of the light emitting diode chip, so that the second conductive leads do not occupy the light emitting area of the chip alone, and by increasing the number of the first conductive leads, the light emitting distribution of the chip is optimized, the electrical conductivity is increased, the light blocking area of the chip is reduced, and the light emitting efficiency of the light emitting diode chip is improved. The embodiment adopts a brand new process, can make the conductive lead with a larger height-width ratio on a low-precision exposure system, and can improve the luminous efficiency of the chip.
The above description is only a preferred embodiment of the present application and the explanation of the technical principle used, and it should be understood by those skilled in the art that the scope of the invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.
Besides the technical features described in the specification, other technical features are known to those skilled in the art, and are not described herein again in order to highlight the innovative features of the present invention.

Claims (3)

1. A method for manufacturing a light emitting diode chip is characterized by comprising the following steps:
providing a substrate;
forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer;
forming a patterned current blocking layer on the epitaxial structure, wherein the thickness of the patterned current blocking layer is 80-500 nm;
forming a current spreading layer on the epitaxial structure, removing part of the current spreading layer and the epitaxial structure, and forming a groove, wherein part of the second semiconductor layer is exposed out of the groove, the current spreading layer covers the patterned current blocking layer, the thickness of the current spreading layer is 20-200nm, and the depth of the groove is 1-2 μm;
forming a first electrode on the current spreading layer and a second electrode on the exposed second semiconductor layer;
forming a first conductive lead on the first electrode and a second conductive lead on the second electrode, wherein the widths of the first conductive lead and the second conductive lead are 1-2 μm;
the step of forming the first and second conductive leads includes:
forming a patterned photoresist layer on the current spreading layer and the second semiconductor layer;
forming a conducting layer on the patterned photoresist layer, and controlling the width of the conducting layer on the side wall of the patterned photoresist layer by adjusting the working condition of equipment when the conducting layer is deposited on the patterned photoresist layer;
removing part of the conductive layer, and reserving the conductive layer on the side wall of the patterned photoresist layer to form a first conductive lead and a second conductive lead;
the patterned photoresist layer comprises a first opening and a second opening, the first opening is positioned on the current expansion layer, the second opening is positioned in the groove, the first electrode grows in the first opening, and the second electrode grows in the second opening;
the patterned photoresist layer comprises a third opening on the first electrode, and the patterned photoresist layer also covers part of the second electrode;
the light emitting diode comprises two first conductive leads;
the first conducting lead is perpendicular to the first electrode, the second conducting lead is perpendicular to the second electrode, the second conducting lead is located on a cutting channel of the light-emitting diode chip, and the cutting channel is located on the outer side of the light-emitting diode chip;
and forming passivation layers on two sides of the first electrode and the second electrode.
2. The manufacturing method according to claim 1, characterized in that: the passivation layer is located on the second semiconductor layer and the current spreading layer.
3. A light emitting diode chip, comprising:
a substrate;
the epitaxial structure is positioned on the substrate and comprises a first semiconductor layer and a second semiconductor layer;
the current blocking layer is positioned on the epitaxial structure, and the thickness of the current blocking layer is 80-500 nm;
the current spreading layer is positioned on the epitaxial structure, covers the current blocking layer and is 20-200nm thick;
a groove located on the epitaxial structure, wherein the groove exposes a part of the second semiconductor layer, and the depth of the groove is 1-2 μm;
a first electrode on the current spreading layer and a second electrode on the second semiconductor layer in the recess;
the first conductive lead is positioned on the first electrode, and the second conductive lead is positioned on the second electrode and positioned on the cutting path of the light-emitting diode chip; the first conductive lead is perpendicular to the first electrode, and the second conductive lead is perpendicular to the second electrode;
the width of the first conductive lead and the second conductive lead is 1-2 μm;
and the passivation layer is positioned on the current expansion layer and the second semiconductor layer.
CN201910535164.7A 2019-06-20 2019-06-20 Light emitting diode chip and manufacturing method thereof Active CN110265515B (en)

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