CN110262887A - CPU-FPGA method for scheduling task and device based on feature identification - Google Patents
CPU-FPGA method for scheduling task and device based on feature identification Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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Abstract
The embodiment of the invention provides a kind of CPU-FPGA method for scheduling task and device based on feature identification, wherein method includes: to obtain the data volume of multiple waiting tasks and each waiting task, extract the characteristic information of each waiting task in multiple waiting tasks, cpu character information based on each waiting task, FPGA characteristic information, and task unique characteristics information, generate the feature vector of each waiting task, it will be in the feature vector input of each waiting task generated disaggregated model trained in advance, obtain the classification results of each waiting task, according to the size relation between the data volume of each waiting task, waiting task is ranked up, and each waiting task after sequence is dispatched in CPU and FPGA respectively according to preset strategy and is handled.The embodiment of the present invention can be realized the load equilibrium that CPU-FPGA is improved during CPU-FPGA task schedule.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of CPU-FPGA task schedule based on feature identification
Method and device.
Background technique
Recently as artificial intelligence, multimedia technology and the development of high-performance calculation, people are excited to Heterogeneous Computing
The extensive research interest of architecture.The unbearable high-volume of traditional server platform and diversified data processing task,
Along with the development of distributed computing and high-performance calculation, Heterogeneous Computing is come into being.Heterogeneous computing platforms incorporate isomery
Computing resource and storage resource provide the resource distribution of elasticity for the data processing of task, improve resource utilization, reduce
Cost of serving, while fault-tolerant and fault recovery technology is provided, for the data processing of task safe and reliable platform is provided,
So that more and more task immigrations are handled into heterogeneous platform.For example, task can be video data processing, picture number
According to processing etc., heterogeneous platform can be heterogeneous server etc..
It is directed to CPU (Central Processing Unit, central processing unit)-FPGA (Field- at present
Programmable Gate Array, field programmable gate array) task to be treated on heterogeneous platform, the place used
Reason method are as follows: CPU is for task received on CPU-FPGA heterogeneous platform, according to the sequencing of the task of reception, by institute
Received task is preferentially assigned on FPGA and executes, (FPGA at this time when executing needed on FPGA for task reaches certain amount
Memory it is completely occupied), then the received task of institute is assigned on CPU and is executed.
However, the existing processing method for task on CPU-FPGA heterogeneous platform, is according to the successive suitable of the task of reception
Ordered pair task is allocated processing, in practical application, the data volume that handles by different required by task it is of different sizes so that
Only task is allocated according to the sequencing of the task of reception, being easy to appear need to handle that data volume is small or computation complexity is low
Task distribute to FPGA, will need to handle the task that data volume is big or computation complexity is high and distribute to CPU, cause CPU-FPGA negative
Carry unbalanced problem.
Summary of the invention
The embodiment of the present invention is designed to provide a kind of CPU-FPGA method for scheduling task and dress based on feature identification
It sets, realizes during CPU-FPGA task schedule, further increase the load equilibrium of CPU-FPGA.Specific technical solution is such as
Under:
In a first aspect, the embodiment of the invention provides a kind of CPU-FPGA method for scheduling task based on feature identification, institute
The method of stating includes:
The data volume of multiple waiting tasks and each waiting task is obtained, the waiting task is the CPU and institute
The task of pending processing in FPGA is stated, the data volume is for data processing needed for indicating the processing waiting task
Amount；
The characteristic information of each waiting task in the multiple waiting task is extracted, the characteristic information includes: CPU spy
Reference breath, FPGA characteristic information and task unique characteristics information；The cpu character information for indicate CPU processing it is described to
The feature having when processing task, the FPGA characteristic information are used for the spy for indicating to have when FPGA handles the waiting task
Sign；
Based on the cpu character information of each waiting task, FPGA characteristic information and task unique characteristics information,
Generate the feature vector of each waiting task；Described eigenvector is the characteristic information of the waiting task through removal amount
It is generated after guiding principle；
By in the feature vector input of each waiting task generated disaggregated model trained in advance, each institute is obtained
State the classification results of waiting task, the classification results include: the first classification results and the second classification results, and described first point
For corresponding first waiting task of class result for handling in CPU, second classification results are second to be processed corresponding
Business in FPGA for handling；The disaggregated model is according to corresponding to the corresponding feature vector of preset task and preset task
Class label training obtain；
According to the size relation between the data volume of each first waiting task, to first waiting task into
Row sequence, and each first waiting task after sequence is dispatched in CPU according to preset strategy and is handled；
According to the size relation between the data volume of each second waiting task, to second waiting task into
Row sequence, and each second waiting task after sequence is dispatched in FPGA according to preset strategy and is handled.
Optionally, the cpu character information based on each waiting task, FPGA characteristic information and task are certainly
The step of body characteristic information, the feature vector of each waiting task of generation, comprising:
By the cpu character information of each waiting task, FPGA characteristic information and the removal of task unique characteristics information
Dimension obtains the cpu character data of each waiting task, FPGA characteristic and task unique characteristics data；
According to preset rules by the cpu character data of each waiting task, FPGA characteristic and task itself
Characteristic is combined into the feature vector of each waiting task.
Optionally, first classification results are CPU task subset, and second classification results are FPGA task subset,
Size relation between the data volume according to each first waiting task, arranges first waiting task
The step of sequence, comprising:
By corresponding first waiting task of the CPU task subset, according to each first waiting task data volume it
Between size relation ascending sort, obtain the first CPU task queue；
Alternatively, by corresponding first waiting task of the CPU task subset, according to the data of each first waiting task
Size relation descending sort between amount, obtains the 2nd CPU task queue；
Size relation between the data volume according to each second waiting task, to described second to be processed
The step of business is ranked up, comprising:
By corresponding second waiting task of the FPGA task subset, according to each second waiting task data volume it
Between size relation descending sort, obtain the first FPGA task queue；
Alternatively, by corresponding second waiting task of the FPGA task subset, according to the number of each second waiting task
According to the size relation ascending sort between amount, the 2nd FPGA task queue is obtained.
Optionally, each first waiting task by after sequence is dispatched in CPU according to preset strategy carries out
The step of processing, comprising:
For each first waiting task after sequence, according to each first to be processed in the first CPU task queue
Each first waiting task in the first CPU task queue is successively dispatched in CPU by the sequencing of business
Reason；
Alternatively, for each first waiting task after sequence, according in the 2nd CPU task queue each first wait locate
Each first waiting task in the 2nd CPU task queue, is successively dispatched in CPU and carries out by the inverted order sequence of reason task
Processing.
Optionally, each second waiting task by after sequence is dispatched in FPGA according to preset strategy carries out
The step of processing, comprising:
For each second waiting task after sequence, according to each second to be processed in the first FPGA task queue
Each second waiting task in the first FPGA task queue is successively dispatched in FPGA by the sequencing of business
Reason；
Alternatively, for sequence after each second waiting task, according in the 2nd FPGA task queue each second to
Each second waiting task in the 2nd FPGA task queue, is successively dispatched in FPGA by the inverted order sequence of processing task
It is handled.
Second aspect, the embodiment of the invention provides a kind of CPU-FPGA task scheduling apparatus based on feature identification, institutes
Stating device includes:
Module is obtained, for obtaining the data volume of multiple waiting tasks and each waiting task, the waiting task
For the task of pending processing in the CPU and the FPGA, the data volume handles the waiting task institute for indicating
The data processing amount needed；
Extraction module, for extracting the characteristic information of each waiting task in the multiple waiting task, the feature
Information includes: cpu character information, FPGA characteristic information and task unique characteristics information；The cpu character information is used for table
Show the feature having when CPU handles the waiting task, the FPGA characteristic information is for indicating that FPGA processing is described wait locate
The feature having when reason task；
Generation module, for the cpu character information based on each waiting task, FPGA characteristic information and task
Unique characteristics information generates the feature vector of each waiting task；Described eigenvector is the spy of the waiting task
Reference breath generates after removing dimension；
Categorization module, the classification mould trained in advance for the feature vector input by each waiting task generated
In type, the classification results of each waiting task are obtained, the classification results include: the first classification results and the second classification knot
Fruit, for corresponding first waiting task of first classification results for handling in CPU, second classification results are corresponding
Second waiting task in FPGA for handling；The disaggregated model be according to the corresponding feature vector of preset task, and it is pre-
If the training of class label corresponding to task obtains；
First scheduler module, for the size relation between the data volume according to each first waiting task, to institute
It states the first waiting task to be ranked up, and each first waiting task after sequence is dispatched to according to preset strategy
It is handled in CPU；
Second scheduler module, for the size relation between the data volume according to each second waiting task, to institute
It states the second waiting task to be ranked up, and each second waiting task after sequence is dispatched to according to preset strategy
It is handled in FPGA.
Optionally, the generation module, comprising:
Dimension submodule is removed, for by the cpu character information of each waiting task, FPGA characteristic information and task
Unique characteristics information removes dimension, obtains the cpu character data of each waiting task, and FPGA characteristic and task itself are special
Levy data；
Generate submodule, for according to preset rules by the cpu character data of each waiting task, FPGA characteristic
Accordingly and task unique characteristics data, it is combined into the feature vector of each waiting task.
Optionally, first scheduler module, is specifically used for:
By corresponding first waiting task of the CPU task subset, according to each first waiting task data volume it
Between size relation ascending sort, obtain the first CPU task queue；
Alternatively, by corresponding first waiting task of the CPU task subset, according to the data of each first waiting task
Size relation descending sort between amount, obtains the 2nd CPU task queue；
Second scheduler module, is specifically used for:
By corresponding second waiting task of the FPGA task subset, according to each second waiting task data volume it
Between size relation descending sort, obtain the first FPGA task queue；
Alternatively, by corresponding second waiting task of the FPGA task subset, according to the number of each second waiting task
According to the size relation ascending sort between amount, the 2nd FPGA task queue is obtained.
Optionally, the first scheduler module is specifically used for:
For each first waiting task after sequence, according to each first waiting task in the first CPU task queue
Each first waiting task in first CPU task queue is successively dispatched in CPU and handles by sequencing；
Alternatively, for each first waiting task after sequence, according to each first to be processed in the 2nd CPU task queue
Each first waiting task in 2nd CPU task queue, is successively dispatched in CPU and handles by the inverted order sequence of business.
Optionally, the second scheduler module is specifically used for:
For each second waiting task after sequence, according to each second waiting task in the first FPGA task queue
Each second waiting task in first FPGA task queue is successively dispatched in FPGA and handles by sequencing；
Alternatively, for each second waiting task after sequence, it is to be processed according in the 2nd FPGA task queue each second
Each second waiting task in 2nd FPGA task queue, is successively dispatched in FPGA by the inverted order sequence of task
Reason.
The third aspect, the embodiment of the invention also provides a kind of electronic equipment, including processor, communication interface, memory
And communication bus, wherein processor, communication interface, memory complete mutual communication by communication bus；
Memory, for storing computer program；
Processor when for executing the program stored on memory, realizes that one kind described in above-mentioned first aspect is based on
The CPU-FPGA method for scheduling task step of feature identification.
Fourth aspect, the embodiment of the invention also provides a kind of computer readable storage mediums, which is characterized in that the meter
Computer program is stored in calculation machine readable storage medium storing program for executing, the computer program is executed by processor described in above-mentioned first aspect
It is a kind of based on feature identification CPU-FPGA method for scheduling task step.
The embodiment of the present invention the utility model has the advantages that
A kind of CPU-FPGA method for scheduling task and device based on feature identification provided in an embodiment of the present invention, due to right
The classification of waiting task is realized based on the characteristic information of each waiting task feature vector generated, scheduling to
Before processing task, cpu character information, FPGA characteristic information and the task unique characteristics letter of each waiting task are comprehensively considered
Breath, and then classify to waiting task, so that the first waiting task obtained after classification is more suitable in CPU
Reason, the second waiting task are more suitable for handling in FPGA, realize during CPU-FPGA task schedule, further increase
The load equilibrium of CPU-FPGA, also, when being scheduled to waiting task, due to the data volume based on waiting task
Between size relation be scheduled, therefore can preferably coordinate the resource using CPU and FPGA.
Certainly, implement any of the products of the present invention or method it is not absolutely required at the same reach all the above excellent
Point.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is that a kind of process of CPU-FPGA method for scheduling task based on feature identification provided in an embodiment of the present invention is shown
It is intended to；
Fig. 2 is feature vectors generating mode flow diagram provided in an embodiment of the present invention；
Fig. 3 is that a kind of structure of CPU-FPGA task scheduling apparatus based on feature identification provided in an embodiment of the present invention is shown
It is intended to；
Fig. 4 is a kind of structural schematic diagram of generation module provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of a kind of electronic equipment provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to solve the problem of existing CPU-FPGA load imbalance caused during CPU-FPGA task schedule,
The embodiment of the invention provides a kind of CPU-FPGA method for scheduling task and device based on feature identification.
It is provided for the embodiments of the invention a kind of CPU-FPGA method for scheduling task based on feature identification first below
It is introduced.
As shown in FIG. 1, FIG. 1 is a kind of task schedule sides CPU-FPGA based on feature identification provided in an embodiment of the present invention
The flow diagram of method, this method may include:
S101, the data volume for obtaining multiple waiting tasks and each waiting task.
In the embodiment of the present invention, for the scheduling process of task on CPU-FPGA heterogeneous platform, it can be executed by CPU.
Before being scheduled to task, the data volume of multiple waiting tasks and each waiting task can be first obtained.Wherein,
Waiting task can be indicated for the task of pending processing in CPU and FPGA, the data volume of waiting task processing to
Handle the data processing amount of required by task.
In practical application, acquired waiting task can be the task that user sends to CPU-FPGA heterogeneous platform,
It is also possible to the task that other equipment are sent to CPU-FPGA heterogeneous platform.
S102, the characteristic information for extracting each waiting task in multiple waiting tasks.
After obtaining multiple waiting tasks, it is corresponding that each waiting task in multiple waiting tasks can be extracted
Characteristic information, this feature information may include: cpu character information, FPGA characteristic information and task unique characteristics information.Its
In, cpu character information is used for the feature for indicating to have when CPU handles waiting task, and FPGA characteristic information is for indicating FPGA
The feature having when handling waiting task.
It should be understood that cpu character information can be the intrinsic some characteristic attributes of CPU, FPGA characteristic information be can be
FPGA intrinsic some characteristic attributes.Illustratively, cpu character information and FPGA characteristic information may include: cpu chip frequency
Maximum data transfer rate, CPU between rate, fpga chip frequency, CPU and host memory and the maximum bandwidth between FPGA with
And bandwidth between local storage and global storage etc..
Task unique characteristics information may include: static nature information and dynamic feature information.Illustratively, static nature
Information may include: the interval time of OpenCL (Open Computing Language, open operation language) kernel, first
Clock cycle number, LUTs (Look-Up-Tables, the look-up table) utilization rate, FFs (Fringe lost before a effective output
Field Switching, fringe field switching technique) utilization rate, the optimal clock cycle of OpenCL kernel, calculating task complexity
Degree etc., for example, first effectively preceding clock cycle number lost of output can be, when first effectively output is in third
It can be used after the clock period, then this first effectively preceding clock cycle number lost of output is 2, the complexity of task, which can be, appoints
The complexity etc. of algorithm in business, the static nature information of the task can indicate that the waiting task will not be sent out during processing
The feature for changing.Dynamic feature information may include: that host is transferred to the data volume of FPGA, FPGA is transferred to the data of host
Amount, CPU and FPGA overall situation work item quantity and CPU and FPGA partial duty amount quantity etc., the dynamic feature information of the task
It can indicate the waiting task changed feature during processing.
S103, the cpu character information based on each waiting task, FPGA characteristic information and task unique characteristics information,
Generate the feature vector of each waiting task.
In the embodiment of the present invention, the characteristic information of each waiting task is extracted, by the characteristic information of waiting task through going
Except the feature vector for generating each waiting task after dimension, referring to fig. 2, Fig. 2 be a kind of feature provided in an embodiment of the present invention to
Generating mode flow diagram is measured, which may include:
S1031, the cpu character information by each waiting task, FPGA characteristic information and task unique characteristics information are gone
Except dimension, the cpu character data of each waiting task, FPGA characteristic and task unique characteristics data are obtained.
Illustratively, the cpu character information of waiting task, FPGA characteristic information and task unique characteristics information can be with
It include: cpu chip frequency for 50Hz, the maximum bandwidth between CPU and FPGA is 50bps, the optimal clock week of OpenCL kernel
Phase is that the data volume that 50s, FPGA are transferred to host is 50MB, CPU and FPGA partial duty amount quantity is 50 etc., by these spies
Reference breath removal dimension, correspondence obtain the cpu character data of waiting task, FPGA characteristic and task unique characteristics number
According to are as follows: maximum bandwidth of the cpu chip frequency between 50, CPU and FPGA is the optimal clock cycle of 50, OpenCL kernel to be
50, FPGA is transferred to that the data volume of host is 50, CPU and FPGA partial duty amount quantity is 50 etc..
S1032, according to preset rules by the cpu character data of each waiting task, FPGA characteristic and task from
Body characteristic is combined into the feature vector of each waiting task.
Illustratively, the cpu character data of waiting task, FPGA characteristic and task unique characteristics data are obtained
Are as follows: maximum bandwidth of the cpu chip frequency between 50, CPU and FPGA be 50 the optimal clock cycle of 50, OpenCL kernel,
FPGA is transferred to that the data volume of host is 50, CPU and FPGA partial duty amount quantity is 50 etc., these characteristics are combined into
The feature vector of waiting task can be expressed as (50,50,50,50,50).Wherein, preset rules can be cpu character number
According to front is placed on, FPGA characteristic is placed on centre, task unique characteristics data are placed on finally, being combined into turn to be processed
The feature vector of task；Preset rules are also possible to the cpu character data of waiting task, FPGA characteristic and task
Unique characteristics data random alignment, is combined into the feature vector of waiting task.Specifically, setting this field skill of preset rules
Art personnel can be configured according to actual needs, and the embodiment of the present invention is not limited thereto.
Referring to Fig. 1, S104, the disaggregated model for training the feature vector input of each waiting task generated in advance
In, obtain the classification results of each waiting task.
Will in the trained in advance disaggregated model of feature vector input of each waiting task of generation, further obtain respectively to
The classification results of processing task.The classification results may include: the first classification results and the second classification results, wherein first point
Corresponding first waiting task of class result for handling in CPU, use by corresponding second waiting task of the second classification results
In being handled in FPGA.
Disaggregated model is trained according to class label corresponding to the corresponding feature vector of preset task and preset task
It arrives.Illustratively, which can be based on SVM (Support Vector Machine, support vector machines) algorithm
Svm classifier model, or be based on KNN (k-NearestNeighbor, K arest neighbors) algorithm KNN disaggregated model, or be based on K-
The K-means disaggregated model of means (k-means clustering algorithm, k mean cluster) algorithm.Preset task can
To be the task in the set of tasks for train classification models collected in advance, the set of tasks collected in advance can for comprising
The data volume of the multiple tasks set of tasks not equal in 1M to 1G, the task in set of tasks may include vision generic task plus
Close generic task and high performance parallel task dispatching, for example, vision generic task may include: edge detection generic task, de-watermarked class
Task or target detection generic task etc..
Illustratively, for the preset task collected in advance, it can refer to the characteristic information of said extracted waiting task, it is raw
It is corresponding to generate preset task to extract the characteristic information of preset task at the implementation of the feature vector of each waiting task
Feature vector.Further actual measurement obtains the corresponding speed-up ratio of preset task on CPU-FPGA platform, which accelerates
Degree can handle the ratio of required processing time with preset task accurately to describe in CPU and FPGA respectively.It can incite somebody to action
Preset task of the speed-up ratio greater than 4 is defined as acceleration task, and the preset task by speed-up ratio no more than 4 is defined as common task,
Further, will accelerate the corresponding classification logotype of task is the second classification results, is the by the corresponding classification logotype of common task
One classification results obtain class label corresponding to preset task.Then, according to the corresponding feature vector of preset task, and it is pre-
If the training of class label corresponding to task obtains disaggregated model, specific training process can refer to the realization of the prior art, this
This will not be repeated here for inventive embodiments.
In the embodiment of the present invention, will accelerate the corresponding classification logotype of task is the second classification results, and common task is corresponding
Classification logotype be the first classification results, the obtained disaggregated model of training can input the feature vector of each waiting task
In the disaggregated model, corresponding first classification results of the first waiting task handled in CPU are obtained, and in FPGA
Corresponding second classification results of the second waiting task of reason.Allow to task complexity is low or data calculate and stroke
It spends waiting task that is small, being unfavorable for fpga chip acceleration to be divided into the first classification results and handle in CPU, by task complexity
High or data calculate the waiting task that degree of concurrence is big, is conducive to fpga chip acceleration and are divided into the second classification results and exist
It is handled in FPGA, to improve the load equilibrium of CPU-FPGA.
S105, according to the size relation between the data volume of each first waiting task, the first waiting task is carried out
Sequence, and each first waiting task after sequence is dispatched in CPU according to preset strategy and is handled.
In the embodiment of the present invention, the first classification results can be expressed as CPU task subset, and the second classification results can indicate
For FPGA task subset.CPU task subset is corresponding with multiple first waiting tasks, and FPGA task subset is corresponding with multiple second
Waiting task.
Wherein, according to the size relation between the data volume of each first waiting task, the first waiting task is carried out
The embodiment of sequence may include:
It is a kind of to the first waiting task sequence embodiment in, can be by CPU task subset corresponding first wait locate
Reason task obtains the first CPU task team according to the size relation ascending sort between the data volume of each first waiting task
Column.Wherein, the data volume of the first waiting task can be expressed as data processing amount needed for handling first waiting task.
In the embodiment that another kind sorts to the first waiting task, can by CPU task subset corresponding first to
Processing task obtains the 2nd CPU task team according to the size relation descending sort between the data volume of each first waiting task
Column.Wherein, the data volume of the second waiting task can be expressed as data processing amount needed for handling second waiting task.
The difference of first waiting task sequence embodiment, by each first waiting task after sequence according to default plan
It is also different to be slightly dispatched to the embodiment handled in CPU.Specifically, for above-mentioned a kind of to the sequence of the first waiting task
Embodiment, each first waiting task after sequence is dispatched to the embodiment party handled in CPU according to preset strategy
Formula can be with are as follows:
For each first waiting task after sequence, according to each first waiting task in the first CPU task queue
Each first waiting task in first CPU task queue is successively dispatched in CPU and handles by sequencing.At this point, pre-
If strategy can be with are as follows: according to the sequencing of each first waiting task in the first CPU task queue successively to each first wait locate
Reason task is scheduled.
For the above-mentioned another embodiment to the sequence of the first waiting task, by each first to be processed after sequence
Business is dispatched to the embodiment that is handled in CPU according to preset strategy can be with are as follows:
For each first waiting task after sequence, according to each first waiting task in the 2nd CPU task queue
Each first waiting task in 2nd CPU task queue, is successively dispatched in CPU and handles by inverted order sequence.At this point, pre-
If strategy can be with are as follows: according to the inverted order sequence of each first waiting task in the first CPU task queue successively to each first wait locate
Reason task is scheduled.
As a kind of optional embodiment of the present invention, closed according to the size between the data volume of each first waiting task
System, each first waiting task is ranked up, and after sequence according to sequencing or inverted order sequence successively by each first to
Processing task schedule is handled into CPU, so that smaller corresponding first waiting task of data volume is preferentially in CPU
Reason.Further, can be when CPU task queue be empty, data volume is smaller by corresponding the in priority scheduling FPGA task queue
Two waiting tasks, in order to preferably coordinate the resource using CPU and FPGA.
S106, according to the size relation between the data volume of each second waiting task, the second waiting task is carried out
Sequence, and each second waiting task after sequence is dispatched in FPGA according to preset strategy and is handled.
Wherein, according to the size relation between the data volume of each second waiting task, the second waiting task is carried out
The embodiment of sequence may include:
It is a kind of to the second waiting task sequence embodiment in, can be by FPGA task subset corresponding second wait locate
Reason task obtains the first FPGA task team according to the size relation descending sort between the data volume of each second waiting task
Column.
In the embodiment that another kind sorts to the second waiting task, can by FPGA task subset corresponding second to
Processing task obtains the 2nd FPGA task according to the size relation ascending sort between the data volume of each second waiting task
Queue.
The difference of second waiting task sequence embodiment, by each second waiting task after sequence according to default plan
It is also different to be slightly dispatched to the embodiment handled in FPGA.Specifically, for above-mentioned a kind of to the second waiting task row
Each second waiting task after sequence is dispatched to the implementation handled in FPGA according to preset strategy by the embodiment of sequence
Mode can be with are as follows:
For each second waiting task after sequence, according to each second waiting task in the first FPGA task queue
Each second waiting task in first FPGA task queue is successively dispatched in FPGA and handles by sequencing.At this point,
Preset strategy can be with are as follows: according to each second waiting task in the first FPGA task queue sequencing successively to each second to
Processing task is scheduled.
For the above-mentioned another embodiment to the sequence of the second waiting task, by each second to be processed after sequence
Business is dispatched to the embodiment that is handled in FPGA according to preset strategy can be with are as follows:
For each second waiting task after sequence, according to each second waiting task in the 2nd FPGA task queue
Each second waiting task in 2nd FPGA task queue, is successively dispatched in FPGA and handles by inverted order sequence.At this point,
Preset strategy can be with are as follows: according to each second waiting task in the 2nd FPGA task queue inverted order sequence successively to each second to
Processing task is scheduled.
As a kind of optional embodiment of the present invention, closed according to the size between the data volume of each second waiting task
System, each second waiting task is ranked up, and after sequence according to sequencing or inverted order sequence successively by each second to
Processing task schedule is handled into FPGA, so that larger corresponding second waiting task of data volume is preferentially in FPGA
Reason.Further, can be when FPGA task queue be empty, data volume larger corresponding the in priority scheduling CPU task queue
One waiting task, in order to preferably coordinate the resource using CPU and FPGA.
A kind of CPU-FPGA method for scheduling task based on feature identification provided in an embodiment of the present invention, due to to be processed
The classification of task is realized based on the characteristic information of each waiting task feature vector generated, in be processed of scheduling
Before business, cpu character information, FPGA characteristic information and the task unique characteristics information of each waiting task are comprehensively considered, in turn
Classify to waiting task so that obtained the first waiting task is more suitable for handling in CPU after classification, second to
Processing task is more suitable for handling in FPGA, realizes during CPU-FPGA task schedule, further increases CPU-FPGA's
Load equilibrium, also, when being scheduled to waiting task, due to the size between the data volume based on waiting task
Relationship is scheduled, therefore can preferably coordinate the resource using CPU and FPGA.
Corresponding to above method embodiment, the embodiment of the invention provides a kind of CPU-FPGA tasks based on feature identification
Dispatching device, as shown in figure 3, the apparatus may include:
Module 201 is obtained, for obtaining the data volume of multiple waiting tasks and each waiting task, waiting task is
The task of pending processing in CPU and FPGA, data volume is for data processing amount needed for indicating processing waiting task.
Extraction module 202, for extracting the characteristic information of each waiting task in multiple waiting tasks, characteristic information packet
It includes: cpu character information, FPGA characteristic information and task unique characteristics information；Cpu character information for indicate CPU processing to
The feature having when processing task, FPGA characteristic information are used for the feature for indicating to have when FPGA handles waiting task.
Generation module 203, for the cpu character information based on each waiting task, FPGA characteristic information and task are certainly
Body characteristic information generates the feature vector of each waiting task；Feature vector is the characteristic information of waiting task through removal amount
It is generated after guiding principle.
Categorization module 204, the classification mould trained in advance for the feature vector input by each waiting task generated
In type, the classification results of each waiting task are obtained, classification results include: the first classification results and the second classification results, and first
Corresponding first waiting task of classification results in CPU for handling, corresponding second waiting task of the second classification results
For being handled in FPGA；Disaggregated model is according to classification corresponding to the corresponding feature vector of preset task and preset task
Label training obtains.
First scheduler module 205, for the size relation between the data volume according to each first waiting task, to first
Waiting task is ranked up, and each first waiting task after sequence is dispatched in CPU according to preset strategy
Reason.
Second scheduler module 206, for the size relation between the data volume according to each second waiting task, to second
Waiting task is ranked up, and each second waiting task after sequence is dispatched in FPGA according to preset strategy
Reason.
A kind of CPU-FPGA task scheduling apparatus based on feature identification provided in an embodiment of the present invention, due to to be processed
The classification of task is realized based on the characteristic information of each waiting task feature vector generated, in be processed of scheduling
Before business, cpu character information, FPGA characteristic information and the task unique characteristics information of each waiting task are comprehensively considered, in turn
Classify to waiting task so that obtained the first waiting task is more suitable for handling in CPU after classification, second to
Processing task is more suitable for handling in FPGA, realizes during CPU-FPGA task schedule, further increases CPU-FPGA's
Load equilibrium, also, when being scheduled to waiting task, due to the size between the data volume based on waiting task
Relationship is scheduled, therefore can preferably coordinate the resource using CPU and FPGA.
It should be noted that the device of the embodiment of the present invention is and a kind of CPU- based on feature identification shown in FIG. 1
FPGA method for scheduling task corresponding device, a kind of CPU-FPGA method for scheduling task based on feature identification shown in FIG. 1
All embodiments are suitable for the device, and can reach identical beneficial effect.
Optionally, as shown in figure 4, generation module 203, comprising:
Dimension submodule 2031 is removed, for by the cpu character information of each waiting task, FPGA characteristic information and task
Unique characteristics information removes dimension, obtains the cpu character data of each waiting task, and FPGA characteristic and task itself are special
Levy data.
Generate submodule 2032, for according to preset rules by the cpu character data of each waiting task, FPGA characteristic
Accordingly and task unique characteristics data, it is combined into the feature vector of each waiting task.
Optionally, the first scheduler module 205, is specifically used for:
By corresponding first waiting task of CPU task subset, between the data volume according to each first waiting task
Size relation ascending sort obtains the first CPU task queue.
Alternatively, by corresponding first waiting task of CPU task subset, according to each first waiting task data volume it
Between size relation descending sort, obtain the 2nd CPU task queue.
Second scheduler module 206, is specifically used for:
By corresponding second waiting task of FPGA task subset, between the data volume according to each second waiting task
Size relation descending sort obtains the first FPGA task queue.
Alternatively, by corresponding second waiting task of FPGA task subset, according to the data volume of each second waiting task
Between size relation ascending sort, obtain the 2nd FPGA task queue.
Optionally, the first scheduler module 205, is specifically used for:
For each first waiting task after sequence, according to each first waiting task in the first CPU task queue
Each first waiting task in first CPU task queue is successively dispatched in CPU and handles by sequencing.
Alternatively, for each first waiting task after sequence, according to each first to be processed in the 2nd CPU task queue
Each first waiting task in 2nd CPU task queue, is successively dispatched in CPU and handles by the inverted order sequence of business.
Optionally, the second scheduler module 206, is specifically used for:
For each second waiting task after sequence, according to each second waiting task in the first FPGA task queue
Each second waiting task in first FPGA task queue is successively dispatched in FPGA and handles by sequencing.
Alternatively, for each second waiting task after sequence, it is to be processed according in the 2nd FPGA task queue each second
Each second waiting task in 2nd FPGA task queue, is successively dispatched in FPGA by the inverted order sequence of task
Reason.
The embodiment of the invention also provides a kind of electronic equipment, as shown in figure 5, include processor 301, communication interface 302,
Memory 303 and communication bus 304, wherein processor 301, communication interface 302, memory 303 are complete by communication bus 304
At mutual communication,
Memory 303, for storing computer program；
Processor 301 when for executing the program stored on memory 303, is realized any of the above-described a kind of based on feature
The step of CPU-FPGA method for scheduling task of identification.
A kind of electronic equipment provided in an embodiment of the present invention, since the classification to waiting task is based on each to be processed
The characteristic information of business feature vector generated before dispatching waiting task, comprehensively considers each waiting task come what is realized
Cpu character information, FPGA characteristic information and task unique characteristics information, and then classify to waiting task so that
The first waiting task obtained after classification is more suitable for handling in CPU, and the second waiting task is more suitable in FPGA
Reason is realized during CPU-FPGA task schedule, further increases the load equilibrium of CPU-FPGA, also, treating place
It, can be more since the size relation between the data volume based on waiting task is scheduled when reason task is scheduled
Good coordination utilizes the resource of CPU and FPGA.
The communication bus that above-mentioned electronic equipment is mentioned can be Peripheral Component Interconnect standard (Peripheral Component
Interconnect, PCI) bus or expanding the industrial standard structure (Extended Industry Standard
Architecture, EISA) bus etc..The communication bus can be divided into address bus, data/address bus, control bus etc..For just
It is only indicated with a thick line in expression, figure, it is not intended that an only bus or a type of bus.
Communication interface is for the communication between above-mentioned electronic equipment and other equipment.
Memory may include random access memory (Random Access Memory, RAM), also may include non-easy
The property lost memory (Non-Volatile Memory, NVM), for example, at least a magnetic disk storage.Optionally, memory may be used also
To be storage device that at least one is located remotely from aforementioned processor.
Above-mentioned processor can be general processor, including central processing unit (Central Processing Unit,
CPU), network processing unit (Network Processor, NP) etc.；It can also be digital signal processor (Digital Signal
Processing, DSP), it is specific integrated circuit (Application Specific Integrated Circuit, ASIC), existing
It is field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete
Door or transistor logic, discrete hardware components.
In another embodiment provided by the invention, a kind of computer readable storage medium is additionally provided, which can
It reads to be stored with computer program in storage medium, the computer program realizes that any of the above-described one kind is based on when being executed by processor
The step of CPU-FPGA method for scheduling task of feature identification.
In another embodiment provided by the invention, a kind of computer program product comprising instruction is additionally provided, when it
When running on computers, so that computer executes any CPU-FPGA task based on feature identification in above-described embodiment
The step of dispatching method.
In the above-described embodiments, can come wholly or partly by software, hardware, firmware or any combination thereof real
It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.The computer program
Product includes one or more computer instructions.When loading on computers and executing the computer program instructions, all or
It partly generates according to process or function described in the embodiment of the present invention.The computer can be general purpose computer, dedicated meter
Calculation machine, computer network or other programmable devices.The computer instruction can store in computer readable storage medium
In, or from a computer readable storage medium to the transmission of another computer readable storage medium, for example, the computer
Instruction can pass through wired (such as coaxial cable, optical fiber, number from a web-site, computer, server or data center
User's line (DSL)) or wireless (such as infrared, wireless, microwave etc.) mode to another web-site, computer, server or
Data center is transmitted.The computer readable storage medium can be any usable medium that computer can access or
It is comprising data storage devices such as one or more usable mediums integrated server, data centers.The usable medium can be with
It is magnetic medium, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or semiconductor medium (such as solid state hard disk
Solid State Disk (SSD)) etc..
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Each embodiment in this specification is all made of relevant mode and describes, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for device/
For electronic equipment embodiment, since it is substantially similar to the method embodiment, so be described relatively simple, related place referring to
The part of embodiment of the method illustrates.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
It is interior.
Claims (10)
1. a kind of CPU-FPGA method for scheduling task based on feature identification, which is characterized in that the described method includes:
Obtain the data volume of multiple waiting tasks and each waiting task, the waiting task is the CPU and described
The task of pending processing in FPGA, the data volume is for data processing amount needed for indicating the processing waiting task；
The characteristic information of each waiting task in the multiple waiting task is extracted, the characteristic information includes: cpu character letter
Breath, FPGA characteristic information and task unique characteristics information；The cpu character information is described to be processed for indicating CPU processing
The feature having when task, the FPGA characteristic information are used for the feature for indicating to have when FPGA handles the waiting task；
Based on the cpu character information of each waiting task, FPGA characteristic information and task unique characteristics information are generated
The feature vector of each waiting task；Described eigenvector is the characteristic information of the waiting task after removing dimension
It generates；
Will in the trained in advance disaggregated model of feature vector input of each waiting task generated, obtain it is each it is described to
The classification results of processing task, the classification results include: the first classification results and the second classification results, the first classification knot
Corresponding first waiting task of fruit for handling in CPU, use by corresponding second waiting task of second classification results
In being handled in FPGA；The disaggregated model is according to class corresponding to the corresponding feature vector of preset task and preset task
Distinguishing label training obtains；
According to the size relation between the data volume of each first waiting task, first waiting task is arranged
Sequence, and each first waiting task after sequence is dispatched in CPU according to preset strategy and is handled；
According to the size relation between the data volume of each second waiting task, second waiting task is arranged
Sequence, and each second waiting task after sequence is dispatched in FPGA according to preset strategy and is handled.
2. the method according to claim 1, wherein the cpu character letter based on each waiting task
The step of breath, FPGA characteristic information and task unique characteristics information, the feature vector of each waiting task of generation, packet
It includes:
By the cpu character information of each waiting task, FPGA characteristic information and task unique characteristics information remove dimension,
Obtain the cpu character data of each waiting task, FPGA characteristic and task unique characteristics data；
According to preset rules by the cpu character data of each waiting task, FPGA characteristic and task unique characteristics
Data are combined into the feature vector of each waiting task.
3. according to the method described in claim 2, it is characterized in that, first classification results are CPU task subset, described the
Two classification results are FPGA task subset, the size relation between the data volume according to each first waiting task,
The step of first waiting task is ranked up, comprising:
By corresponding first waiting task of the CPU task subset, between the data volume according to each first waiting task
Size relation ascending sort obtains the first CPU task queue；
Alternatively, by corresponding first waiting task of the CPU task subset, according to each first waiting task data volume it
Between size relation descending sort, obtain the 2nd CPU task queue；
Size relation between the data volume according to each second waiting task, to second waiting task into
The step of row sequence, comprising:
By corresponding second waiting task of the FPGA task subset, between the data volume according to each second waiting task
Size relation descending sort obtains the first FPGA task queue；
Alternatively, by corresponding second waiting task of the FPGA task subset, according to the data volume of each second waiting task
Between size relation ascending sort, obtain the 2nd FPGA task queue.
4. according to the method described in claim 3, it is characterized in that, each first waiting task by after sequence is pressed
The step of being handled in CPU is dispatched to according to preset strategy, comprising:
For each first waiting task after sequence, according to each first waiting task in the first CPU task queue
Each first waiting task in the first CPU task queue is successively dispatched in CPU and handles by sequencing；
Alternatively, for each first waiting task after sequence, according to each first to be processed in the 2nd CPU task queue
Each first waiting task in the 2nd CPU task queue, is successively dispatched in CPU by the inverted order sequence of business
Reason.
5. according to the method described in claim 3, it is characterized in that, each second waiting task by after sequence is pressed
The step of being handled in FPGA is dispatched to according to preset strategy, comprising:
For each second waiting task after sequence, according to each second waiting task in the first FPGA task queue
Each second waiting task in the first FPGA task queue is successively dispatched in FPGA and handles by sequencing；
Alternatively, for each second waiting task after sequence, it is to be processed according in the 2nd FPGA task queue each second
Each second waiting task in the 2nd FPGA task queue, is successively dispatched in FPGA and carries out by the inverted order sequence of task
Processing.
6. a kind of CPU-FPGA task scheduling apparatus based on feature identification, which is characterized in that described device includes:
Module is obtained, for obtaining the data volume of multiple waiting tasks and each waiting task, the waiting task is institute
The task of pending processing in the CPU and FPGA is stated, the data volume is for indicating needed for handling the waiting task
Data processing amount；
Extraction module, for extracting the characteristic information of each waiting task in the multiple waiting task, the characteristic information
It include: cpu character information, FPGA characteristic information and task unique characteristics information；The cpu character information is for indicating CPU
The feature having when handling the waiting task, the FPGA characteristic information is for indicating that FPGA handles the waiting task
When the feature that has；
Generation module, for the cpu character information based on each waiting task, FPGA characteristic information and task itself
Characteristic information generates the feature vector of each waiting task；Described eigenvector is that the feature of the waiting task is believed
What breath generated after removing dimension；
Categorization module, the disaggregated model trained in advance for the feature vector input by each waiting task generated
In, the classification results of each waiting task are obtained, the classification results include: the first classification results and the second classification knot
Fruit, for corresponding first waiting task of first classification results for handling in CPU, second classification results are corresponding
Second waiting task in FPGA for handling；The disaggregated model be according to the corresponding feature vector of preset task, and it is pre-
If the training of class label corresponding to task obtains；
First scheduler module, for the size relation between the data volume according to each first waiting task, to described
One waiting task is ranked up, and each first waiting task after sequence is dispatched in CPU according to preset strategy
It is handled；
Second scheduler module, for the size relation between the data volume according to each second waiting task, to described
Two waiting tasks are ranked up, and each second waiting task after sequence is dispatched in FPGA according to preset strategy
It is handled.
7. device according to claim 6, which is characterized in that the generation module, comprising:
Dimension submodule is removed, for by the cpu character information of each waiting task, FPGA characteristic information and task itself
Characteristic information removes dimension, obtains the cpu character data of each waiting task, FPGA characteristic and task unique characteristics number
According to；
Generate submodule, for according to preset rules by the cpu character data of each waiting task, FPGA characteristic with
And task unique characteristics data, it is combined into the feature vector of each waiting task.
8. device according to claim 7, which is characterized in that first scheduler module is specifically used for:
By corresponding first waiting task of the CPU task subset, between the data volume according to each first waiting task
Size relation ascending sort obtains the first CPU task queue；
Alternatively, by corresponding first waiting task of the CPU task subset, according to each first waiting task data volume it
Between size relation descending sort, obtain the 2nd CPU task queue；
Second scheduler module, is specifically used for:
By corresponding second waiting task of the FPGA task subset, between the data volume according to each second waiting task
Size relation descending sort obtains the first FPGA task queue；
Alternatively, by corresponding second waiting task of the FPGA task subset, according to the data volume of each second waiting task
Between size relation ascending sort, obtain the 2nd FPGA task queue.
9. a kind of electronic equipment, which is characterized in that including processor, communication interface, memory and communication bus, wherein processing
Device, communication interface, memory complete mutual communication by communication bus；
Memory, for storing computer program；
Processor when for executing the program stored on memory, realizes any method and step of claim 1-5.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer in the computer readable storage medium
Program realizes claim 1-5 any method and step when the computer program is executed by processor.
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| CN110908797B (en) * | 2019-11-07 | 2023-09-15 | 浪潮电子信息产业股份有限公司 | Call request data processing method, device, equipment, storage medium and system |
| CN111400007A (en) * | 2020-03-13 | 2020-07-10 | 重庆特斯联智慧科技股份有限公司 | Task scheduling method and system based on edge calculation |
| CN116073890A (en) * | 2023-03-06 | 2023-05-05 | 成都星联芯通科技有限公司 | Service data processing method, device, receiving equipment, earth station and storage medium |
| CN116073890B (en) * | 2023-03-06 | 2023-06-02 | 成都星联芯通科技有限公司 | Service data processing method, device, receiving equipment, earth station and storage medium |
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