CN110246830B - Semiconductor structure, image sensor, chip and forming method thereof - Google Patents
Semiconductor structure, image sensor, chip and forming method thereof Download PDFInfo
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- CN110246830B CN110246830B CN201910497752.6A CN201910497752A CN110246830B CN 110246830 B CN110246830 B CN 110246830B CN 201910497752 A CN201910497752 A CN 201910497752A CN 110246830 B CN110246830 B CN 110246830B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
A semiconductor structure, a method of forming an image sensor chip, an image sensor chip and an image sensor, the structure comprising: a substrate comprising a plurality of mutually discrete chip regions; each chip area comprises more than 4 discrete device areas, each device area comprises pixel array units, and at least 2 pixel array units are adjacent in each chip area. The semiconductor structure improves the yield of the image sensor.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for forming an image sensor chip, and an image sensor.
Background
In the field of semiconductor technology, an image sensor is a functional device that can convert an optical image into an electrical signal. Image sensors can be broadly classified into Charge Coupled Devices (CCDs) and complementary metal oxide semiconductor Image sensors (CIS).
At present, the CCD is a main practical solid-state image sensing device and has the advantages of low reading noise, large dynamic range, high response sensitivity and the like. The CMOS image sensor has advantages of simple process, easy integration with other devices, small size, light weight, and low power consumption, and is widely used in the fields of digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), and vehicle imaging devices.
However, the chip of the image sensor is easily damaged or failed in the manufacturing process, so that the yield of the whole image sensor is reduced, and the manufacturing cost of the image sensor is increased.
Disclosure of Invention
The invention solves the technical problems of reducing the rejection rate of the image sensor chip and reducing the manufacturing cost of the image sensor chip.
To solve the above problem, an aspect of the present invention provides a semiconductor structure, including: a substrate comprising a plurality of mutually discrete chip regions; each chip area comprises more than 4 discrete device areas, each device area comprises pixel array units, and at least 2 pixel array units are adjacent in each chip area.
Optionally, each of the chip regions includes 4 adjacent device regions, the 4 adjacent device regions are arranged in a 2 × 2 array, the 4 adjacent device regions are arranged in a centrosymmetric manner, and the pixel array units of the 4 adjacent device regions are adjacent to each other.
Optionally, the number of the device regions in each of the chip regions is 4.
Optionally, the number of the device regions in each of the chip regions is greater than 4.
Optionally, the device region further includes: the device comprises a timing and control unit, a comparison loop unit, a memory unit, a column selection unit, a row selection unit, a data transmission unit, a phase locking loop unit, a signal conversion unit and a ramp generator unit.
Another aspect of the embodiments of the present invention provides a method for forming an image sensor chip, including:
providing a semiconductor structure as described above; detecting the plurality of chip areas to obtain detection result information corresponding to each chip area; and cutting the substrate according to the detection result information of the chip areas to form a plurality of mutually independent chips, wherein each chip comprises at least 1 device area.
Optionally, the method further includes: and arranging a lens on the chip, wherein the lens has a projection pattern on the chip, and the pixel array unit in the chip is in the range of the projection pattern.
Optionally, the method further includes: and carrying out a packaging process on the chip.
Optionally, the detection result information includes: a number of device regions damaged within the chip region.
Optionally, the detection result information includes: the detection result information includes: and the damage ratio of the chip area is the ratio of the number of damaged device areas in the chip area to the total number of the device areas.
Optionally, the method for forming a plurality of mutually independent chips includes: and performing first cutting between adjacent chip areas to form a plurality of mutually independent chip areas.
Optionally, the chip region includes 4 device regions; the method for forming a plurality of mutually independent chips further comprises the following steps: and when the detection result information comprises the damage number of the device areas in the chip area and the damage number is more than 1, performing second cutting on the chip area to enable a plurality of device areas in the chip area to form mutually independent device areas.
Optionally, the method for forming a plurality of mutually independent chips includes: and performing first cutting between adjacent chip areas to form a plurality of mutually independent chip areas.
Optionally, the method for forming a plurality of mutually independent chips further includes: and when the detection result information comprises the damage ratio and the damage ratio is larger than 1/3, performing second cutting on the chip area to enable a plurality of device areas in the chip area to form mutually independent device areas.
Another aspect of an embodiment of the present invention provides a chip of an image sensor, including: an image sensor chip formed by any of the above methods.
Another aspect of an embodiment of the present invention provides an image sensor, including: the image sensor chip described above.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor structure of the technical scheme of the invention, because the chip area and the device area are separated on the substrate, no matter the substrate is cut to form the image sensor chip with the chip area, or the chip area on the substrate is continuously cut to form the image sensor chip with a single device area, the image sensor chip with the chip area and the image sensor chip with the single device area can be independently used, and further the substrate has a more flexible cutting mode; meanwhile, as at least 2 pixel array units are adjacent in each chip area, and the at least 2 pixel array units can form pixel array unit combination in the chip area, the resolution of the formed image sensor chip with the chip area is higher, and the resolution of the formed image sensor chip with a single device area is lower, so that the image sensor formed after the substrate is cut has wider application environment.
Correspondingly, in the method for forming the image sensor chip according to the embodiment of the invention, since the plurality of chip areas are detected, the substrate is cut according to the obtained detection result information corresponding to each chip area, and then the plurality of discrete chips each including at least 1 device area are formed, a plurality of different image sensor chips, namely the image sensor chips including different numbers of device areas, can be obtained to flexibly correspond to different resolution requirements.
Further, since the structure of the lens is affected by the structure of the pixel array unit within the chip, the kind and size of the lens may be controlled according to the structure of the pixel array unit within the chip.
Further, since the image sensor chip including the plurality of device regions is formed by performing the first dicing, when the device regions are not damaged by more than 1, the image sensor chip is a good product that can be used, the utilization rate of the substrate is improved, the yield is increased, and the manufacturing cost of the image sensor is reduced by a simple method. Meanwhile, the image sensor chips with different resolutions may also be formed for the number of pixel array units used in the chip area, i.e., the greater the number of uses, the higher the resolution of the formed image sensor.
Furthermore, whether the second cutting is carried out or not is selected according to the damage degree of the device area in the chip area, so that when the second cutting is carried out, the undamaged device area forms a chip with lower resolution which can be used, the utilization rate of the substrate is improved, and the yield is increased; when the second cutting is not carried out, the chip comprises more undamaged device areas, and the image sensor chip is ensured to have higher resolution.
Accordingly, the image sensor chip in the technical scheme of the invention has the advantages that due to the adoption of the forming method, the utilization rate of the substrate is improved, the yield is increased, the manufacturing cost is reduced, the management convenience is improved, and meanwhile, various resolutions can be met according to different requirements.
Drawings
FIG. 1 is a schematic diagram of a top view of a wafer with image sensor chips;
FIG. 2 is an enlarged partial view of a region A in the wafer of FIG. 1;
FIG. 3 is a schematic diagram of a chip region in a region A of the wafer of FIG. 1;
FIG. 4 is a schematic diagram illustrating a top view of a semiconductor structure in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of the structure of the chip region of FIG. 4;
FIG. 6 is a schematic diagram of a functional unit distribution of one of the device regions of FIG. 5;
FIG. 7 is a schematic diagram illustrating a top view of another semiconductor structure in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram of the structure of the chip region of FIG. 7;
FIG. 9 is a flow chart illustrating a method of forming an image sensor chip according to an embodiment of the invention;
FIG. 10 is a flow chart illustrating a method of forming a plurality of independent chips according to an embodiment of the present invention;
FIG. 11 is a flow chart illustrating another method for forming a plurality of independent chips according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an image sensor chip according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of another image sensor chip according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of another image sensor chip according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of an image sensor according to an embodiment of the present invention;
FIG. 16 is a schematic diagram of another image sensor according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of another image sensor according to an embodiment of the present invention.
Detailed Description
As described in the background art, it is necessary to improve the yield of an image sensor and reduce the manufacturing cost of an image sensor chip.
Fig. 1 is a schematic top view of a wafer with image sensor chips, fig. 2 is a partially enlarged view of a region a in the wafer of fig. 1, and fig. 3 is a schematic structural view of a chip region in the region a in the wafer of fig. 1.
Referring to fig. 1 to 3, the wafer with image sensor chips includes: a wafer 100, wherein the wafer 100 includes a plurality of independent chip regions 101 separated from each other; the individual chip region 101 includes: an independent chip area pixel array unit 103, an independent chip area comparison loop unit 104, an independent chip area timing and control unit 105, an independent chip area memory unit 106, an independent chip area row selection unit and column selection unit 107, an independent chip area data transmission unit 111, an independent chip area phase locking loop unit 110, an independent chip area signal conversion unit 108 and an independent chip area ramp generator unit 109.
Wherein the arrangement directions of the independent chip regions on the wafer 100 are consistent.
In the above method, since each image sensor chip can only be used individually, if a chip is partially damaged or failed due to some processing or other reasons during the formation, an entire chip is failed, that is, a chip is actually lost, so that the yield is reduced, and the manufacturing cost is increased.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, a method for forming an image sensor chip, and an image sensor, which can solve the problem of damage or failure of an entire image sensor chip due to partial damage of an image sensor chip, thereby improving the utilization rate of a substrate, i.e., a wafer in the above method, increasing the yield of the chip in the manufacturing process, and saving the design and manufacturing costs in the manufacturing process of the chip.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of a chip region of fig. 4, and fig. 6 is a schematic functional unit distribution diagram of a device region of fig. 5.
Referring to fig. 4, the semiconductor structure includes:
a substrate 201, wherein the substrate 201 comprises a plurality of chip regions 202 which are mutually separated; each of the chip regions 202 includes more than 4 discrete device regions, each of the device regions includes a pixel array unit, and at least 2 pixel array units are adjacent to each other in each of the chip regions 202.
The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 4, in the present embodiment, the substrate 201 is a wafer, and the material of the wafer is silicon. In other embodiments, the substrate 201 material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
The substrate 201 includes a number of chip regions 202, and the chip regions 202 are discrete from each other.
Referring to fig. 4 and fig. 5, in the present embodiment, the chip region 202 includes 4 device regions, and the four device regions are arranged in a 2 × 2 array. The four device regions are respectively a first device region 203, a second device region 205, a third device region 207 and a fourth device region 209 according to different arrangement positions. The first device region 203, the second device region 205, the third device region 207, and the fourth device region 209 are discrete from one another; the first device region 203, the second device region 205, the third device region 207, and the fourth device region 209 are arranged in a central symmetry manner with the center of the chip region 202 as a symmetry center.
With continued reference to fig. 4 and 5, each of the device regions includes 1 pixel array unit. Specifically, the first pixel array unit 204 is provided in the first device region 203, the second pixel array unit 206 is provided in the second device region 205, the third pixel array unit 208 is provided in the third device region 207, and the fourth pixel array unit 210 is provided in the fourth device region 209.
The first pixel array unit 204 is adjacent to the second pixel array unit 206 and the third pixel array unit 208, the second pixel array unit 206 is adjacent to the first pixel array unit 204 and the fourth pixel array unit 210, and the third pixel array unit 208 is adjacent to the first pixel array unit 204 and the fourth pixel array unit 2010.
Therefore, the pixel array units in the chip area 202 form a pixel array unit combination in the middle of the chip area 202 to obtain higher resolution.
Referring to fig. 5, a first channel 215 is formed between the chip regions 202 (shown in fig. 4) that are separated from each other; a second channel 216 is provided in the chip region 202 between the first device region 203, the second device region 205, the third device region 207 and the fourth device region 209 (as shown in fig. 4). A cutting process can be performed on the first channel 215 and the second channel 216.
Since the substrate 201 has the first channel 215 and the second channel 216 that can be used for dicing, damage to the chip region 202, the first device region 203, the second device region 205, the third device region 207, or the fourth device region 209 due to dicing is reduced when the dicing process is performed.
For the semiconductor structure of this embodiment, according to the requirement for the resolution of the image sensor chip, the dicing can be flexibly selected only between the adjacent chip regions 202 to form a plurality of mutually independent chip regions 202 to form the image sensor chip; or further cutting in the chip region 202 to form the first device region 203, the second device region 205, the third device region 207 and the fourth device region 209 which are independent of each other, so as to form an image sensor chip. And furthermore, the substrate 201 has a more flexible cutting mode, and meets the requirements of various resolutions without increasing the cost when designing and manufacturing the image sensor chip by using a simple semiconductor structure.
Referring to fig. 6, the first device region 203 includes not only the first pixel array unit 204, but also functional units: a timing and control unit 231, a comparison loop unit 238, a memory unit 232, a column selection unit and row selection unit 233, a data transmission unit 234, a phase-locked loop unit 235, a signal conversion unit 236, and a ramp generator unit 237.
In this embodiment, the second device region 205, the third device region 207 and the fourth device region 209 in the chip region 202 include the same functional units as the first device region 203, and the functional units are arranged in the chip regions in a central symmetry manner with the center of the chip region 202 as a symmetry center.
In an embodiment, the memory unit 232 of the device region 203 further includes a One Time Programmable (OTP) memory, and during a subsequent process of forming an image sensor chip, preset operation programs are written into the image sensor chip in a One Time programming manner, so that the operation programs are in One-to-One correspondence with the image sensors having different resolutions, and the image sensor chip cannot be randomly rewritten, thereby maintaining normal operation of the image sensors.
Fig. 7 is a schematic top view of another semiconductor structure according to an embodiment of the invention, and fig. 8 is a schematic structure of the chip region of fig. 7.
Referring to fig. 7, in the present embodiment, the semiconductor structure includes a substrate 301, the substrate 301 includes a plurality of chip regions 302 separated from each other, each chip region 302 includes 9 device regions separated from each other, and each device region includes a pixel array unit.
Referring to fig. 8, specifically, in the chip region 302, the device regions are arranged in a 3 × 3 array, and the 9 device regions are a first device region 303, a second device region 305, a third device region 307, a fourth device region 309, a fifth device region 311, a sixth device region 313, a seventh device region 315, an eighth device region 317, and a ninth device region 319, respectively, according to different arrangement positions. The first device region 303, the second device region 305, the third device region 307, and the fourth device region 309 are arranged in a 2 × 2 array, and are arranged in a central symmetry manner.
With reference to fig. 8, in the present embodiment, the first device region 303 includes a first pixel array unit 304, the second device region 305 includes a second pixel array unit 306, the third device region 307 includes a third pixel array unit 308, the fourth device region 309 includes a fourth pixel array unit 310, the fifth device region 311 includes a fifth pixel array unit 312, the sixth device region 313 includes a sixth pixel array unit 314, the seventh device region 315 includes a seventh pixel array unit 316, the eighth device region 317 includes an eighth pixel array unit 318, and the ninth device region 319 includes a ninth pixel array unit 320.
The first pixel array unit 304 is adjacent to the second pixel array unit 306 and the third pixel array unit 308 respectively, the second pixel array unit 306 is adjacent to the first pixel array unit 304 and the fourth pixel array unit 310 respectively, and the third pixel array unit 308 is adjacent to the first pixel array unit 304 and the fourth pixel array unit 310 respectively, so as to form a first pixel array unit combination; the fifth pixel array unit 312 is adjacent to the sixth pixel array unit 314 to form a second pixel array unit; the seventh pixel array unit 316 is adjacent to the eighth pixel array unit 318 to constitute a third pixel array unit.
In the present embodiment, the chip area 302 includes 1 first pixel array unit combination having 4 pixel array units, a second pixel array unit combination and a third pixel array unit combination having 2 pixel array units, and a separate pixel array unit 320. By using the first pixel array unit combination, the second pixel array unit combination, the third pixel array unit combination and the single pixel array unit 320 in cooperation, higher resolution can be obtained.
In other embodiments, the number of device regions in the chip region 302 is other than 4, such as 8, 12, or 16.
Accordingly, fig. 9 is a schematic flowchart of a method for forming an image sensor chip using the semiconductor structure according to an embodiment of the present invention, including:
step S100, providing a semiconductor structure;
step S200, detecting a plurality of chip areas to obtain detection result information corresponding to each chip area;
and step S300, cutting the substrate according to the detection result information of the chip areas to form a plurality of mutually independent chips, wherein each chip comprises at least 1 device area.
The following description is made with reference to the accompanying drawings.
Referring to fig. 4, a semiconductor structure is provided.
The semiconductor structure is as described in fig. 4 to fig. 6 and the related description of the preceding embodiments, and is not repeated herein.
With reference to fig. 4, the chip regions 202 on the substrate 201 are detected, and the detection result information corresponding to each chip region 202 is obtained.
In this embodiment, a method for inspecting the chip regions 202 on the substrate 201 and obtaining the inspection result is a chip bonding (CP).
The detection result information includes the number of damages of the device region within the chip region 202; or an undamaged number of device regions within the chip region 202; or a damage ratio including the chip region 202, the damage ratio being a ratio of a number of damaged device regions within the chip region 202 to a total number of device regions within the chip region 202; or an undamaged proportion comprising the chip area 202, the undamaged proportion being the ratio of the number of undamaged device areas within the chip area 202 to the total number of device areas within the chip area 202.
Since the detection result information includes a plurality of types of information, it is possible to flexibly cope with different manufacturing apparatuses at the time of actual production and manufacturing by changing the type of the detection result information in the process of forming the chip.
In this embodiment, after step S200 and before step S300, according to the detection result information, the running programs corresponding to the finally formed chips with different resolution types are written into the chips. Specifically, the method for writing the running program into the chip comprises the following steps: after the detection result information is obtained, the number of the device regions 203 which can be used in the chip finally formed after cutting is judged; and writing the corresponding program into the chip according to the number of the usable device areas in the chip. Thereby ensuring that the chip is able to function properly and achieve the required resolution.
In another embodiment, after the step S300, according to the detection result information, a preset running program corresponding to the finally formed chip type with different resolutions is written into the chip.
Subsequently, the step S300 is executed, and the substrate 201 is cut according to the detection result information of the chip regions 202 to form a plurality of mutually independent chips, wherein each chip at least includes 1 device region. Please refer to fig. 10 to fig. 13.
Fig. 10 is a flow chart of a method for forming a plurality of independent chips according to an embodiment of the present invention, including:
step S301a, performing first cutting between adjacent chip regions to form a plurality of mutually independent chip regions;
step S302a, judging whether the number of the damaged device areas in the chip area is more than 1;
when the number of the damages is larger than 1, executing step S303a, performing second cutting on the chip regions to make a plurality of device regions independent from each other, and forming a plurality of independent first chips including 1 device region;
when the number of the damages is not more than 1, that is, the number of the damages is 1 or 0, a plurality of independent second chips including 4 device regions are directly formed after the first cutting.
The following description is made with reference to the accompanying drawings.
Referring to fig. 4, a first cut is performed between adjacent chip regions 202 to form a plurality of independent chip regions 202.
The first cut is a cut of the substrate 201 along the first channel 215. Since the first dicing is performed along the first trench 215, damage to the chip region 202 due to dicing is reduced.
Referring to fig. 4, it is determined whether the number of damaged device regions in the chip region 202 is greater than 1. Specifically, it is determined whether the numbers of damages of the first device region 203 (shown in fig. 5), the second device region 205 (shown in fig. 5), the third device region 207 (shown in fig. 5) and the fourth device region 209 (shown in fig. 5) in the chip region 202 are greater than 1.
In this embodiment, after the first dicing, it is determined whether the number of the damaged device regions in the chip region 202 is greater than 1.
In another embodiment, the first dicing is performed after determining whether the number of the damaged device regions in the chip region 202 is greater than 1.
Referring to fig. 12, when the number of the damaged device regions is greater than 1, step S303a is performed to perform a second dicing on the chip region 202 to make a plurality of device regions independent from each other, even if the first device region 203 (shown in fig. 5), the second device region 205 (shown in fig. 5), the third device region 207 (shown in fig. 5) and the fourth device region 209 (shown in fig. 5) in the chip region 202 are independent from each other, so as to form a plurality of independent first chips 250 including 1 device region.
The second dicing is to dice the chip region 202 along the second channel 216 (as shown in fig. 5). Damage to the device region from dicing is reduced due to the second cut along the second channel 216.
In an embodiment, after the first chip 250 is formed, the method for forming the image sensor chip further includes: and packaging the first chip.
Referring to fig. 13, when the number of the device regions damaged is not greater than 1, that is, the number of the device regions damaged is 1 or 0, several independent second chips 260 including 4 device regions are directly formed after the first cutting, that is, independent second chips 260 including the first device region 203, the second device region 205, the third device region 207, and the fourth device region 209 are formed.
In an embodiment, after the second chip 260 is formed, the method for forming the image sensor chip further includes: the second chip 260 is packaged.
In this embodiment, only the number of the damaged device regions needs to be determined, that is, only counting is needed in the determination process, so that the determination procedure for manufacturing the chip can be simplified, the calculation time of the determination procedure can be reduced, and the manufacturing time can be reduced.
Meanwhile, different independent chips, namely the first chip 250 and the second chip 260, are formed according to the damage condition of the device region in the chip region 202, so that the packaging process for the damaged device region is reduced when the packaging process is performed, and the manufacturing cost is further reduced.
Fig. 11 is a schematic flow chart of another embodiment of a method for forming a plurality of independent chips according to the embodiment of the present invention, including:
step S301b, performing first cutting between adjacent chip regions to form a plurality of mutually independent chip regions;
step S302b, judging whether the damage proportion is more than 1/3;
when the damage ratio is greater than 1/3, performing step S303b, performing a second dicing on the chip regions to make the device regions independent from each other, and forming a plurality of independent first chips including 1 device region;
when the damage ratio is less than or equal to 1/3, a plurality of independent second chips including 4 device regions are directly formed after the first cutting.
The following description is made with reference to the accompanying drawings.
Referring to fig. 4, a first cut is performed between adjacent chip regions 202 to form a plurality of independent chip regions 202.
The first cut is a cut of the substrate 201 along the first channel 215. Since the first dicing is performed along the first trench 215, damage to the chip region 202 due to dicing is reduced.
With continued reference to fig. 4, it is determined whether the damage ratio is greater than 1/3.
In the present embodiment, after the first cutting, it is determined whether the damage ratio is greater than 1/3.
In another embodiment, the first cut is performed after determining whether the damage ratio is greater than 1/3.
Referring to fig. 12, when the damage ratio is greater than 1/3, step S303b is performed to perform a second dicing on the chip region 202 to make a plurality of device regions independent from each other, even if the first device region 203 (as shown in fig. 5), the second device region 205 (as shown in fig. 5), the third device region 207 (as shown in fig. 5) and the fourth device region 209 (as shown in fig. 5) in the chip region 202 are independent from each other, so as to form a plurality of independent first chips 250 including 1 device region.
In an embodiment, after the first chip 250 is formed, the method for forming the image sensor chip further includes: the first chip 250 is packaged.
Referring to fig. 13, when the damage ratio is smaller than or equal to 1/3, several independent second chips 260 including 4 device regions are directly formed after the first cutting, that is, independent second chips 260 including the first device region 203, the second device region 205, the third device region 207, and the fourth device region 209 are formed.
In an embodiment, after the second chip 260 is formed, the method for forming the image sensor chip further includes: the second chip 260 is packaged.
By the above method for forming a plurality of mutually independent chips, as long as one device region in the chip region 202 is not damaged, that is, as long as one device region in the first device region 203, the second device region 205, the third device region 207 and the fourth device region 209 in the chip region 202 is not damaged, at least one usable and good chip can be formed, thereby improving the yield in the manufacturing process and simultaneously improving the utilization rate of the substrate 201.
Meanwhile, since the first dicing or the second dicing is determined according to the detection result information, that is, the damage condition of the device region in the chip region 202, one or more of the first chip 250 or the second chip 260 is formed, and different image sensors can be manufactured to correspond to different resolution requirements while controlling the manufacturing cost.
Specifically, when the chip is the first chip 250, since the first chip 250 includes only one pixel array unit, an image sensor with a lower resolution and a lower manufacturing cost can be manufactured; when the chip is the second chip 260 and the second chip 260 has a damaged device region, the damaged device region is backed up by using an undamaged device region, and a plurality of undamaged pixel array units in the second chip 260 are used in a matching manner, so that an image sensor with higher resolution can be manufactured; when the chip is the second chip 260 and all device regions in the second chip 260 are not damaged, the image sensor with the highest resolution can be manufactured by using all pixel array units in the second chip 260 in a matching manner.
Referring to fig. 14 in addition to fig. 7, in another embodiment, the chip region 302 (shown in fig. 7) includes 9 device regions, so that after the first cutting, a third chip 360 including 9 device regions is formed.
Compared to forming the second chip 260 including 4 device regions, since the third chip 360 includes 9 device regions, that is, the third chip 360 includes more pixel array units, an image sensor with higher resolution can be manufactured. Accordingly, an embodiment of the present invention further provides an image sensor chip formed by the method for forming an image sensor chip, please refer to fig. 12, which includes: a device region including a pixel array unit.
Accordingly, another image sensor chip formed by the method for forming an image sensor chip according to the embodiment of the present invention is provided, with reference to fig. 13, including: the chip area 202 comprises 4 device areas, the 4 device areas are a first device area 203, a second device area 205, a third device area 207 and a fourth device area 209, the 4 device areas are arranged in a central symmetry mode by taking the center of the chip area 202 as a symmetry center, each device area comprises a pixel array unit, and the pixel array units of the adjacent device areas are adjacent.
Accordingly, another image sensor chip formed by the method for forming an image sensor chip is provided in an embodiment of the present invention, with reference to fig. 14, including: a chip area 302, the chip area 302 including 9 device areas, the device areas being arranged in a 3 × 3 array, each of the device areas including a pixel array unit. The device region of the chip region 302 includes 4 device regions that are adjacent to each other and arranged in a 2 × 2 array, and the pixel array units of the 4 device regions that are adjacent to each other and arranged in a 2 × 2 array are adjacent to each other. The chip region 302 further includes 2 sets of 2 adjacent device regions, the pixel array elements of the 2 sets of 2 adjacent device regions being adjacent.
Accordingly, an embodiment of the present invention further provides an image sensor, please refer to fig. 15, including: an image sensor chip (as shown in fig. 12); the lens 410 is arranged on the image sensor chip, the lens 410 has a projection pattern on the image sensor chip, and the pixel array unit 204 in the image sensor chip is within the range of the projection pattern.
In this embodiment, since only one pixel array unit 204 needs to be within the projection pattern of the first lens 410, the volume of the first lens 410 is small, and the material cost of the lens is reduced.
Accordingly, another image sensor is provided in the embodiments of the present invention, please refer to fig. 16, which includes: an image sensor chip (shown in fig. 13); the lens 420 is arranged on the image sensor chip, the lens 420 has a projection pattern on the image sensor chip, and the first pixel array unit 204, the second pixel array unit 206, the third pixel array unit 208 and the fourth pixel array unit 210 in the image sensor chip are within the range of the projection pattern.
In this embodiment, since the pixel array unit combinations composed of the 4 pixel array units of the image sensor chip have the same structure, no matter how many pixel array units are used in the image sensor chip, the size of the lens disposed on the image sensor chip may be the same, so that one type of lens can be used to correspond to the image sensor chip having different resolutions, thereby reducing the types of lenses, facilitating the design of lens modules, reducing the number of molds and other devices required for manufacturing lenses, and improving the convenience of management during production.
Accordingly, another image sensor is provided in the embodiments of the present invention, please refer to fig. 17, which includes: an image sensor chip (shown in fig. 14); the image sensor chip is provided with a lens 430, the lens 430 has a projection pattern on the image sensor chip, and the first pixel array unit 304, the second pixel array unit 306, the third pixel array unit 308, the fourth pixel array unit 310, the fifth pixel array unit 312, the sixth pixel array unit 314, the seventh pixel array unit 316, the eighth pixel array unit 318 and the ninth pixel array unit 320 in the image sensor chip are within the range of the projection pattern.
In this embodiment, since the image sensor includes 9 pixel array units, more different resolutions can be formed by combining the image sensor with 4 pixel array units, and therefore, more image sensor chips with different resolutions can be provided by one lens type, i.e., the lens 430.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A method of forming an image sensor chip, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: the chip region comprises a plurality of mutually-separated chip regions, a first channel is arranged between the mutually-separated chip regions, and a cutting process can be carried out on the first channel; each chip area comprises more than 4 discrete device areas, each device area comprises pixel array units, at least 2 pixel array units are adjacent in each chip area, second channels are arranged in the discrete device areas, and a cutting process can be carried out on the second channels;
detecting a plurality of chip areas to obtain detection result information corresponding to each chip area, wherein the detection result information comprises the damage number of the device areas in the chip area, or the detection result information comprises the damage proportion of the chip area, and the damage proportion is the proportion of the number of the damaged device areas in the chip area to the total number of the device areas;
cutting the substrate according to the detection result information of the chip areas to form a plurality of mutually independent chips, wherein each chip comprises at least 1 device area, and the method for forming the plurality of mutually independent chips comprises the following steps: performing first cutting between adjacent chip areas to form a plurality of mutually independent chip areas; and judging whether the chip area is subjected to second cutting after the first cutting according to the detection result information.
2. The method of claim 1, wherein each of the chip regions comprises 4 adjacent device regions, the 4 adjacent device regions are arranged in a 2 x 2 array, the 4 adjacent device regions are arranged in a central symmetry, and the pixel array units of the 4 adjacent device regions are adjacent.
3. The method of claim 2, wherein the number of the device regions in each of the chip regions is 4.
4. The method of claim 2, wherein the number of device regions in each of the chip regions is greater than 4.
5. The method of claim 1, wherein the device region further comprises: the device comprises a timing and control unit, a comparison loop unit, a memory unit, a column selection unit, a row selection unit, a data transmission unit, a phase locking loop unit, a signal conversion unit and a ramp generator unit.
6. The method of forming an image sensor chip according to any one of claims 1 to 5, further comprising: and arranging a lens on the chip, wherein the lens has a projection pattern on the chip, and the pixel array unit in the chip is in the range of the projection pattern.
7. The method of forming an image sensor chip according to any one of claims 1 to 5, further comprising: and carrying out a packaging process on the chip.
8. The method of forming an image sensor chip according to any one of claims 1 to 5, wherein the chip region includes 4 device regions; the method for forming a plurality of mutually independent chips further comprises the following steps: and when the detection result information comprises the damage number of the device areas in the chip area and the damage number is more than 1, performing second cutting on the chip area to enable a plurality of device areas in the chip area to form mutually independent device areas.
9. The method of forming an image sensor chip according to any one of claims 1 to 5, wherein the method of forming a plurality of chips independent of each other further comprises: and when the detection result information comprises the damage ratio and the damage ratio is larger than 1/3, performing second cutting on the chip area to enable a plurality of device areas in the chip area to form mutually independent device areas.
10. An image sensor chip formed by the method of any one of claims 1 to 9.
11. An image sensor, comprising: the image sensor chip of claim 10.
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| CN1463036A (en) * | 2001-07-10 | 2003-12-24 | 株式会社东芝 | Chip of memory, chip-on-chip device of using same and its mfg. method |
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| CN102983144B (en) * | 2012-11-30 | 2015-02-11 | 格科微电子（上海）有限公司 | Wafer level packaging method of image sensor |
| US9012245B1 (en) * | 2014-09-22 | 2015-04-21 | Xilinx, Inc. | Methods of making integrated circuit products |
| US10032682B1 (en) * | 2016-11-22 | 2018-07-24 | Xilinx, Inc. | Multi-die wafer-level test and assembly without comprehensive individual die singulation |
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| CN1463036A (en) * | 2001-07-10 | 2003-12-24 | 株式会社东芝 | Chip of memory, chip-on-chip device of using same and its mfg. method |
| CN108242450A (en) * | 2016-12-23 | 2018-07-03 | 三星电子株式会社 | Imaging sensor and its manufacturing method |
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